JP2000269804A - Level conversion circuit and semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To achieve high-speed level conversion and low current consumption. In a level conversion circuit for transmitting a signal from a positive low potential side to a positive high potential side, a one-shot pulse generation circuit (13) for generating a one-shot pulse signal synchronized with an edge at the time of transition of an input signal. ) And a forced pull-up circuit (10) for forcibly pulling up a signal transmission node on the positive high potential side based on the generated one-shot pulse. The forced pull-up circuit
By applying a pulse signal synchronized with the edge at the time of transition of the input signal, the signal transmission node on the positive high potential side is forcibly pulled up. Due to this forced pull-up, the output logic at the time of transition of the input signal is inverted at high speed, which achieves high-speed level conversion and low current consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for improving a level conversion circuit, and more particularly to a technique effective when applied to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, an internal power supply voltage, for example, 5 V, is stepped down to 2.5 V in an internal circuit of the semiconductor integrated circuit and supplied to an internal function module. In addition, the processing result of the 2.5 V circuit in the semiconductor integrated circuit is 5 V
It may be externally output to the system circuit. In such a case, it is necessary to adjust the DC level.
A level conversion (level shift) circuit is provided. The level conversion circuit includes a circuit that propagates a signal from a positive low voltage side to a positive high voltage side and a circuit that propagates a signal from a negative low voltage side to a negative high voltage side.

As an example of a document describing DC level conversion, there is an "LSI Handbook (page 804)" issued by Ohm Corporation in 1983.

[0004]

The inventors of the present invention have studied the conventional level conversion circuit. As a result, the fall is slow when the rise is fast, and the rise is slow when the fall is fast due to the circuit configuration. It has been found that the level conversion time becomes longer in any case. In addition, since the rise or fall time (gradient) of the output of the level conversion circuit is long (large), a large through current flows in the next-stage gate receiving this. Further, when the voltage level difference is large in the level conversion, the conversion circuit itself may not operate normally, which prevents the reliability of the level conversion circuit from being improved.

An object of the present invention is to achieve high-speed level conversion and low current consumption.

Another object of the present invention is to improve reliability.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, as a first means, in a level conversion circuit for transmitting a signal from a positive low potential side to a positive high potential side, a one-shot pulse signal synchronized with an edge at the time of transition of an input signal is generated. A one-shot pulse generation circuit (13, 33) and a pulse signal generated by the one-shot pulse generation circuit are applied, thereby forcibly pulling up a signal transmission node on the positive high potential side. Circuits (10, 30).

According to the first means, the forcible pull-up circuit forcibly pulls the signal path on the positive high potential side by applying the one-shot pulse signal generated by the one-shot pulse generation circuit. Up. By this forced pull-up, the output logic at the time of transition of the input signal is inverted at high speed, and this is reflected in the inversion of the output logic. This achieves faster level conversion. At this time, the forcible pull-up circuit includes a resistance means (102, 302) coupled to a positive high-potential-side power supply, and a one-shot pulse output from the one-shot pulse generation circuit connected in series to the resistance means. A first transistor (103, 303) whose operation is controlled by the resistance means and the first transistor.
It can be easily configured to include a second transistor (101, 301) for supplying a positive high potential to the signal path based on the potential of the series connection node of the transistors.

As a second means, in a level conversion circuit for transmitting a signal from a negative low potential side to a negative high potential side, a one-shot pulse for generating a one-shot pulse signal synchronized with an edge at the time of transition of an input signal is provided. Pulse generation circuit (5
3, 73) and a forced pull-down circuit (50, 70) for forcibly pulling down a signal path on the negative high potential side by applying a pulse signal generated by the one-shot pulse generation circuit. .

According to the second means, the forced pull-down circuit forcibly pulls down the signal path on the negative high potential side by applying a pulse signal synchronized with the edge at the time of transition of the input signal. Due to this forced pull-down, the output logic at the time of transition of the input signal is inverted at a high speed, and this achieves a high-speed level conversion. At this time, the forcible pull-down circuit includes a resistance means (502, 702) coupled to the negative high potential side power supply and a one-shot pulse output from the one-shot pulse generation circuit connected in series to the resistance means. A third transistor (503, 703) whose operation is controlled, and a fourth transistor (501, 701) for supplying a negative high potential to the signal path based on the potential of the series connection node of the resistance means and the third transistor. ) Can be easily included.

When a semiconductor integrated circuit is configured to include such a level conversion circuit, the level conversion time is shortened, so that the time required for signal exchange between internal circuits via the level conversion circuit is reduced. Achieving shortening.

[0013]

FIG. 15 shows a configuration example of a semiconductor integrated circuit according to the present invention.

The semiconductor integrated circuit shown in FIG. 15 is not particularly limited, but includes a power supply circuit 151 and a RAM (random access memory).
Access memory) 152, CPU (central processing unit) 1
53, a level shift circuit 154, and a logic circuit 155.
It is formed on one semiconductor substrate such as a single crystal silicon substrate. The power supply circuit 151 has a power supply voltage V supplied from the outside.
Generate VCL = 2.5V based on CC = 5V.
This VCL = 2.5V corresponds to the RAM 152 and the CPU 1
53 are supplied as operating voltages thereof. CPU
153 executes a predetermined arithmetic processing according to a predetermined program. The RAM 153 stores the CPU 1
It is used as a work area in the arithmetic processing of 53. C
The signal output from the PU 153 is a 2.5 V system,
It is converted to a 5V system by a level conversion circuit 154 and then output externally. Also, the logic circuit 156 basically has V
Since the operation is performed using CC = 5V as a power supply, the CPU 1
A level conversion circuit 156 for converting the 2.5V system signal from 53 into a 5V system signal is included.

The level conversion circuits 154 and 155 have the same configuration.

FIG. 1 shows a configuration example of the level conversion circuit 154.

An inverter 11 for inverting a signal input via input node IN is provided.
An inverter 12 for inverting one output logic is provided. Although not particularly limited, the inverters 11 and 12 are supplied with a high-potential-side power supply VCL = 2.5 V for operation. The low potential side is set to the ground level.

A p-channel MOS transistor 14 and an n-channel MOS transistor 15 are connected in series, and a p-channel MOS transistor 16 and an n-channel MOS transistor 17 are connected in series. Then, a series connection node (indicated by P) of the p-channel MOS transistor 14 and the n-channel MOS transistor 15 is coupled to the gate electrode of the p-channel MOS transistor 16,
A series connection node of transistor 16 and n-channel MOS transistor 17 is coupled to the gate electrode of p-channel MOS transistor 14. The source electrodes of the p-channel MOS transistors 14 and 16 are coupled to a high potential side power supply VCH = 5V. Also, n
The source electrodes of the channel type MOS transistors 15 and 17 are connected to a ground line.

The p-channel type MOS transistor 1
An output signal of the level conversion circuit is obtained from a series connection node of the MOS transistor 6 and the n-channel MOS transistor 17.

Further, a one-shot pulse generating circuit 13 for generating a one-shot pulse signal based on the output signal of the inverter 11 is provided. This one-shot pulse generation circuit 13 is not particularly limited, but includes an inverter 131 and a NOR gate 132 coupled to each other. Input terminal of inverter 131 and NOR gate 1
32 has one input terminal coupled to the output terminal of the inverter 11. When the output logic of the inverter 11 transitions from a high level to a low level, the output node A of the one-shot pulse generation circuit 13
1, a one-shot pulse signal having a pulse width determined by the signal delay is output.

Based on the one-shot pulse signal generated by the one-shot pulse generation circuit 13, the output node O of the high potential side signal path in the level conversion circuit 154 is output.
A forced pull-up circuit 10 for forcibly pulling up the UT is provided. This forced pull-up circuit 10
Although not particularly limited, a p-channel MOS transistor 101, a resistor 102, and an n-channel MOS transistor 103 are combined. The resistor 102 is an example of a resistor in the present invention, and is formed of polysilicon, and is a channel type MOS transistor 1.
01 and one terminal of the resistor 102 are coupled to the high potential side power supply VCH = 5V. Then, the potential of the series connection node of the resistor 102 and the n-channel MOS transistor 103 is transmitted to the gate electrode of the p-channel MOS transistor 101.

Here, the gate width and the gate length of the p-channel type MOS transistor are denoted by “Wp” and “L”, respectively.
p ”, the driving force βp of the p-channel MOS transistor is

[0023]

## EQU1 ## βp = Wp / Lp. Assuming that the driving force of the p-channel MOS transistor 16 is “βp1” and the driving force of the p-channel MOS transistor 101 is “βp2”,

[0024]

## EQU2 ## The constants of the p-channel MOS transistors 16 and 101 are set so that the relationship of βp1 << βp2 holds. In other words, the constant of the MOS transistor is set such that the driving force of the p-channel MOS transistor 101 is sufficiently larger than that of the p-channel MOS transistor 16.

The operation of the above configuration will be described.

FIG. 2A shows an operation waveform of a main part in the circuit shown in FIG. 1, and FIG.
5 shows operation waveforms when the one-shot pulse generation circuit 13 and the forced pull-up circuit 10 are not provided.

If the one-shot pulse generation circuit 13 and the forced pull-up circuit 10 are not provided in FIG. 1, the logic of the input node IN transitions from low to high as shown in FIG. The rising of the waveform at the output node OUT is delayed as compared with the falling. This is because the driving capability of the p-channel MOS transistor 16 is set smaller than that of the n-channel MOS transistor 17.

Therefore, in the circuit configuration shown in FIG. 1, the one-shot pulse generation circuit 13 and the forced pull-up circuit 1
By providing 0, as shown in FIG. 2A, the rising speed of the output node OUT is increased. That is, when the logic of the input node IN transitions from low level to high level, the one-shot pulse generation circuit 13
Generates a one-shot pulse signal. While this one-shot pulse signal is at a high level, n
The channel type MOS transistor 103 is turned on, whereby the p-channel type MOS transistor 101
Is turned on. Thereby, the signal path on the high potential side is forcibly pulled up. This forced pull-up period is equal to the high-level period of the node A, that is, the high-level period of the one-shot pulse signal. By this forced pull-up, the output logic of the level conversion circuit 154 is inverted at high speed. In other words, the p-channel MOS transistor 101 is turned on, thereby forcibly pulling up the signal path on the high-potential side, so that the output node OU
The rise characteristic of T is improved, and the rise of the output waveform is accelerated.

According to the above example, the following effects can be obtained.

(1) A forced pull-up circuit 10 for forcibly pulling up a signal transmission node on the positive high potential side is provided by applying a pulse signal synchronized with an edge at the time of transition of an input signal. When the input node IN transitions from the low level to the high level, the signal transmission node on the positive high potential side is forcibly pulled up, and the output logic at the time of transition of the input signal is rapidly inverted by this forced pull-up. Thus, the rising characteristics of the output waveform are improved, and the level conversion is speeded up.

(2) When the n-channel MOS transistor 103 is turned on by the output signal of the one-shot pulse generation circuit 13, a through current flows through the resistor 102. Since the high-potential-side power supply VCH is lowered by this through current, a substantial potential difference for level conversion is reduced, and as a result, the circuit operation can be speeded up and stabilized.

(3) The through current flowing through the forced pull-up circuit can be controlled by the one-shot pulse width and the resistance value of the resistor 102, and is suppressed to be lower than the through current at the next stage gate of the conventional level conversion circuit. Therefore, the current consumption of the entire circuit can be reduced.

FIG. 3 shows another configuration example of the level conversion circuit 154 according to the present invention.

An inverter 31 for inverting a signal input through input node IN is provided.
An n-channel MOS transistor 32 for transmitting one output logic to the subsequent circuit is provided. Although not particularly limited, the inverter 31 is supplied with a high potential side power supply VCL = 2.5 V for operation. The low potential side is set to the ground level. The high potential side power supply VCL = is also applied to the gate electrode of the n-channel MOS transistor 32.
2.5V is supplied.

An inverter is formed by connecting the p-channel MOS transistor 35 and the n-channel MOS transistor 36 in series. p-channel type M
The source electrode of the OS transistor 35 is a high potential side power supply VC.
H, the n-channel MOS transistor 36
Are coupled to the ground line. Also, p
A series connection node of the channel type MOS transistor 35 and the n-channel type MOS transistor 36 is an output node of this level conversion circuit. p-channel type M
The gate electrodes of the OS transistor 35 and the n-channel MOS transistor 36 are set to a node Q, and an input signal is transmitted to the node Q via the n-channel MOS transistor 32. Further, a p-channel MOS transistor 34 for pull-up is provided at the node Q. The source electrode of this p-channel MOS transistor is coupled to a high potential side power supply VCH,
The signal of the output node OUT is fed back to the gate electrode.

Further, a one-shot pulse generation circuit 33 for generating a one-shot pulse signal based on the signal logic of the input node IN is provided. The one-shot pulse generation circuit 33 is not particularly limited, but includes an inverter 331 and a NOR gate 332 coupled to each other. Input terminal of inverter 331 and NOR gate 332
Is connected to the output terminal of the inverter 31. When the signal logic of the input node IN transitions from low level to high level, a one-shot pulse signal having a pulse width determined by the signal delay in the inverter 331 is output to the output node A of the one-shot pulse generation circuit 13. Is done.

A forced pull-up circuit 30 for forcibly pulling up the signal path on the high potential side in the level conversion circuit 154 based on the one-shot pulse signal generated by the one-shot pulse generation circuit 33 is provided. . The forced pull-up circuit 30 includes, but is not limited to, a p-channel MOS transistor 301 and a resistor 3
02 and an n-channel MOS transistor 303. The resistor 302 is an example of a resistor in the present invention, and is not particularly limited, but is formed of polysilicon. The source electrode of the p-channel MOS transistor 301 and one terminal of the resistor 302
It is coupled to the high potential side power supply VCH = 5V. And
Resistor 302 and n-channel MOS transistor 303
Is transmitted to the gate electrode of the p-channel MOS transistor 301.

The operation of the above configuration will be described.

FIG. 4A shows an operation waveform of a main part in the circuit shown in FIG. 3, and FIG.
5 shows operation waveforms when the one-shot pulse generation circuit 33 and the forced pull-up circuit 30 are not provided.

When the one-shot pulse generation circuit 33 and the forced pull-up circuit 30 are not provided in FIG. 3, the logic of the input node IN transitions from low level to high level as shown in FIG. The fall of the waveform at the output node OUT is delayed as compared with the rise.

Therefore, in the circuit configuration shown in FIG. 3, the one-shot pulse generation circuit 33 and the forced pull-up circuit 3
By providing 0, as shown in FIG. 4A, the rising speed of the output node OUT is increased. That is, when the logic of the input node IN transitions from the high level to the low level, the one-shot pulse generation circuit 33
Generates a one-shot pulse signal, and during a period in which the one-shot pulse signal is at a high level, the n-channel MOS transistor 303 is turned on, whereby the p-channel MOS transistor 301 is turned on. Node Q, which is a signal path, is forcibly pulled up. This forced pull-up period is equal to the high-level period of the node Q, that is, the high-level period of the one-shot pulse signal. The forced pull-up of node Q2 supports the pull-up of p-channel MOS transistor 34 based on the output signal.

As described above, since the p-channel MOS transistor 301 is turned on and the node Q is forcibly pulled up, the fall characteristic of the output node OUT is improved. Is faster.

According to the above example, the following operation and effect can be obtained.

(1) Since the one-shot pulse signal synchronized with the edge at the time of transition of the input signal is applied, the forced pull-up circuit 10 for forcibly pulling up the signal path on the positive high potential side is provided. When the input node IN transitions from the low level to the high level, the signal transmission node on the positive high potential side is forcibly pulled up, and the output logic at the time of transition of the input signal is rapidly inverted by this forced pull-up. Thus, the rising characteristics of the output waveform are improved, and the level conversion is speeded up.

(2) When the n-channel MOS transistor 303 is turned on by the output signal of the one-shot pulse generating circuit 33, a through current flows through the resistor 302. Since the high-potential-side power supply VCH is lowered by this through current, a substantial potential difference for level conversion is reduced, and as a result, the circuit operation can be speeded up and stabilized.

(3) The through current flowing through the forced pull-up circuit can be controlled by the one-shot pulse width and the resistance value of the resistor 302, and should be kept lower than the through current at the next stage gate of the conventional level conversion circuit. Therefore, the current consumption of the entire circuit can be reduced.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, FIGS. 1 and 3 show a configuration for converting a positive voltage level. However, as a level conversion circuit applied to a semiconductor integrated circuit, a level from a negative low potential to a negative high potential is applied. In some cases, a signal is propagated.

FIGS. 5 and 7 show a level conversion circuit for converting a negative voltage level.

The level conversion circuit shown in FIG. 5 will be described.

An inverter 51 for inverting a signal input through input node IN is provided.
An inverter 52 for inverting one output logic is provided. The inverters 51 and 52 are supplied with a low-potential-side power supply Vss for operation.

A p-channel MOS transistor 54 and an n-channel MOS transistor 55 are connected in series, and a p-channel MOS transistor 56 and an n-channel MOS transistor 57 are connected in series. A series connection node (indicated by P) of the p-channel MOS transistor 54 and the n-channel MOS transistor 55 is coupled to the gate electrode of the n-channel MOS transistor 57,
A series connection node of transistor 56 and n-channel MOS transistor 57 is coupled to the gate electrode of n-channel MOS transistor 55. The source electrodes of the p-channel MOS transistors 54 and 56 are connected to a high-potential-side power supply VCC. The source electrodes of the n-channel MOS transistors 55 and 57 are connected to the negative high potential power supply VSX. Here, the negative high-potential-side power supply VSX has a lower level than the negative low-potential-side power supply VSS.

The p-channel type MOS transistor 5
An output signal of the level conversion circuit is obtained from a series connection node of the MOS transistor 6 and the n-channel MOS transistor 57.

Further, a one-shot pulse generating circuit 53 for generating a one-shot pulse signal based on the output signal of the inverter 51 is provided. The one-shot pulse generating circuit 53 is not particularly limited, but includes an inverter 531 and a NAND gate 532 coupled to each other. An input terminal of the inverter 531 and one input terminal of the NAND gate 532 are coupled to an output terminal of the inverter 51. When the output logic of the inverter 51 transitions from the high level to the low level, a one-shot pulse signal having a pulse width determined by the signal delay in the inverter 531 is output to the output node A of the one-shot pulse generation circuit 13. Is done.

A forced pull-down circuit 50 for forcibly pulling down the output node OUT of the level conversion circuit based on the one-shot pulse signal generated by the one-shot pulse generation circuit 53 is provided. The forced pull-down circuit 50 includes, but is not limited to, an n-channel MOS transistor 501, a resistor 502, and a p-channel MOS transistor 503. The resistor 502 is an example of a resistor in the present invention, and is not particularly limited, and is formed of polysilicon. The source electrode of the n-channel MOS transistor 501 and one terminal of the resistor 502 are coupled to the negative high potential power supply VSX. Then, the potential of the series connection node of the resistor 502 and the p-channel type MOS transistor 503 becomes the p-channel type MOS transistor 501.
To the gate electrode.

Here, the driving force of the n-channel MOS transistor 57 is set to “βn1” and the p-channel MOS transistor 57 is driven.
Assuming that the driving force of the S transistor 501 is “βn2”,

[0057]

## EQU3 ## The constants of the n-channel MOS transistors 57 and 501 are set so that the relationship of βn1 << βn2 holds.

The operation of the above configuration will be described.

FIG. 6A shows an operation waveform of a main part in the circuit shown in FIG. 5, and FIG.
5 shows operation waveforms when the one-shot pulse generation circuit 53 and the forced pull-down circuit 50 are not provided.

When the one-shot pulse generating circuit 53 and the forced pull-down circuit 50 are not provided in FIG. 5, the logic of the input node IN is changed from low level to high level as shown in FIG. In this case, the falling of the waveform of the output node OUT is delayed as compared with the rising. This is because the driving capability of the n-channel MOS transistor 57 is set smaller than that of the p-channel MOS transistor 57.

Therefore, in the circuit configuration shown in FIG. 5, one-shot pulse generation circuit 53 and forced pull-up circuit 5
By providing 0, as shown in FIG. 6A, the fall of the output node OUT is speeded up. That is, when the logic of the input node IN transitions from the low level to the high level, the one-shot pulse generation circuit 53
Generates a one-shot pulse signal. While this one-shot pulse signal is at a low level, p
The channel type MOS transistor 503 is turned on, whereby the n-channel type MOS transistor 501 is turned on.
Is turned on. As a result, the signal path on the negative high potential side is forcibly pulled down. This forced pull-down period is equal to the low-level period of the node A, that is, the low-level period of the one-shot pulse signal.

As described above, the n-channel MOS transistor 501 is turned on, whereby the output node OU
By forcibly pulling down T, the fall characteristic of the output node OUT is improved, and the fall is accelerated.

According to the above-described example, the following effects can be obtained.

(1) By applying a pulse signal synchronized with the edge at the time of transition of the input signal, a forced pull-down circuit 50 for forcibly pulling down the signal path on the negative high potential side is provided. When the signal transitions from high level to low level, the signal transmission node on the negative high potential side is forcibly pulled down, and the output logic at the time of transition of the input signal is rapidly inverted by this forced pull down, so that the output waveform falls. Characteristics are improved,
Level conversion is speeded up.

(2) When the p-channel MOS transistor 503 is turned on by the output signal of the one-shot pulse generation circuit 53, a through current flows through the resistor 502. This through current reduces the substantial potential difference for level conversion, and as a result, the circuit operation can be speeded up and stabilized.

(3) The through current can be controlled by the one-shot pulse width and the resistance value of the resistor 502, and can be suppressed lower than the through current at the next stage gate of the conventional level conversion circuit. Therefore, it is possible to reduce current consumption in the entire circuit.

Next, the level conversion circuit shown in FIG. 7 will be described.

An inverter 71 for inverting a signal input through input node IN is provided.
A p-channel MOS transistor 72 for transmitting one output logic to the subsequent circuit is provided. The inverter 71 is supplied with a high-potential-side power supply VCC for operation. The low potential side is set to the ground level VSS. The ground level VSS is also supplied to the gate electrode of the p-channel MOS transistor 72.

An inverter is formed by connecting a p-channel MOS transistor 75 and an n-channel MOS transistor 76 in series. p-channel type M
The source electrode of the OS transistor 75 is a high potential side power supply VC.
C, and is connected to an n-channel MOS transistor 76
Are coupled to the negative high potential side power supply VSX.
A series connection node of the p-channel MOS transistor 75 and the n-channel MOS transistor 76 is an output node of the level conversion circuit. p-channel type MOS transistor 75 and n-channel type M
The gate electrode of the OS transistor 76 is a node Q,
An input signal is transmitted to the node Q via the p-channel MOS transistor 72. Further, the node Q has an n-channel MOS for pull-down.
A transistor 74 is provided. This n-channel type M
The source electrode of the OS transistor 74 is coupled to the negative high potential side power supply VSX, and the gate electrode is connected to the output node OU.
The T signal is fed back.

Further, a one-shot pulse generation circuit 73 for generating a one-shot pulse signal based on the signal logic of input node IN is provided. The one-shot pulse generation circuit 73 is not particularly limited, but includes an inverter 731 and a NAND gate 732 coupled to each other. Input terminal of inverter 731 and NAND gate 73
One of the two input terminals is coupled to the input terminal of the inverter 31. When the signal logic of input node IN transitions from low level to high level, a one-shot pulse signal having a pulse width determined by the signal delay in inverter 731 is output to output node A of one-shot pulse generation circuit 73. Is done.

A forced pull-down circuit 70 for forcibly pulling down the node Q of the level conversion circuit based on the one-shot pulse signal generated by the one-shot pulse generation circuit 73 is provided. The forced pull-down circuit 70 is not particularly limited, but may be an n-channel type MO.
An S transistor 701, a resistor 702, and an n-channel MOS transistor 703 are combined. Resistance 7
02 is an example of the resistance means in the present invention, and is not particularly limited, but is formed of polysilicon. The source electrode of the n-channel MOS transistor 701 and one terminal of the resistor 702 are coupled to the negative high potential power supply VSX. Then, the resistor 702 and the p-channel type M
The potential of the node connected in series with the OS transistor 703 is
The signal is transmitted to the gate electrode of the n-channel MOS transistor 701.

The operation of the above configuration will be described.

FIG. 8A shows an operation waveform of a main part in the circuit shown in FIG. 7, and FIG.
5 shows operation waveforms when the one-shot pulse generation circuit 73 and the forced pull-down circuit 70 are not provided.

If the one-shot pulse generation circuit 73 and the forced pull-down circuit 70 are not provided in FIG. 7, the logic of the input node IN transitions from the low level to the high level as shown in FIG. In this case, the rising of the waveform of the output node OUT is delayed as compared with the falling.

Therefore, in the circuit configuration shown in FIG. 7, one-shot pulse generation circuit 73 and forced pull-down circuit
By providing 0, as shown in FIG. 8A, the rising speed of the output node OUT is increased. That is, when the logic of the input node IN transitions from the low level to the high level, the one-shot pulse generation circuit 73
Generates a one-shot pulse signal, and while the one-shot pulse signal is at a low level, the p-channel MOS transistor 703 is turned on, thereby turning on the n-channel MOS transistor 701. Thereby, the node Q is forcibly pulled down. This forced pull-down period is equal to the low-level period of the node A, that is, the low-level period of the one-shot pulse signal.

The n-channel MOS transistor 7
01 is turned on, thereby forcibly pulling down the node Q, so that the rising characteristics of the output node OUT are improved and the rising is quickened.

According to the above example, the following operation and effect can be obtained.

(1) Since a pulse signal synchronized with the edge at the time of transition of the input signal is applied, a forced pull-up circuit 70 for forcibly pulling up the signal transmission node on the positive high potential side is provided. When the input node IN transitions from the low level to the high level, the signal path on the negative high potential side is forcibly pulled down, and the output logic at the time of transition of the input signal is rapidly inverted by this forced pull down, so that the output waveform The rise characteristics have been improved,
Level conversion is speeded up.

(2) When the p-channel MOS transistor 703 is turned on by the output signal of the one-shot pulse generation circuit 73, a through current flows through the resistor 702. This through current reduces the substantial potential difference for level conversion, and as a result, the circuit operation can be speeded up and stabilized.

(3) The through current can be controlled by the one-shot pulse width and the resistance value of the resistor 702, and can be suppressed lower than the through current at the next stage gate of the conventional level conversion circuit. Therefore, it is possible to reduce current consumption in the entire circuit.

FIGS. 9 and 10 show another example of the configuration of the forced pull-up circuits 10 and 30. FIG.

For example, the resistance means in the forced pull-up circuit can be formed by a MOS transistor as shown in FIG. In FIG. 9, a p-channel MOS transistor (PMOS) 91 is applied instead of the resistor. The gate electrode of this MOS transistor is set to the ground level. In FIG. 10, a depletion-type p-channel MOS is used as the resistance means.
A transistor (PMOS) 101 is applied. The gate electrode is coupled to the high potential side power supply together with the source electrode. The gate-source voltage of the p-channel MOS transistor 91 is large, but in the case of the depletion type, the gate-source voltage Vgs = 0, and the dependency of the resistance value on the high-potential-side voltage is small. That is, the resistance value is stable.

FIGS. 11 and 12 show another example of the structure of the forced pull-down circuits 50 and 70. FIG.

In FIG. 11, an n-channel MOS transistor (NMOS) 111 is applied as the resistance means. The gate electrode is set to the high potential side power supply level. In FIG. 12, a depletion type n-channel MOS transistor (NMOS) 1 is used in place of the resistor.
21 are applied. The gate electrode is coupled to the negative high potential power supply along with the source electrode. As in the case of FIG. 10, in the case of the depletion type, the gate-source voltage Vgs = 0, and there is an advantage that the dependency of the resistance value on the high-potential-side voltage is small.

FIG. 13 shows a one-shot pulse generation circuit 1
Another configuration example of 3, 33, 53, 73 is shown.

The one-shot pulse generating circuit shown in FIG. 13 includes clocked inverters 133 and 132, a two-input AND gate 134, and an inverter 131. Clocked inverter 132 and inverter 1
31 is coupled in a loop and functions as a latch circuit for latching an input signal. The input node IN is transmitted to one input terminal of the AND gate 134, and is input to the AND gate 134 via the clocked inverter 133.
Is transmitted to the other terminal. Clocked inverter 13
2 and 133 are clock signals CK and CKB of complementary levels.
Are operated complementarily.

FIG. 14 shows the operation timing of the circuit shown in FIG.

As shown in FIG. 14, the pulse width of the one-shot pulse signal at node A is determined by the pulse widths of complementary-level clock signals CK and CKB.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is the field of application as the background has been described. However, the present invention is not limited to this, and various types of semiconductor integrated circuits can be used. It can be widely applied to circuits.

The present invention can be applied on condition that at least DC level conversion is performed.

[0091]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the level conversion circuit that propagates a signal from the positive low potential side to the positive high potential side, the signal on the positive high potential side is generated based on the one-shot pulse signal generated by the one-shot pulse generation circuit. The transmission node is forcibly pulled up, and the output logic at the time of transition of the input signal is inverted at high speed by this forcible pull-up, so that the speedup of the level conversion and the reduction of the current consumption are achieved.

In the level conversion circuit for transmitting a signal from the negative low potential side to the negative high potential side, a forced pull-down circuit for forcibly pulling down a signal transmission node on the negative high potential side is provided. Since the signal transmission node on the negative high potential side is forcibly pulled down based on the one-shot pulse signal, the output logic at the time of transition of the input signal is rapidly inverted by this forcible pull down,
Thereby, high-speed level conversion and low current consumption are achieved.

[0094] By configuring a semiconductor integrated circuit including such a level conversion circuit, the time required for exchanging signals between internal circuits can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration example of a level conversion circuit according to the present invention.

FIG. 2 is an operation timing chart of the level conversion circuit shown in FIG. 1 and a circuit to be compared with the level conversion circuit.

FIG. 3 is a circuit diagram illustrating another configuration example of the level conversion circuit according to the present invention;

4 is an operation timing chart of the level conversion circuit shown in FIG. 3 and a circuit to be compared with the level conversion circuit.

FIG. 5 is a circuit diagram of another configuration example of the level conversion circuit according to the present invention.

6 is an operation timing chart of the level conversion circuit shown in FIG. 5 and a circuit to be compared with the level conversion circuit.

FIG. 7 is a circuit diagram of another configuration example of the level conversion circuit according to the present invention.

8 is an operation timing chart of the level conversion circuit shown in FIG. 7 and a circuit to be compared with the level conversion circuit.

FIG. 9 is a circuit diagram of another configuration example of a forced pull-up circuit included in the level conversion circuit.

FIG. 10 is a circuit diagram of another configuration example of a forced pull-up circuit included in the level conversion circuit.

FIG. 11 is a circuit diagram of another configuration example of a forced pull-up circuit included in the level conversion circuit.

FIG. 12 is a circuit diagram illustrating another configuration example of a forced pull-down circuit included in the level conversion circuit.

FIG. 13 is a circuit diagram showing another example of the configuration of the one-shot pulse generation circuit included in the level conversion circuit.

14 is an operation timing chart of the one-shot pulse generation circuit shown in FIG.

FIG. 15 is a block diagram illustrating a configuration example of a semiconductor integrated circuit including the level conversion circuit.

[Explanation of symbols]

10, 30 forced pull-up circuit 13, 33, 53, 73 one-shot pulse generation circuit 50, 70 forced pull-down circuit 154, 155 level conversion circuit 101, 301, 503, 703 p-channel type MO
S transistor 102, 302, 502 Resistance 103, 303, 501, 701 n-channel type MO
S transistor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirozo Kawai 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term (reference) 5F038 AR30 CD02 CD03 in Hitachi Super LSI Systems, Ltd. DF01 DF04 DF05 DF08 DF14 EZ20 5J056 AA32 BB02 BB17 BB19 CC00 CC15 CC21 DD13 DD28 DD29 EE11 FF08 GG06 HH01 HH02

Claims (7)

[Claims] 1. A level conversion circuit for transmitting a signal from a positive low potential side to a positive high potential side, comprising: a one-shot pulse generation circuit for generating a one-shot pulse signal synchronized with an edge when an input signal transitions; A forced pull-up circuit for forcibly pulling up a signal path on the positive high potential side by applying a pulse signal generated by the one-shot pulse generation circuit. circuit. 2. The operation of the forced pull-up circuit is controlled by a resistance means coupled to a positive high-potential-side power supply and a one-shot pulse output from the one-shot pulse generation circuit connected in series to the resistance means. 2. The first transistor according to claim 1, further comprising: a first transistor to be supplied; and a second transistor for supplying a positive high potential to the signal path based on a potential of a series connection node of the resistor and the first transistor. Level conversion circuit. 3. The level conversion circuit according to claim 2, wherein said resistance means comprises a p-channel transistor. 4. A level conversion circuit for transmitting a signal from a negative low potential side to a negative high potential side, comprising: a one-shot pulse generation circuit for generating a one-shot pulse signal synchronized with an edge at the time of transition of an input signal; A forced pull-down circuit for forcibly pulling down a signal path on the negative high potential side by applying a pulse signal generated by the one-shot pulse generation circuit. 5. The operation of the forced pull-up circuit is controlled by a one-shot pulse output from the one-shot pulse generation circuit, the resistor being coupled to a negative high-potential-side power supply, and connected in series with the resistance. 4. The third transistor according to claim 3, further comprising: a third transistor to be supplied; and a fourth transistor for supplying a negative high potential to the signal path based on a potential of the series connection node of the resistor and the third transistor. Level conversion circuit. 6. The level conversion circuit according to claim 5, wherein said resistance means comprises an n-channel transistor. 7. A semiconductor integrated circuit formed on one semiconductor substrate including the level conversion circuit according to claim 1.