JP2000261674A - Image expansion device - Google Patents

Abstract

(57) Abstract: Provided is an image decompression device that outputs a black and white bit pattern as output data at a high speed based on image information specified by a run length. SOLUTION: Run length holding means for holding a plurality of digits of run length, and accumulatively adding one digit after another from a first digit to a subsequent digit of the plurality of digits of run length, and outputting an addition result for each digit And a change point bit indicating a change point position of the output data based on the addition result, the number of which is equal to the number of run-length digits. An image decompression device comprising: a change point information generation unit that outputs a change point bit; and a bit output generation unit that generates and outputs a black and white bit pattern based on the change point bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decompression device for generating a black and white bit pattern from compressed image data.

An image has a large data size compared to a text, so that a large-capacity memory is required to process the image, and a long processing time is required. It has a feature that it is much easier to understand as compared with the case where it is explained, and with the development of image input technology such as a scanner, an explanation using an image has been frequently used.

In business, an image displayed in black and white is generally used in many cases. Therefore, an image decompression device for processing an image displayed in black and white at high speed is required.

[0004]

2. Description of the Related Art As a method of outputting an image from image data, image data is expressed as a sequence of run lengths (referred to as "continuous length of white or black bits"). "Black" is set to "1", the initial value is white and the run length is "1", "2", "3", "4", "5",
If "6", ... is input, "1" is decoded, then "0" is decoded, then "2" is decoded, then "1", "1", then "3".
Is generally used to decode the run length one digit at a time, such as '0', '0', '0', and output a black and white bit string.

[0005]

However, an image in which black and white changes rapidly, that is, "1",
When run lengths having a small value such as “1”, “1”, “1”,... Continue, the number of run lengths increases, so that there is a problem in that processing takes a long time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image decompression device that outputs a black and white bit pattern from image data at high speed even for an image having a sharp change in black and white.

[0007]

According to the present invention, when an image is generated by using run length as an input as shown in FIG. Focusing on the fact that individual points at which black continuity changes to black or white can be detected numerically, the numerical values are converted into positions as shown in process 2, and the obtained individual positions are shown in process 3. In summary, information indicating a changing position having a certain number of bits can be obtained, and as shown in processing 4, the exclusive OR of the preceding bit and the information is taken bit by bit from the front to the rear. Thus, black and white data having a fixed number of bits is output.

The image decompression device of the present invention will be described with reference to FIG.

According to the first aspect of the present invention, the image decompression device includes a run length holding unit for holding a plurality of digits of run length.
And 1 from the leading digit to the trailing digit of the multi-digit run length.
Adding means 3 for accumulating and adding a result for each digit and outputting a result for each digit; and generating a change point bit indicating a change point position of the output data on the basis of the addition result for the number of run length digits. A change point information generating means 4 for generating change point bits for one digit of output data from change point bits generated for several minutes, and a bit output generating means 5 for generating and outputting black and white data based on the change point bits. When a run length of a predetermined number of digits is read from the leading digit to the succeeding digit into the run length holding means, one digit of monochrome data is generated and output.

According to a second aspect of the present invention, in addition to the means described in the first aspect, the image decompression apparatus further comprises: an offset value holding means 1 for holding an offset value for designating a start position of the black and white data; Adding means 3 for outputting the carry generated in the process for each digit, and counting the number of additions until the digit at which the carry is generated is counted, and processing is performed up to the said digit. The change point information generation means 4 is instructed to generate a change point bit indicating that there is no point, the addition result of the digit where the carry has occurred is stored in the offset value holding means 1, and the unprocessed digit following the processed digit is stored. The run length is packed and stored from the beginning of the run length holding means 2, and the run length following the number of digits indicated by the number of additions is packed and stored in the run length holding means 2 so as to be continuous with the unprocessed run length. Image expansion A control means 6, it has to configured generates and outputs the white data of consecutive number of bits specified by the run-length from the position specified by the offset value.

According to a third aspect of the present invention, the image decompression device further includes a run length holding unit that holds a plurality of digits of a run length including a counter unit and a register unit, in addition to the units described in the first and second aspects. Means 2, accumulative addition means 3 for accumulating the multi-digit run-length register portion by one digit from the beginning to the rear and outputting the addition result for each digit, and the counter portion of the leading digit. If a valid value is set, a flag is set, and the change point information generation means 4 is instructed to generate a change point bit indicating that there is no change point for all digits of the run length. Is not set, a carry does not occur due to the addition of the offset value and the first digit of the run length, and when the flag is set, a change point bit indicating that there is no change point for the digit is set. Change generation Image decompression control means 6 for instructing the point information generation means 4 and resetting the flag so as to generate and output one digit of monochrome data with a small circuit amount regardless of the magnitude of the run length value. Be composed.

In the first aspect, the run length of N digits is stored in the run length holding means 2 first.

Next, the run length of N digits is read from the run length holding means 2 and the first digit run length is inputted to the change point information generating means 4.

The first digit run length and the second digit run length are input to the adding means 3 and the addition result is input to the change point information generating means 4.

The result of the addition and the run length of the third digit are input to the adding means 3, and the result of the addition is input to the change point information generating means 4.

Thus, the run length of the Nth digit is input to the adding means 3 and the addition is repeated until the addition result is input to the change point information generating means 4.

The change point information generating means 4 calculates the first digit run length, the addition result of the first digit run length and the second digit run length, and the addition result of the addition result and the third digit run length. Then, an N-digit change point bit is generated based on the N-digit data, a logical sum of the N-digit change point bit is generated for each bit, and is output as one change point bit.

The bit output generating means 5 outputs a value which is inverted from the preceding output at the position where the change point bit indicates a change, and outputs the same value as the preceding output at the position where there is no change.

Then, the run length of the next N digits is stored in the run length holding means 2 again, and the above processing is repeated. The same processing is repeated until all the run lengths have been processed.

In the present invention, first, the offset value is stored in the offset value holding means 1, and the run length of N digits is stored in the run length holding means 2.

Next, the offset value is read from the offset value holding means 1 and the N-digit run length is read from the run length holding means 2, and the offset value is input to the change point information generating means 4.

Further, the offset value and the first-digit run length are input to the adding means 3, and the addition result is input to the change point information generating means 4.

The result of the addition and the run length of the second digit are input to the adding means 3, and the result of the addition is input to the change point information generating means 4.

The result of the addition and the run length of the third digit are input to the adding means 3, and the result of the addition is input to the change point information generating means 4.

Thus, the run length of the Nth digit is input to the adding means 3 and the addition is repeated until the addition result is input to the change point information generating means 4.

During this time, the image decompression control means 6
Each time a run length is input by one digit, the number of times is counted, and when a carry is detected from the adding means 3, generation of a change point bit indicating that there is no change point in the digits after that digit is performed. For the previous digit, it instructs the change point information generating means 4 to generate a change point bit based on the addition result.

The change point information generating means 4 generates N digit change point bits based on the instruction of the image decompression control means 6,
A logical sum for each digit of the change point bits for the digit is generated and output as a change point bit.

The bit output generating means 5 outputs a value which is inverted from the preceding output at the position where the change point bit indicates a change, and outputs the same value as the preceding output at the position where there is no change.

The image decompression control means 6 stores the result of addition by the adding means 3 in which the carry has occurred in the offset value holding means 1 and the run length of the number of digits indicated by the count value in the run length holding means 2. Read the length, store it with the number of digits indicated by the count value at the beginning, store it, and repeat the above processing.
The same processing is repeated until all run lengths have been processed.

In claim 3, first, the offset value is stored in the offset value holding means 1, and the run length of N digits is stored in the run length holding means 2.

Next, it is determined whether a valid value is set in the first-digit run-length counter.

When a valid value is set, the offset value is read from the offset value holding means 1 and input to the change point information generating means 4. The image decompression control means 6 refers to the flag. When the flag is off, the change point bit based on the input value is sent to the change point information generating means 4, and when the flag is on, the change point bit indicating that there is no change point. It instructs to generate a change point bit indicating that there is no change point in a digit other than the digit concerned.

The change point information generating means 4 generates N digit change point bits based on the instruction of the image decompression control means 6,
A logical sum for each digit of the change point bits for the digit is generated and output as a change point bit.

The bit output generating means 5 outputs a value which is the inverse of the preceding output at the position where the change point bit indicates a change, and outputs the same value as the preceding output at the position where there is no change.

The image expansion control means 6 decrements the value of the first-digit run-length counter by one, sets a flag, and sets a valid value in the first-digit run-length counter. The above-described processing is repeated from the reference as to whether or not it is performed.

When it is detected that a valid value has not been set in the first digit run length counter section, the offset value is supplied from the offset value holding means 1 and the N digit run number is supplied from the run length holding means 2. The length is read, and the offset value is input to the change point information generating means 4.

The offset value and the first-digit run length are input to the adding means 3, and the addition result is input to the change point information generating means 4.

The result of the addition and the run length of the second digit are input to the adding means 3, and the result of the addition is input to the change point information generating means 4.

The result of the addition and the run length of the third digit are input to the adding means 3, and the result of the addition is input to the change point information generating means 4.

Thus, the run length of the Nth digit is input to the adding means 3 and the addition is repeated until the addition result is input to the change point information generating means 4.

During this time, the image decompression control means 6
Each time a run length is input by one digit, the number of times is counted, and when a carry is detected from the adding means 3, generation of a change point bit indicating that there is no change point in the digits after that digit is performed. For the previous digit, it instructs the change point information generating means 4 to generate a change point bit based on the addition result.

If no carry is detected,
Refer to the flag when adding the run length of the first digit,
If the flag is off, the change point information generation means 4 is instructed to generate a change point bit based on the input value, and if the flag is on, the change point bit indicating that there is no change point is generated, and the flag is turned off.

Further, each time the second and subsequent run lengths are added, it is determined whether or not a valid value is set in the counter unit, and it is detected that a valid value is set. In this case, it is instructed to generate a change point bit indicating that there is no change point in the digits after the digit.

The change point information generating means 4 generates N digit change point bits based on the instruction of the image decompression control means 6,
A logical sum for each digit of the change point bits for the digit is generated and output as a change point bit.

The bit output generating means 5 outputs a value which is inverted from the preceding output at the position where the change point bit indicates a change, and outputs the same value as the preceding output at the position where there is no change.

The image decompression control means 6 stores the result of the addition performed by the adding means 3 in the offset value holding means 1 and the run length holding means 2 stores the run number corresponding to the number of digits indicated by the count value. The length is read, stored by packing the number of digits indicated by the count value at the beginning, and the above processing is repeated. The same processing is repeated until all run lengths have been processed.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.

In this description, the offset value is 2 bits,
The run length is described as 4 bits.

The image decompression device is provided with an offset register (hereinafter abbreviated as “OFR”) 1 for holding an offset value.
0, each of which has a 2-bit counter section (hereinafter abbreviated as “C section”) and a 2-bit register section (hereinafter abbreviated as “R section”) and holds one digit of run length. Run-length register A (hereinafter abbreviated as “RLRA”)
2-1, B (hereinafter abbreviated as "RLRB") 2-2, C
(Hereinafter abbreviated as "RLRC") 2-3, D (hereinafter, referred to as "RLRC").
Abbreviated as “RLRD”. 2), an adder A (hereinafter abbreviated as “ADDA”) 3-1 that adds the OFR and the RLRA, and generates a carry signal CA and an addition result SUMA.
An adder B (hereinafter abbreviated as “ADDB”) 3-2 that adds UMA and RLRB to generate a carry signal CB and an addition result SUMB, adds SUMB and RLRC, and generates a carry signal CC Adder C that generates addition result SUMC
(Hereinafter abbreviated as "ADDC"). 3-3 is added to SUMC and RLRD, and carry signal CD and addition result SUM are added.
Adder D that generates D (hereinafter abbreviated as “ADDD”)
3-4 and the value indicated by the addition result (for example, “3”) as bit positions, bit 0 is “0”, bit 1 is “0”,
A plurality of decoders that convert bit 2 to “0” and bit 3 to “1” to indicate that bit position 3 is a conversion point, that is, a decoder A that receives SUMA as an input (hereinafter, “DECA”)
Abbreviated. ) 4-1 and decoder B having SUMB as input
(Hereinafter abbreviated as "DECB") 4-2 and a decoder C which receives SUMC as an input (hereinafter abbreviated as "DECC")
4-3 and a decoder D which receives SUMD as an input (hereinafter referred to as a decoder D).
Abbreviated as "DECD". 4) and a decoder Z indicating that the bit position is a conversion point using the offset value as an input.
(Hereinafter abbreviated as "DECZ") 4-0 and DECA4
-1 to DECZ 4-0 as inputs, and a logical sum circuit (hereinafter abbreviated as "OR") 4-5 for generating one-digit change point information, and a flip-flop (hereinafter, referred to as "OR") for holding the value of the preceding bit , "FF".) 5-5 and FF5-
An EORA 5-1 that outputs an exclusive OR of a value of 5 and a subsequent bit that is continuous; an EORB 5-2 that outputs an exclusive OR of the output of the EORA 5-1 and the subsequent bit;
E that outputs the exclusive OR of the output of 5-2 and the following bit
An ORC 5-3 and an EORD 5-4 for outputting an exclusive OR of an output of the EORC 5-3 and a succeeding bit, and generate one digit of succeeding monochrome data based on the preceding output monochrome data and change point information. Bit output generation circuits (hereinafter abbreviated as “EOR”) 5-0 and RLRA2-1 to RLRA2-1.
A counter (hereinafter abbreviated as “CNT”) 6-2 in which the C section holds the number of “00” in RLRD 2-4, and R
4 or more flags 6-1 indicating that the C portion of LRA2-1 is other than '00', and refer to C portion of RLRA2-1 and set 4 or more flags 6-1 if other than '00' Then, when it becomes '00', it is reset and C of RLRA2-1 is reset.
If the part is other than '00', count down the C part of RLRA2-1 until it becomes '00', and each time DEC
Control circuit 6 for outputting "0000" from A4-1 to DECD4-4, sequentially referring to the C section of RLRA2-1 to RLR2-4, and recording the number of "00" in CNT6-2.
6

Next, the flow of the image decompression process of the present invention will be described.
The offset value is “2” and the run length is “5”, “2”, “3”, “1”, “2”, “3”,
An example in which “1”, “2”, “3”, and “1” are successively described will be described.

In the following description, numerical values enclosed by “” are expressed in binary notation (from the rear to the front, 2 to the 0th power, 2 to the 1st power,...).
・ It is weighted. ), And the number in parentheses is a binary representation (2 from front to back).
, 2 to the first power, and so on. ).

First, the CNT 6-2 is initialized to 0 (ie, '00' is set), the flag 6-1 is initialized to 4 or more to 0 (ie, '0' is set), and the offset value 2 is set.
(That is, '10') is set to OFR1-0, and run length 5 (that is, '0101') is set to RLRA2-1, and
(Ie, '0010') to RLRB 2-2, 3 (ie, '0011') to RLRC 2-3, 1 (ie,
'0001') is set to RLRD2-4. [Refer to timing T1 in FIG. 7] (Step S00) Next, the control circuit 6-0 refers to the C section of the RLRA2-1, and since it is not 0, the process proceeds to Step S31. (Step S
01) Next, the control circuit 6-0 refers to the flag 6-1 for 4 or more,
The conversion result “0010” is converted from DECZ4-0 to DECA
"0000" is output from each of 4-1 to DECD 4-4 (see timing T3 in FIG. 7), and a change point bit DECO "0010" is output from OR 4-5. [FIG.
Then, the DECO “0010” is converted to EOR5 in the order of i0 being “0”, i1 being “0”, i2 being “1”, and i3 being “0”.
0, and the exclusive OR '0' of the initial value '0' held by the FF 5-5 and i0 is set as b0, and the exclusive OR '0' of b0 and i1 is set as b1. b
Assuming that the exclusive OR '1' of 1 and i2 is b2, b2 and i
The exclusive OR '1' of 3 is b3, that is, b0, b
It outputs black and white data OUT consisting of 4 bits of 1, b2 and b3. [See timing T5 in FIG. Further, the flag 6-1 is set to 4 or more, and the RLRA 2-1 is set.
Is set to 0 by decrementing the C part of b, ie, b3, ie, '1' is
And returns to step S01. (Step S31
-S35) Next, the control circuit 6-0 refers to the C section of the RLRA2-1, and since it is 0, the process proceeds to step S02. At this time CNT
6-2 is "00", 4 or more flag 6-1 is "1",
'10' for OFR1-0, '00' for RLRA2-1
01 ',' 0010 'for RLRB2-2, RLRC2
'0011' for -3, '000 for RLRD2-4
1 'is set. [Refer to timing T6 in FIG. 7] (Step S01) The control circuit 6-0 adds 1 to the CNT 6-2 to make 1
ADD FR1-0, RLRA2-1 to RLRD2-4
A3-1 to ADDD3-4, and since the carry signal CA was not output from ADDA3-1, step S3 is executed.
Go to 05. (Steps S02 to S04) The addition result '11' from ADDA3-1 is added to ADDB3-
2 outputs the addition result '01' (see timing T7 in FIG. 7), and the control circuit 6-0 outputs “0000” from the DECZ 4-0 because the flag 6-1 is “1” or more.
"0001" obtained by converting "11" from ECA4-1
Is output and the flag 6-1 is set to "0" for the flag 6-1 (step S05). Referring to the C section of the RLRB 2-2, since it is 0, 1 is added to the CNT 6-2, and the carry CB is shifted from the ADDB 3-2. Output (steps S05 to S08), DE
"0000" is output from CB4-2 to DECD4-4. [See timing T8 in FIG. 7] (Step S27)
-S28) Then, the change point bit DECO “000” is obtained from OR4-5.
1 is output (refer to the timing T9 in FIG. 7). Then, the DECO "0001" is set to EOR5 in the order of i0 being "0", i1 being "0", i2 being "0", and i3 being "1".
0 and the EORA 5-1 sets the exclusive OR '1' between '1' held by the FF 5-5 and i0 as b0 and b
Assuming that the exclusive OR “1” of 0 and i1 is b1, b1 and i
The exclusive OR '1' of two is b2, and the exclusive OR '0' of b2 and i3 is b3, ie, b0, b1, b
It outputs monochrome data OUT consisting of 4 bits of 2 and b3. [See timing T10 in FIG. ] (Step S
18 to S19) Then, the addition result '0 of the ADDB3-2 that caused the carry
1 ′ is set in OFR1-0, the number of digits specified by the CNT, that is, the two-digit run length is read, and RLRC2
-3 to '0011' to RLRA2-1, RLRD2
-4 is transferred to RLRB2-2 from -4, and RL
"0010" is set in RC2-3 and "0011" is set in RLRD2-4 (see timing T11 in FIG. 8). ], Four or more flags 6-1 and CNT6-2 are reset, and the process returns to step S01. (Steps S20 to S2
2) Next, the control circuit 6-0 refers to the C section of the RLRA2-1, and since the value is 0, the process proceeds to step S02. (Step S
01) The control circuit 6-0 adds 1 to the CNT 6-2 to obtain 1, and the control circuit 6-0
ADD FR1-0, RLRA2-1 to RLRD2-4
A3-1 to ADDD3-4 are input, and since the carry signal CA is output from ADDA3-1, the process proceeds to step S29. (Steps S02 to S04) Then, “0100” generated based on “01” held in OFR1-0 is converted from DECZ4-0 to DECA4-
1 to DECD4-4 output "0000".
[See timing T13 in FIG. 8] (Steps S29 to S29)
S30) Then, the change point bit DECO “010” is obtained from OR4-5.
[0100] [Refer to timing T14 in FIG. 8] Then, the DECO “0100” is set to EOR5 in the order of i0 being '0', i1 being '1', i2 being '0', and i3 being '0'.
0 and the EORA 5-1 sets the exclusive OR '0' of '0' and i0 held by FF5-5 as b0,
Assuming that the exclusive OR “1” of 0 and i1 is b1, b1 and i
The exclusive OR '1' of two is set to b2, and the exclusive OR '1' of b2 and i3 is set to b3, that is, b0, b1, b
It outputs monochrome data OUT consisting of 4 bits of 2 and b3. [See timing T15 in FIG. ] (Step S
18 to S19) Then, the addition result '0 of the ADDA 3-1 that caused the carry
0 'is set in OFR1-0, the number of digits specified by the CNT, that is, one digit of the run length is read, and RLRC2
-0001 from -2 to RLRA2-1, RLRD2
-3 to '0010' are replaced with RLRB2-2B, RC2-4
To “RLRA2-3” from RLRC
Set “0001” in 2-4 [timing T in FIG.
See FIG. ], 4 or more flags 6-1 and CNT 6-2
Is reset and the process returns to step S01. (Step S2
Next, the control circuit 6-0 refers to the C section of the RLRA2-1, and since the value is 0, the control circuit 6-0 proceeds to step S02. (Step S
01) The control circuit 6-0 adds 1 to the CNT 6-2 to obtain 1, and the control circuit 6-0
ADD FR1-0, RLRA2-1 to RLRD2-4
A3-1 to ADDD3-4, and since the carry signal CA is not output from ADDA3-1, step S05
Proceed to. (Steps S02 to S04) Since four or more flags 6-1 are off, “1000” generated based on “00” held in OFR1-0 is DECZ
4-0, and outputs “0100” based on the output “01” of the ADDA 3-1 from the DECA 4-1. (Step S05) Next, the control circuit 6-0 refers to the C section of the RLRB2-2 and, since it is 0, proceeds to the step S07. (Step S
06) The control circuit 6-0 adds 1 to the CNT 6-2 to obtain 2 and A
Since the carry signal CB is not output from DDB3-2,
Proceed to step S09. (Steps S07 to S08) “0001” based on the output “11” of the ADDB 3-2 is output from the DECB 4-2. (Step S09) Next, the control circuit 6-0 refers to the C section of the RLRC2-3, and since it is 0, proceeds to the step S02. (Step S
10) The control circuit 6-0 adds 1 to the CNT 6-2 to obtain 3, and A
Since the carry signal CC is not output from the DDC 3-3, the process proceeds to step S25. (Steps S11 to S12) Then, from DECC4-3 to DECD4-4, "00"
00 "(see timing T18 in FIG. 8).
(Steps S25 to S26) Then, the change point bit DECO “110” is obtained from OR4-5.
1 is output. (See timing T19 in FIG. 8) Then, the DECO "1101" is output as EOR5 in the order of i0 being "1", i1 being "1", i2 being "0", and i3 being "1".
0 and the EORA 5-1 sets the exclusive OR '0' of '1' and i0 held by FF5-5 as b0,
Assuming that the exclusive OR “1” of 0 and i1 is b1, b1 and i
The exclusive OR '1 of 2 is b2, and the exclusive OR' 0 'of b2 and i3 is b3, that is, b0, b1, b
It outputs monochrome data OUT consisting of 4 bits of 2 and b3. [See timing T20 in FIG. ] (Step S
18 to S19) Hereinafter, the same processing is repeated until the run length is exhausted, and the processing ends.

[0053]

As described above, according to the present invention, a black-and-white pattern having a fixed number of bits at a single digit can be formed at a high speed according to the present invention even when an image having a sharp change in black and white, that is, even when a small value of run length continues. Since the output can be performed, there is an industrial effect that the image processing time can be shortened.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an image decompression device of the present invention.

FIG. 3 is a configuration diagram of a bit output circuit of the present invention.

FIG. 4 is a flowchart (part 1) of the present invention.

FIG. 5 is a flowchart of the present invention (part 2).

FIG. 6 is a flowchart (part 3) of the present invention.

FIG. 7 is a view for explaining a change in data according to the present invention (part 1);

FIG. 8 is a view for explaining a change in data according to the present invention (part 2);

FIG. 9 is a diagram showing an outline of processing;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Offset value holding means 2 Run length holding means 3 Addition means 4 Change point information generating means 5 Bit output generating means 6 Image expansion control means 1-0 Offset register (abbreviated as "OFR") 2-1 Run length register 1 ( 2-2 Run-length register 2 (abbreviated as "RLRB") 2-3 Run-length register 1 (abbreviated as "RLRC") 2-3 Run-length register 2 (abbreviated as "RLRD") ) 3-1 Adder A (abbreviated as "ADDA") 3-2 Adder B (abbreviated as "ADDB") 3-3 Adder C (abbreviated as "ADDC") 3-4 Adder D (Abbreviated as "ADDD") 4-0 Decoder Z (abbreviated as "DECZ") 4-1 Decoder A (abbreviated as "DECA") 4-2 Decoder B (abbreviated as "DECB") 4- Decoder C (abbreviated as "DECC") 4-4 Decoder D (abbreviated as "DECD") 4-5 Logical OR circuit (abbreviated as "OR") 5-0 Bit output circuit (abbreviated as "EOR") 6-0 Control circuit 6-1 4 or more flag 6-2 Counter (abbreviated as "CNT")

Claims (3)

[Claims] 1. An image decompression device for outputting black and white data by inputting a run length indicating a continuous length of white or black bits, comprising: run length holding means for holding a plurality of digits of run length; Adding means for accumulating one digit at a time from the first digit to the succeeding digit of the run length of the digit and outputting a result for each digit; and a run length bit indicating a change point position of output data based on the addition result. Change point information generating means for generating change point bits for one digit of output data from change point bits generated for the number of digits of the run length, and generating black and white data based on the change point bits And a bit output generating means for performing output. 2. An offset value holding means for holding an offset value designating a start position of black and white data, an addition means for outputting a carry generated in the process of cumulative addition for each digit, and a digit at which a carry occurs. Count the number of additions to reach,
When the digit has been processed and the carry has occurred, the digit after the digit is instructed to generate a change point bit meaning that there is no change point, and the change point information generating means is instructed. The result of digit addition is stored in the offset value holding means,
The unprocessed run length following the processed digit is stored from the beginning of the run length holding means, and the run length following the number of digits indicated by the number of additions is set to be continuous with the unprocessed run length. 2. The image decompression device according to claim 1, further comprising: an image decompression control unit that stores the data in the holding unit. 3. A run length holding means for holding a plurality of digits of run length each comprising a counter portion and a register portion, and the register portion of the plurality of digits of run length is sequentially shifted by one digit from a leading digit to a succeeding digit. Addition means that accumulates every minute and outputs the result for each digit, and sets a flag if a valid value is set by referring to the counter at the first digit and changes for all digits of the run length. The change point information generation means is instructed to generate a change point bit indicating that there is no point, and a valid value is not set in the counter of the first digit, and the carry is added by adding the offset value and the first digit of the run length. If the flag is set, the image decompression control unit instructs the change point information generation unit to generate a change point bit indicating that there is no change point for the digit, and resets the flag. 3. The image decompression device according to claim 2, comprising: