JP2000138371A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device capable of electrically forming a quantum wire. A source region, a channel region,
An MIS semiconductor device including the drain region 102 and having the gate electrode 103 over the channel region 104 is manufactured. Providing a trench structure on both sides of the channel region 104,
Second gate electrodes 106a and 106b are formed. While a positive voltage is applied to the gate electrode 103, a predetermined negative voltage is applied to the second gate electrode 106. The inversion layer 110 generated by the voltage of the gate electrode 103 forms the second gate electrode 1
Depletion layer 1 formed by negative voltages of transistors 06a and 106b
It contracts due to the expansion of 08a and 108b, and the inversion layer becomes the quantum wire 107. Further, both the second gate electrodes 106a, 1
06b by the voltage difference applied to the quantum wire 107b.
Is controlled. Thereby, the channel region 104
A tunnel junction is formed inside the semiconductor device, and the semiconductor device can be controlled by a single electron.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a thin inversion layer in a channel region. In particular, the present invention relates to a semiconductor device in which a quantum wire or quantum dot structure is formed by a depletion layer to enable single-electron control. According to the present invention, for example, a transistor with extremely low power consumption can be provided. Also, the presence or absence of a single electron is logically determined to be 1,0.
And a single-electron memory.

[0002]

2. Description of the Related Art For example, in a MOS type field effect transistor, the electric conductivity at an interface between an insulating film and a semiconductor is changed by an electric field effect caused by a gate voltage, and a current (a majority carrier) flowing between a source region and a drain region. ) Is controlled. This is accompanied by a great deal of heat. In recent years, advances in semiconductor manufacturing technology have enabled the production of quantum dots or quantum wires that enable nanometer-scale, ie, quantum mechanical behavior of electrons.
For example, it is a single-electron transistor that controls one electron. FIG. 6 shows an equivalent circuit of a basic single-electron transistor using a conductor island (quantum dot), and FIGS. 8 and 9 show that using a quantum wire. Note that a single-electron transistor using a quantum wire uses a quantum dot generated in the quantum wire to conduct only a small number of electrons, and thus hardly generates heat. Therefore, it is expected as an electronic device which is extremely excellent in power saving.

As shown in FIG. 6, a single-electron transistor has two small tunnel junctions 10 and 20 and one small tunnel junction 1
It is composed of a conductive island 30 of 0 nm scale and a gate capacitor 40 for controlling the potential of the conductive island. The minute tunnel junction is a metal junction having a metal-insulator-metal structure schematically shown in FIG.
About 10 ^-15 F at 1K, 10 ^-18 F at room temperature
It is necessary that the amount be as small as F. The junction capacitance C is determined from the next electron tunneling condition.

[0004]

[Number 1] _{E F + K B T / 2} <E F -K B T / 2 + △ E, △ E = e 2 / 2C (1) Here, E _F is the Fermi energy -, K _B is Botsuruman constant 8. 62 × 10 ⁻⁵ (eV / K), T is absolute temperature, e
Is the elementary charge of 1.6 × 10 ⁻¹⁹ coulomb, C is the tunnel junction capacity, and T is the absolute temperature. Rewriting equation (1),

[0005]

[Number 2] _{K B T <△ E = e} 2 / 2C (2) , and the From this junction capacitance C necessary for single-electron transistor operates at an absolute temperature T is determined.

[0006] In a single-electron transistor, only one to a few electrons are conducted due to a phenomenon called Coulomb blockage of a tunnel junction. As described above, when electrons pass through the tunnel junction, the tunnel junction involves a change in charging energy. In other words, electrons that cannot be given a change in charging energy cannot pass through. The phenomenon that the current hardly flows due to the charging effect is called Coulomb brocade or Coulomb blockage.

[0007] For simplicity, assume a single tunnel junction as shown in FIG. Consider a case in which an electric charge q exists in the tunnel junction in advance, and a slight voltage is applied thereon, and, for example, one electron tunnels out of the electric charge q.
The charging energy before the tunnel is 1/2 C · q ² , and that after the tunnel is 1/2 C · (q−e) ² . Therefore, the charging energy change of the junction before and after the tunnel is ΔE
= E (e / 2−q) / C, that is, ΔE = e (e / 2C
−V). At this time, (2) from the condition △ E> K _B T to Coulomb blockage of formula, e (e / 2C-V )> K
_BT .

When the temperature is sufficiently low, e (e / 2C
-V)> K _B T ≒ 0 becomes the voltage V applied to the tunnel junction is less than near e / 2C occur Coulomb blockage tunnel current does not flow, it is seen tunneling current when exceeding the vicinity of the voltage e / 2C flows Is shown. In such a tunnel junction having an extremely small junction capacitance, a Coulomb brocade phenomenon in which the current is intermittently occurs around the voltage e / 2C due to the charging effect. By utilizing this phenomenon, a single electron is controlled.

[0009] The number of minute tunnel junctions in a single-electron transistor is not one, but two or more. Its role is to link the quantum dots. In a single-electron transistor, a gate electrode is connected via a gate capacitor to control the potential of a quantum dot, and the change in the gate voltage controls the electron conduction of a source, a small tunnel junction, a quantum dot, a small tunnel junction, and a drain. in this case,
Coulomb block gates may or may not occur due to the small tunnel junction, thereby achieving single-electron control.

FIG. 8 shows a structure of a single-electron transistor using a silicon quantum wire, and FIG. 9 shows an equivalent circuit thereof. The operating principle is the same as that of the single electron transistor of FIG. In the case of manufacturing the silicon quantum wires 50, incorporation of impurities, narrowing of the width of the thin wires, fluctuation of the interface state, and the like are inevitably generated in the manufacturing process. 60, 70, 80, etc. are formed. Similarly, at this time, when a voltage is applied to the gate electrode, single electrons from the source impurity concentration layer connected to the source electrode sequentially move through the minute tunnel junction and the conductive island, and the drain connected to the drain electrode. Reaches the impurity layer. In this way, a single-electron transistor is realized even if a quantum wire is formed.

[0011]

However, in the single-electron transistor using the quantum wire described above, it is necessary to control the size and position and to produce a high-quality quantum dot in the quantum wire without processing damage. . For that purpose, the manufacturing technology of the angstrom order was required not only in the vertical direction but also in the horizontal direction, and the device was not always inexpensive. In addition, the tunnel junction and the conductor island are manifested by chance, and their positions and numbers are controlled and cannot be produced with good reproducibility. Therefore, a single-electron transistor cannot be reliably produced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In a device which enables single-electron control using a field-effect transistor, a voltage is applied to a side surface of a channel region to form an inversion layer. The purpose is to obtain a thinned inversion layer by electrically forming depletion layers on both sides. It is still another object of the present invention to provide a semiconductor device in which a single-electron transistor is surely developed by controlling the width and position of the thinned inversion layer by the magnitude of an applied voltage, thereby enabling single-electron control.

[0013]

To achieve this object, the present invention provides a source region, a channel region,
A field-effect semiconductor device having a drain region, wherein a voltage applied to a gate electrode controls an inversion layer generated in a channel region to control a current flowing between the drain region and the source region. A second gate electrode is provided on a side surface of the region in parallel with a direction in which electrons flow, and a predetermined voltage is applied to the second gate electrode to expand a depletion layer of the channel region, thereby reducing a width of the inversion layer. It is characterized by thinning.

According to another aspect of the present invention, the second gate electrode is formed in a trench formed in a depth direction from a surface, and in another aspect of the invention, the second gate electrode is exposed. Characterized in that it is formed on the side wall of the channel region formed. Further, another invention is characterized in that the gate electrode and the second gate electrode are formed via an insulating layer with respect to the channel region.
The position of forming the thinned inversion layer is controlled by the magnitude of the voltage applied to the gate. Another invention provides a single carrier transistor in which a fine tunnel junction is formed on the inversion layer by controlling the position of the thinned inversion layer by controlling the voltage applied to the second gate. It is characterized by obtaining.

[0015]

When a voltage is applied to the gate electrode, an inversion layer serving as a current path is formed in the channel region, and a current flows between the drain region and the source region. The second gate electrode is provided on the side surface of the inversion layer in parallel with the flow path of the inversion layer. Therefore, when a predetermined voltage is further applied to the second gate electrode in a state where the inversion layer is formed, the width of the inversion layer is reduced from the second gate electrode side into the channel by the electric field effect. A depletion layer is formed.
The size of the depletion layer can be controlled by the magnitude of the voltage applied to the second gate electrode. Therefore, it is possible to make the inversion layer into a fine line shape. The second gate electrode is desirably formed on both sides of the inversion layer, so that the depletion layer is extended on both sides of the inversion layer, and the inversion layer can be efficiently thinned.

The second gate electrode is perpendicular to the substrate, ie,
By forming the inversion layer in the trench formed in the depth direction, the inversion layer can be efficiently thinned. Further, even if the second gate electrode is formed on the exposed side surface of the channel region, the inversion layer can be similarly efficiently thinned.

Also, the gate electrode and the second gate electrode can be easily formed by using a so-called MIS type formed on an insulating film. Alternatively, a gate electrode may be formed by Schottky junction by depositing a metal on a semiconductor.

In these semiconductor devices, by controlling the voltage applied to the second gate electrode, the width or position or the width and position of the thinned inversion layer can be controlled. For example, if the channel region is p-type and the source and drain regions are n-type, the inversion layer is n-type and the carriers are electrons. In this element, by applying a positive potential to the gate electrode, a negative potential to the second gate electrode, a ground potential to the source region, and a positive potential to the drain region,
An inversion layer is formed on the surface of the channel region. Inversion layer is n
Since the type and the periphery are p-type, the depletion layer expands from both sides to the n-type inversion layer at the boundary parallel to the flow path of the inversion layer, and the inversion layer can be thinned.

A large number of quantum dots are distributed in a quantum wire, and when these quantum dots are combined with a tunnel junction, the semiconductor device becomes a single carrier transistor. That is, even after manufacturing, a single-carrier transistor can be easily formed by electrically controlling the position of the quantum wire.

In the present invention, quantum wires and quantum dots are not obtained by physical processing, but quantum wires and quantum dots are obtained by a depletion layer by an applied voltage. Therefore, the manufacturing becomes simpler and more reliable. They can be formed into Therefore, the semiconductor device can be controlled from a normal current to a single carrier by a voltage applied to the second gate electrode. Also, the manufacturing cost is reduced.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a top view illustrating the configuration of the present embodiment, and FIG. 2 is a cross-sectional view illustrating the internal configuration thereof. The cut surface is a straight line AA ′ in FIG. The semiconductor device of the present invention is a kind of MIS type transistor, and boron is 10%.
^A source region 101, a channel region 104, and a drain region 1 are formed on a p-type silicon substrate 100 containing ¹⁷ / cm ^3.
02, a gate oxide film 105a, which is an insulating film, is formed on the channel region 104, and a gate electrode 103 is formed thereon.

Source region 101, drain region 102
Is an n-type layer formed by, for example, arsenic ion implantation, and has an impurity concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁹ / c.
m is ^3. The channel region is a p-type layer equivalent to the silicon substrate 100, and has an impurity concentration of about 1 × 10 ¹⁶ / c
m is ^3. That is, it is an n-type MOS field effect transistor.

The gate oxide film 105a is obtained by heat treatment at about 1000 ° C. in an oxygen atmosphere, for example.
Its thickness is about 30 nm. Further, the gate electrode 103 formed thereon is, for example, polysilicon doped with phosphorus at a high concentration, and is obtained by CVD or the like.

In the semiconductor device of the present invention, a trench is formed on both sides of the channel region 104 in parallel (y direction) to the current path by using a lithography technique and an etching technique.
Similarly, a gate oxide film 105b is provided inside thereof, and second gate electrodes 106a and 106b are formed on the surface thereof. The gate oxide film 105b is formed in the same step as the gate oxide film 105a, and the second gate electrodes 106a and 106b are formed in the same step as the gate electrode 103.

Next, the operation of the semiconductor device having the above configuration will be described. Normally, the n-type MOS transistor changes the electric conductivity at the semiconductor interface (channel region 104) by the electric field effect of the gate electrode 103, and controls the current flowing through the source region 101 and the drain region 102.

Source region 101 and p-type silicon substrate 10
When 0 is a ground potential, the drain region 102 is a positive potential, and a positive voltage is applied to the gate electrode 103, an n-type inversion with a high electron concentration near the interface between the channel region 104 and the gate oxide film 105a by an electric field effect according to the voltage. Layer 110
Is formed. In this state, since the gate electrode 103 has a planar shape, the inversion layer 110 is also formed in a planar shape.

Next, when a negative voltage is applied to the second gate electrodes 106a and 106b present on both sides of the channel region 104, the holes in the p-type silicon substrate 100 become
06a and 106b are drawn toward the gate oxide film 105b. As a result, the depletion layers 108a and 108b are spread on both sides of the inversion layer 110 along the flow path. This depletion layer 1
08a and 108b are the same as those of the second gate electrode 106.
The larger the absolute value of the negative voltage applied to a and 106b, the larger the value. Thereby, as shown in FIG. 2, the inversion layer 107 thinned along the flow path can be obtained. The width of the thin line-shaped inversion layer 107 is equal to the width of the second gate electrode 106a.
The position can be controlled by the magnitude of the negative voltage applied to the second gate electrodes 106a, 106b,
06b can be changed by the ratio of the applied voltage to the magnitude of the applied voltage.

In the case of an n-type MOS, electrons are supplied to the source region 10
1 flows into the drain region 102 through the thin inversion layer 107. At this time, the length of the inversion layer 107 is the length of the channel region 104 formed by lithography. That is, the length (the y direction) of the inversion layer 107 is limited by the limit value of the lithography technique.

By controlling the width and position of the thin inversion layer 107 by voltage, a quantum thin line 107 having a width on the order of several tens of nm can be obtained. For example, the gate electrode 1
03 at 3V, and -3 at the second gate electrodes 106a and 106b.
When a voltage of V is applied, a quantum wire 107 having a width of about 20 nm is formed at the center of the channel region 104 in the direction (x direction) perpendicular to the current path. Also, both second gate electrodes 1
If the balance of the voltages applied to the 06a and 106b is controlled, the position of the quantum wire 107 in the x direction moves due to the difference between the voltages. That is, the width and the position of the quantum wire are controlled by the magnitude of the voltage and the difference therebetween.

As described in the conventional example, in the channel region 104, impurities are unavoidably mixed in the manufacturing process, fluctuations in the interface state, and the like, which inevitably occur. A plurality of tunnel junctions are formed. According to the semiconductor device of the present invention, the position of the quantum wire 107 can be accurately controlled by providing a difference between the voltages applied to the second gate electrodes 106a and 106b. Accordingly, the plurality of tunnel junctions can be arranged on the quantum wire 107. Quantum wire 10
When a plurality of tunnel junctions are arranged on the substrate 7 and quantum dots are formed between the plurality of tunnel junctions, a single-electron transistor is formed as described in the conventional example.

FIG. 3 shows the relationship between the gate voltage and the drain current when 3 V is applied to the gate electrode 103 and -3 V is applied to the second gate electrodes 106a and 106b. As the gate voltage increases, Coulomb oscillation in which electrons flow one by one is observed. That is, a single-electron transistor is formed. At this time, the source-drain voltage is about 1 mV. As described above, if the second gate electrodes are provided on both sides of the channel region of the MIS type semiconductor device, different negative voltages are applied between the electrodes, and the width and position of the formed quantum wires are easily controlled, A single-electron transistor for controlling electrons can be formed. Thus, even with standard microfabrication, a semiconductor device which can control single electrons at low cost and with high yield can be obtained.

(Second Embodiment) In the first embodiment, a trench is formed in a p-type silicon substrate, that is, a three-dimensional structure is constructed below, and an oxide film and a second gate electrode are formed therein. Thus, a semiconductor device in which quantum wires were electrically formed was obtained. In this embodiment, an equivalent MIS type semiconductor device is realized on a substrate. For that purpose, an SOI substrate was used. The SOI substrate is obtained by forming a thin silicon single crystal on an insulating substrate by an epitaxial technique or the like. In this embodiment, an SOI substrate in which a silicon substrate is thermally oxidized and a single crystal silicon film is further grown thereon is employed.

FIGS. 4 and 5 show a second embodiment of the present invention.
FIG. 4 is a top view illustrating the configuration of the present embodiment, and FIG. 5 is a cross-sectional view illustrating the internal structure. The cut surface is a straight line B in FIG.
B '. In the semiconductor device of this embodiment, a silicon support substrate 119 and a buried oxide film 11 formed thereon are formed.
8, a p-type silicon single crystal film 117 on which an n-type source region 101, an n-type drain region 102 and a channel region 104 are formed. Further, a gate oxide film 105a and a gate electrode 103 are sequentially formed on the p-type silicon single crystal film 117, and further on both sides thereof, as in the first embodiment, the gate oxide film 105a is formed.
b and the second gate electrodes 106a and 106b are formed. As described above, the semiconductor device of this embodiment has a structure in which the p-type silicon single crystal film 117 erected is sandwiched between the two second gate electrodes 106a and 106b. The same components as those in the first embodiment are denoted by the same reference numerals.

Next, the manufacturing method will be described. First, p
The SOI substrate on which the type silicon single crystal film is formed is patterned. After that, unnecessary portions are removed by dry etching to form a p-type silicon single crystal film 117 in which the source region 101, the channel region 104, and the drain region 102 are continuous. Thereafter, the source region 101 and the drain region 102 are masked, and high-temperature processing is performed, for example, to form gate oxide films 105a and 105b around the remaining p-type silicon single crystal film 117. next,
For example, polysilicon doped with a high concentration of phosphorus is formed therearound by an epitaxial technique, and the gate electrode 103 and the second gate electrodes 106a and 106b are formed. Finally, the masked source region 101 and drain region 102 are exposed, and ion implantation
Arsenic is doped to form an n ⁺ -type source region 101 and a drain region 102. Incidentally, the impurity concentration is equivalent to that of the first embodiment. In such a process, an MIS semiconductor device capable of single-electron control similar to that of the first embodiment is formed on the SOI substrate.

The operation is the same as that of the first embodiment. That is, when a voltage lower than that of the gate electrode 103, preferably a voltage lower than that of the substrate, that is, a negative voltage is applied to the second gate electrodes 106a and 106b formed on both sides of the channel region 104, the current flows in parallel from both sides. The depletion layers 108a and 108b are expanded, and the thin line-shaped inversion layer 107 is formed in the y-axis direction.

The second gate electrodes 106a, 106
If the balance of the voltage applied to b is controlled, the position of the quantum wire 107 is moved by the voltage difference as in the first embodiment. That is, the width and the position of the quantum wire are controlled by the magnitude of the voltage and the difference therebetween. Thus, the single-electron transistor is formed by coupling with the tunnel junction in the channel region 104. Therefore, SOI
A semiconductor device capable of single-electron control can be manufactured using a substrate.

(Modifications) Although the basic structure of the present invention has been described above, various other modifications are conceivable. For example, although the second gate electrodes 106a and 106b are formed on both sides of the channel region 104 in the first and second embodiments, only one side may be used as long as the applied voltage difference can be made sufficiently large. Also, the SOI structure used in the second embodiment may be made in various other ways. For example, by implanting oxygen ions deeply into a silicon substrate and subjecting the substrate to a heat treatment, SiO 2 is formed inside the substrate, and a SIMOX technique of making the surface a thin silicon single crystal, or a silicon single crystal is grown on a sapphire single crystal SOS (Silico
n On Sapphire technology, solid layer growth technology, bonding technology, or the like may be used. In the first and second embodiments, an n-type MOS transistor has been described as an example for convenience. However, a p-type MOS transistor having an opposite conductivity type or a complementary CMOS transistor may be used. Any type of semiconductor device can be used as long as the second gate electrode can be employed so that the n-type inversion layer or the p-type inversion layer formed in the channel region can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration top view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a configuration sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing Coulomb oscillation.

FIG. 4 is a configuration top view of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a configuration sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a single-electron transistor.

FIG. 7 is an explanatory view of a tunnel junction.

FIG. 8 is a top view of a configuration of a single-electron transistor using a quantum wire.

FIG. 9 is an equivalent circuit diagram of a single-electron transistor using a quantum wire.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 p-type silicon substrate 101 source region 102 drain region 103 gate electrode 104 channel region 105 a gate oxide film 105 b gate oxide film 106 second gate electrode 107 quantum fine wire, fine linear inversion layer 110 planar inversion layer 108 a, 108 b depletion layer 117 p-type silicon single crystal film 118 buried oxide film 119 silicon support substrate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 622 F term (Reference) 5F040 DA02 DC01 EA05 EB12 EC20 EE01 EE10 5F110 AA09 AA16 BB03 BB05 BB13 CC02 DD05 DD13 DD25 EE09 EE22 EE27 EE45 FF02 FF12 FF23 GG02 GG12 GG32 HJ01 HJ04 HJ13

Claims (6)

[Claims] 1. A semiconductor device having a source region, a channel region, and a drain region, comprising: controlling an inversion layer generated in a channel region by a voltage applied to a gate electrode;
In the field effect semiconductor device for controlling a current flowing between the drain region and the source region, a second gate electrode is provided on a side surface of the channel region in parallel to a direction in which electrons flow, and a predetermined voltage is applied to the second gate electrode. A width of the inversion layer is reduced by enlarging a depletion layer in the channel region. 2. The semiconductor device according to claim 1, wherein said second gate electrode is formed in a trench formed in a depth direction from a surface. 3. The semiconductor device according to claim 1, wherein said second gate electrode is formed on a side wall of said exposed channel region. 4. The method according to claim 1, wherein the gate electrode and the second gate electrode are
4. The channel region according to claim 1, wherein the channel region is formed via an insulating layer.
13. The semiconductor device according to item 9. 5. The method according to claim 1, wherein the formation position of the thinned inversion layer is controlled by the magnitude of the voltage applied to the second gate. Semiconductor device. 6. A single carrier transistor having a fine tunnel junction formed on the inversion layer by controlling the position of the thinned inversion layer by controlling the voltage applied to the second gate. 2. The method according to claim 1, wherein
The semiconductor device according to claim 1.