JP2000133739A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JP2000133739A JP2000133739A JP30274598A JP30274598A JP2000133739A JP 2000133739 A JP2000133739 A JP 2000133739A JP 30274598 A JP30274598 A JP 30274598A JP 30274598 A JP30274598 A JP 30274598A JP 2000133739 A JP2000133739 A JP 2000133739A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- external connection
- tin
- plating film
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 89
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 30
- 229910052737 gold Inorganic materials 0.000 claims abstract description 20
- 239000010931 gold Substances 0.000 claims abstract description 20
- 230000008018 melting Effects 0.000 claims abstract description 18
- 238000002844 melting Methods 0.000 claims abstract description 18
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims description 52
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 19
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 37
- 239000004065 semiconductor Substances 0.000 description 25
- 238000010438 heat treatment Methods 0.000 description 11
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 229910000990 Ni alloy Inorganic materials 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 5
- CLDVQCMGOSGNIW-UHFFFAOYSA-N nickel tin Chemical compound [Ni].[Sn] CLDVQCMGOSGNIW-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910001245 Sb alloy Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000002140 antimony alloy Substances 0.000 description 1
- GVFOJDIFWSDNOY-UHFFFAOYSA-N antimony tin Chemical compound [Sn].[Sb] GVFOJDIFWSDNOY-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- ACVYVLVWPXVTIT-UHFFFAOYSA-M phosphinate Chemical compound [O-][PH2]=O ACVYVLVWPXVTIT-UHFFFAOYSA-M 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＢＧＡ（ボールグリ
ッドアレイ）型の半導体パッケージ等の回路基板に関す
る。The present invention relates to a circuit board such as a BGA (ball grid array) type semiconductor package.
【０００２】[0002]
【従来の技術】図１はＢＧＡ型の半導体パッケージ１０
の概略的な断面図、図２はその部分拡大図である。１２
は半導体パッケージの本体となる多層回路基板で、所要
の配線パターンが多段に形成されている。１４は配線パ
ターンのパッド部（ランドを含む）に接合された外部接
続端子としてのはんだボール（錫−鉛合金）である。１
５は半導体チップ搭載部である。上記配線パターンの一
部が半導体チップ搭載部１５を囲む段差面１７上に露出
している。半導体チップ搭載部１５に半導体チップが搭
載され、半導体チップと上記段差面１７に露出している
配線パターンとの間でワイヤにより電気的接続がなされ
たうえで、半導体チップが樹脂封止あるいは金属製キャ
ップにより封止されて半導体装置に完成される。2. Description of the Related Art FIG. 1 shows a BGA type semiconductor package 10.
2 is a partially enlarged view of FIG. 12
Is a multilayer circuit board serving as a main body of a semiconductor package, in which required wiring patterns are formed in multiple stages. Reference numeral 14 denotes a solder ball (tin-lead alloy) as an external connection terminal joined to a pad portion (including a land) of the wiring pattern. 1
Reference numeral 5 denotes a semiconductor chip mounting portion. Part of the wiring pattern is exposed on the step surface 17 surrounding the semiconductor chip mounting portion 15. The semiconductor chip is mounted on the semiconductor chip mounting portion 15, and after the semiconductor chip and the wiring pattern exposed on the step surface 17 are electrically connected by wires, the semiconductor chip is sealed with resin or made of metal. The semiconductor device is completed by being sealed with a cap.
【０００３】図２の拡大図に示されるように、銅からな
る配線パターン１６のパッド部１６ａには、無電解ニッ
ケル皮膜１８が形成され、この無電解ニッケルめっき皮
膜１８上に無電解金めっき皮膜２０が形成され、この無
電解金めっき皮膜２０上にはんだボールが載置され、リ
フロー加熱されることによってはんだボールからなる外
部接続端子１４に形成される。２２は絶縁層、２４はソ
ルダーレジスト層である。As shown in an enlarged view of FIG. 2, an electroless nickel film 18 is formed on a pad portion 16a of a wiring pattern 16 made of copper, and an electroless gold plating film is formed on the electroless nickel plating film 18. A solder ball is placed on the electroless gold plating film 20 and is formed on the external connection terminal 14 made of the solder ball by reflow heating. 22, an insulating layer; and 24, a solder resist layer.
【０００４】[0004]
【発明が解決しようとする課題】上記無電解ニッケルめ
っきを施す場合、一般的に還元剤として次亜リン酸塩が
添加された無電解ニッケルめっき液が用いられる。その
ため無電解ニッケルめっき皮膜１８は、めっき皮膜中に
リンが含有されるめっき皮膜となる。前記のように、無
電解金めっき皮膜２０上にはんだボールを載置し、リフ
ロー加熱することによりはんだボールが接合され、外部
接続用端子１４に形成される。ところが、一般に無電解
ニッケルめっき皮膜１８を下地にはんだボールを接合す
ると、はんだボールの密着性がよくなく、いわゆるボー
ルシュア強度が低いという課題がある。When the above electroless nickel plating is performed, an electroless nickel plating solution to which hypophosphite is added as a reducing agent is generally used. Therefore, the electroless nickel plating film 18 becomes a plating film containing phosphorus in the plating film. As described above, the solder balls are mounted on the electroless gold plating film 20 and reflow-heated to join the solder balls to form the external connection terminals 14. However, in general, when solder balls are joined with the electroless nickel plating film 18 as a base, there is a problem that the adhesion of the solder balls is not good and so-called ball sure strength is low.
【０００５】そこで、本発明は上記課題を解決すべくな
されたものであり、その目的とするところは、外部接続
端子の接合強度に優れる回路基板を提供するにある。Accordingly, the present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a circuit board having excellent bonding strength of external connection terminals.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、本発明に係る回
路基板は、配線パターンのパッド部に無電解ニッケルめ
っき皮膜が形成され、該無電解ニッケルめっき皮膜上に
金めっき皮膜が形成された回路基板において、前記金め
っき皮膜上に、形成すべきはんだボール等の錫合金から
なる外部接続端子の融点よりも高い融点を有し、かつ該
外部接続端子よりも錫含有量の低い錫合金からなる、前
記外部接続端子接合用のはんだ層が形成されていること
を特徴としている。The present invention has the following arrangement to achieve the above object. That is, in the circuit board according to the present invention, the electroless nickel plating film is formed on the pad portion of the wiring pattern, and the gold plating film is formed on the electroless nickel plating film. A solder having a melting point higher than that of an external connection terminal made of a tin alloy such as a solder ball to be formed, and made of a tin alloy having a lower tin content than the external connection terminal; It is characterized in that a layer is formed.
【０００７】上記構成を採用することにより、外部接続
端子を接合する際、錫−ニッケル合金層が形成される割
合を減少させ、界面のリンの濃度がそれ程高くならず、
外部接続端子の接合強度を向上させうる。前記はんだ層
を介して前記外部接続端子を接合した回路基板としても
提供できる。前記外部接続端子をはんだボールとしたＢ
ＧＡ型の回路基板として提供できる。By adopting the above structure, when joining the external connection terminals, the rate of formation of the tin-nickel alloy layer is reduced, and the phosphorus concentration at the interface does not increase so much.
The bonding strength of the external connection terminal can be improved. It can also be provided as a circuit board in which the external connection terminals are joined via the solder layer. B where the external connection terminal is a solder ball
It can be provided as a GA type circuit board.
【０００８】[0008]
【発明の実施の形態】以下、本発明の好適な実施の形態
を添付図面に基づいて詳細に説明する。本実施の形態を
適用した回路基板の一例であるＢＧＡ型半導体パッケー
ジ１０はその基本構造において図１および図２に示すも
のと変わりはない。本実施の形態では、図３の拡大図に
示すように、はんだボール等の外部接続端子１４を接合
する下地金属の構造に従来のものと差がある。Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The BGA type semiconductor package 10, which is an example of a circuit board to which the present embodiment is applied, has the same basic structure as that shown in FIGS. In the present embodiment, as shown in the enlarged view of FIG. 3, there is a difference in the structure of the underlying metal joining the external connection terminals 14 such as solder balls from the conventional one.
【０００９】以下図３にしたがって説明する。図３にお
いて、図２と同様、２２は絶縁層、１６は配線パター
ン、２４はソルダーレジスト層である。ソルダーレジス
ト層２４は、パッド部１６ａを除く外層の配線パターン
１６を覆うように形成されている。パッド部１６ａに
は、従来と同様に、まず無電解ニッケルめっき皮膜１８
が形成され、この無電解ニッケルめっき皮膜１８の上に
無電解金めっき皮膜２０が形成されている。The operation will be described below with reference to FIG. In FIG. 3, as in FIG. 2, 22 is an insulating layer, 16 is a wiring pattern, and 24 is a solder resist layer. The solder resist layer 24 is formed so as to cover the wiring pattern 16 in the outer layer except for the pad portion 16a. First, the electroless nickel plating film 18 is formed on the pad portion 16a as in the prior art.
Is formed, and an electroless gold plating film 20 is formed on the electroless nickel plating film 18.
【００１０】本実施の形態で特徴的なのは、この無電解
金めっき皮膜２０を覆って、形成すべきはんだボール等
の錫合金からなる外部接続端子１４の融点よりも高い融
点を有し、かつ該外部接続端子１４よりも錫含有量の低
い錫合金からなる、外部接続端子接合用のはんだ層２６
を形成した点にある。The feature of the present embodiment is that it has a melting point higher than the melting point of the external connection terminal 14 made of a tin alloy such as a solder ball to cover the electroless gold plating film 20, and Solder layer 26 for joining external connection terminals, made of a tin alloy having a lower tin content than external connection terminals 14
It is in the point which formed.
【００１１】外部接続端子１４を形成するはんだ（錫合
金）として例えば共晶はんだ（６：４の錫−鉛合金）を
用いた場合、はんだ層２６には、例えば５：５錫−鉛合
金、あるいは３：７錫−鉛合金からなるはんだを用いる
ことができる。これらのはんだ層２６は共晶はんだから
なる外部接続端子１４よりも高融点で、かつ錫含有量が
低い。はんだ層２６としては錫−鉛合金の他に、錫−銀
合金等の錫合金、あるいは錫−アンチモン合金等の錫合
金を用いることもできる。When a solder (tin alloy) for forming the external connection terminals 14 is, for example, a eutectic solder (tin-lead alloy of 6: 4), the solder layer 26 is formed of, for example, a 5: 5 tin-lead alloy, Alternatively, a solder made of a 3: 7 tin-lead alloy can be used. These solder layers 26 have a higher melting point and a lower tin content than the external connection terminals 14 made of eutectic solder. As the solder layer 26, in addition to the tin-lead alloy, a tin alloy such as a tin-silver alloy, or a tin alloy such as a tin-antimony alloy can be used.
【００１２】はんだ層２６を形成するには、上記合金の
無電解めっきを施して形成してもよいが、より簡易に
は、上記合金の微細なボールを所要量混入させて、樹脂
バインダーでペースト状になしたはんだペーストを塗布
し、リフロー加熱してはんだ層２６を形成するようにし
てもよい。このリフロー加熱は後記する理由によりでき
るだけ短時間の加熱で行うようにするのが好ましい。In order to form the solder layer 26, the above alloy may be formed by electroless plating. However, more simply, a required amount of fine balls of the above alloy are mixed, and the solder paste is mixed with a resin binder. The solder paste formed into a shape may be applied, and the solder layer 26 may be formed by reflow heating. This reflow heating is preferably performed by heating as short as possible for the reason described below.
【００１３】上記のようにはんだ層２６を形成した基板
をＢＧＡ型半導体パッケージ１０として提供できる。あ
るいははんだ層２６を介してはんだボール等の外部接続
端子１４を接合したものでＢＧＡ型半導体パッケージ１
０として提供できる。表１はこのはんだボール（６：４
錫−鉛合金）を接合したＢＧＡ型半導体パッケージのボ
ールシェア強度試験のデータを示す。The substrate on which the solder layer 26 is formed as described above can be provided as the BGA type semiconductor package 10. Alternatively, the BGA type semiconductor package 1 is formed by bonding external connection terminals 14 such as solder balls via a solder layer 26.
0 can be provided. Table 1 shows this solder ball (6: 4
4 shows data of a ball shear strength test of a BGA type semiconductor package bonded with a tin-lead alloy).
【００１４】[0014]
【表１】 [Table 1]
【００１５】比較例１は、下地めっきが電解ニッケルめ
っき／電解金めっきであり、直接はんだボールを接合し
たもの。比較例２は、下地めっきが無電解ニッケルめっ
き／無電解金めっきであり、直接はんだボールを接合し
たもの。実施例１は、無電解ニッケルめっき／無電解金
めっきの下地上に５：５錫−鉛合金からなるはんだ層を
形成し、このはんだ層上にはんだボールを接合したも
の。実施例２は、無電解ニッケルめっき／無電解金めっ
きの下地上に３：７錫−鉛合金からなるはんだ層を形成
し、このはんだ層上にはんだボールを接合したものであ
る。また表１中、直後とは、はんだボールをリフロー加
熱して接合した直後のデータであり、３０分後とは、は
んだボールをリフロー加熱して接合した後、さらにリフ
ロー炉内に３０分（加熱条件下に）放置した後のデータ
を示す。In Comparative Example 1, the underlying plating was electrolytic nickel plating / electrolytic gold plating and solder balls were directly joined. In Comparative Example 2, the base plating was electroless nickel plating / electroless gold plating, and solder balls were directly joined. In the first embodiment, a solder layer made of a 5: 5 tin-lead alloy is formed on a lower surface of electroless nickel plating / electroless gold plating, and a solder ball is joined on this solder layer. In the second embodiment, a solder layer made of a 3: 7 tin-lead alloy is formed on the lower surface of electroless nickel plating / electroless gold plating, and a solder ball is joined on this solder layer. In Table 1, “immediately” means data immediately after the solder balls were reflow-heated and joined. “30 minutes later” means that the solder balls were reflow-heated and joined, and further placed in a reflow furnace for 30 minutes (heating The data after standing (under conditions) are shown.
【００１６】表１から明らかなように、下地めっき皮膜
が電解ニッケルめっき皮膜の上に電解金めっき皮膜を形
成した電解めっき皮膜である場合には、ボールシェア強
度が高い。しかるに、下地めっき皮膜が無電解ニッケル
めっき皮膜の上に無電解金めっき皮膜を形成した無電解
めっき皮膜である場合には、ボールシェア強度が低い。
リフロー加熱直後、およびさらに３０分間リフロー加熱
雰囲気中（リフロー加熱炉中）に放置した加速試験後の
いずれの場合もボールシェア強度が低いことがわかる。As is clear from Table 1, when the base plating film is an electrolytic plating film formed by forming an electrolytic gold plating film on an electrolytic nickel plating film, the ball shear strength is high. However, when the base plating film is an electroless plating film in which an electroless gold plating film is formed on an electroless nickel plating film, the ball shear strength is low.
It can be seen that the ball shear strength was low immediately after the reflow heating and after the accelerated test left for 30 minutes in the reflow heating atmosphere (in the reflow heating furnace).
【００１７】これに対して、無電解めっき皮膜上に５：
５の錫−鉛合金からなるはんだ層を形成した実施例１、
無電解めっき皮膜上に３：７の錫−鉛合金からなるはん
だ層を形成した実施例２のいずれの場合も、下地に電解
めっき皮膜を形成した比較例１よりは若干劣るが、無電
解めっき皮膜上に直接はんだボールを接合した比較例２
よりも格段に優れたボールシェア強度が得られている。On the other hand, 5:
Example 1 in which a tin-lead alloy solder layer of No. 5 was formed,
In any case of Example 2 in which a solder layer made of a 3: 7 tin-lead alloy was formed on the electroless plating film, electroless plating was slightly inferior to Comparative Example 1 in which an electroplating film was formed on the underlayer. Comparative Example 2 in which solder balls were directly bonded on the film
A much better ball shear strength is obtained.
【００１８】ボールシェア強度は特に最低強度が問題と
なる。すなわち、はんだボールの脱落が生じる可能性が
大きくなるからである。表１から明らかなように、比較
例２の場合は最低強度が極めて低い。これに対して実施
例１、２の場合、最低強度が比較例１に対しても遜色が
ないのである。The ball shear strength is particularly problematic in the minimum strength. That is, the possibility that the solder balls fall off increases. As is clear from Table 1, in the case of Comparative Example 2, the minimum strength is extremely low. On the other hand, in the case of Examples 1 and 2, the minimum strength is not inferior to Comparative Example 1.
【００１９】下地めっき皮膜上にはんだボールを接合す
ると、無電解（あるいは電解）金めっき皮膜ははんだ中
に拡散し、ニッケルとはんだボールとが接合する構造と
なる。この界面において、ニッケルの一部ははんだと錫
−ニッケル合金を形成する。下地が無電解ニッケルめっ
き被膜の場合には、ニッケルが錫と合金を形成するか
ら、この界面における無電解ニッケルめっき皮膜中のリ
ンの濃度が高くなる。この界面におけるリンがリッチな
構造になるとはんだとニッケルとの接合強度が低くなる
と考えられる。When a solder ball is joined to a base plating film, the electroless (or electrolytic) gold plating film diffuses into the solder, so that nickel and the solder ball are joined. At this interface, some of the nickel forms a tin-nickel alloy with the solder. When the base is an electroless nickel plating film, nickel forms an alloy with tin, so that the concentration of phosphorus in the electroless nickel plating film at this interface increases. It is considered that when the structure at the interface is rich in phosphorus, the bonding strength between the solder and nickel decreases.
【００２０】本実施の形態では、上記の界面に、形成す
べきはんだボール等の錫合金からなる外部接続端子１４
の融点よりも高い融点を有し、かつ該外部接続端子１４
よりも錫含有量の低い錫合金からなる、外部接続端子１
４接合用のはんだ層２１が形成される。外部接続端子と
なるはんだボールをリフロー加熱して接合する際、はん
だ層２６はこのはんだボールより融点が高いから、リフ
ロー加熱時の温度に対して、はんだボールよりも溶融が
遅いといえる。またはんだ層２６ははんだボールよりも
錫の含有量が低いからその下地の無電解ニッケルめっき
層１８との間での錫−ニッケル合金が形成される割合が
比較例２に対して低くなり、したがって、界面における
無電解ニッケルめっき皮膜１８中のリンの濃度がそれ程
高くならず、これによりボールシェア強度が高く維持さ
れると考えられる。In this embodiment, the external connection terminal 14 made of a tin alloy such as a solder ball to be formed is provided at the interface.
Having a melting point higher than the melting point of the external connection terminal 14.
External connection terminal 1 made of a tin alloy having a lower tin content than
Four solder layers 21 for bonding are formed. When a solder ball serving as an external connection terminal is joined by reflow heating, the melting point of the solder layer 26 is higher than that of the solder ball. Further, since the solder layer 26 has a lower tin content than the solder ball, the ratio of the formation of the tin-nickel alloy with the underlying electroless nickel plating layer 18 is lower than that of Comparative Example 2, and therefore, It is considered that the concentration of phosphorus in the electroless nickel plating film 18 at the interface does not increase so much, so that the ball shear strength is maintained high.
【００２１】はんだ層２６をはんだペーストをリフロー
加熱して形成する場合、錫含有量を少なくしたはんだを
用いるとはいえ、溶融時間が長いとそれだけ錫−ニッケ
ル合金を形成しやすくなるから、リフロー加熱時間はで
きるだけ短い方がよい。When the solder layer 26 is formed by reflow heating the solder paste, although a solder having a reduced tin content is used, a longer melting time facilitates the formation of a tin-nickel alloy. Time should be as short as possible.
【００２２】ＢＧＡ型半導体パッケージ１０は、ビルド
アップ構造のもの、プリプレグの接着層を介した積層構
造のものなど、その構造は特に限定されない。もちろん
フェースアップだけでなく、フェースダウンの構造のも
のにも適用できることはもちろんである。また本発明
は、半導体チップを搭載する半導体パッケージのみに適
用されるものではない。広く、無電解の下地めっき皮膜
上にはんだボールやはんだからなる外部接続端子を形成
した回路基板に適用できる。The structure of the BGA type semiconductor package 10 is not particularly limited, such as a build-up structure and a laminated structure with a prepreg adhesive layer interposed therebetween. Of course, the present invention can be applied not only to the face-up but also to the face-down structure. Further, the present invention is not applied only to a semiconductor package on which a semiconductor chip is mounted. The present invention can be widely applied to a circuit board in which external connection terminals made of solder balls or solder are formed on an electroless base plating film.
【００２３】例えば図４はプリント配線基板３０の例を
示す。単層あるいは多層の基板３２の表面配線パターン
３４のパッド部３４ａに半導体チップがフリップチップ
接続されるプリント配線基板に適用できる。すなわち、
パッド部３４ａに無電解ニッケルめっき皮膜（図示せ
ず）、次いで無電解金めっき皮膜（図示せず）を形成
し、この無電解金めっき皮膜上に、上記と同様に、形成
すべき予備はんだ（外部接続端子）の融点よりも高い融
点を有し、かつ該外部接続端子よりも錫含有量の低い錫
合金からなる、前記外部接続端子接合用のはんだ層（図
示せず）を形成し、このはんだ層上にはんだペーストを
塗布してリフロー加熱して予備はんだ（図示せず）を形
成するのである。半導体チップ側には上記予備はんだよ
りも融点の高いはんだによるはんだバンプが形成されて
おり、半導体チップは上記予備はんだを介してパッド部
３４ａ上に接合される。この場合も予備はんだと下地の
無電解ニッケルめっき皮膜との間、ひいては半導体チッ
プと予備はんだとの間の接合性は良好である。FIG. 4 shows an example of the printed wiring board 30. The present invention can be applied to a printed wiring board in which a semiconductor chip is flip-chip connected to a pad portion 34a of a surface wiring pattern 34 of a single-layer or multilayer substrate 32. That is,
An electroless nickel plating film (not shown) is formed on the pad portion 34a, and then an electroless gold plating film (not shown) is formed on the pad portion 34a. Forming a solder layer (not shown) for joining the external connection terminals, which has a melting point higher than the melting point of the external connection terminals and is made of a tin alloy having a lower tin content than the external connection terminals; A solder paste is applied on the solder layer and reflow-heated to form a preliminary solder (not shown). Solder bumps made of solder having a higher melting point than the preliminary solder are formed on the semiconductor chip side, and the semiconductor chip is joined to the pad portion 34a via the preliminary solder. Also in this case, the bondability between the preliminary solder and the underlying electroless nickel plating film, and thus between the semiconductor chip and the preliminary solder, is good.
【００２４】図５はチップサイズパッケージ４０の例を
示す。４２は半導体チップであり、絶縁フィルム（ポリ
イミドなど）４４上に形成されたパッド部４５にフリッ
プチップ接続されている。絶縁フィルム４４の他面側に
は、パッド部４５とビア４６を介して電気的に接続する
外部接続用のパッド部４７が形成されている。このパッ
ド部４７に上記と同様に無電解ニッケルめっき皮膜（図
示せず）、次いで無電解金めっき皮膜（図示せず）を形
成し、この無電解金めっき皮膜上に、接合すべきはんだ
ボール（外部接続端子）の融点よりも高い融点を有し、
かつ該外部接続端子よりも錫含有量の低い錫合金からな
る、はんだボール接合用のはんだ層（図示せず）を形成
し、このはんだ層上にはんだボール１４をリフロー加熱
して接合するのである。FIG. 5 shows an example of the chip size package 40. Reference numeral 42 denotes a semiconductor chip, which is flip-chip connected to a pad portion 45 formed on an insulating film (such as polyimide) 44. On the other side of the insulating film 44, a pad portion 47 for external connection electrically connected to the pad portion 45 via the via 46 is formed. An electroless nickel plating film (not shown) and then an electroless gold plating film (not shown) are formed on the pad portion 47 in the same manner as described above, and a solder ball (to be joined) is formed on the electroless gold plating film. Has a melting point higher than the melting point of the external connection terminals)
In addition, a solder layer (not shown) for joining solder balls, which is made of a tin alloy having a lower tin content than the external connection terminals, is formed, and the solder balls 14 are joined on the solder layer by reflow heating. .
【００２５】以上本発明につき好適な実施例を挙げて種
々説明したが、本発明はこの実施例に限定されるもので
はなく、発明の精神を逸脱しない範囲内で多くの改変を
施し得るのはもちろんである。Although the present invention has been described in detail with reference to the preferred embodiments, the present invention is not limited to these embodiments, and it should be noted that many modifications can be made without departing from the spirit of the invention. Of course.
【００２６】[0026]
【発明の効果】本発明に係る回路基板によれば、上述し
たように、無電解めっき皮膜上に、形成すべきはんだボ
ール等の錫合金からなる外部接続端子の融点よりも高い
融点を有し、かつ該外部接続端子よりも錫含有量の低い
錫合金からなる、前記外部接続端子接合用のはんだ層を
形成したので、外部接続端子を接合する際、錫−ニッケ
ル合金層が形成される割合を減少させ、界面のリンの濃
度がそれ程高くならず、外部接続端子の接合強度を向上
させうる回路基板を提供できる。According to the circuit board of the present invention, as described above, the electroless plating film has a melting point higher than the melting point of the external connection terminal made of a tin alloy such as a solder ball to be formed. Since the solder layer for joining the external connection terminals is formed of a tin alloy having a tin content lower than that of the external connection terminals, a rate at which the tin-nickel alloy layer is formed when the external connection terminals are joined. Can be provided, and the concentration of phosphorus at the interface does not increase so much, and the bonding strength of the external connection terminal can be improved.
【図１】ＢＧＡ型半導体パッケージの断面説明図、FIG. 1 is a cross-sectional explanatory view of a BGA type semiconductor package,
【図２】図１の部分拡大部、2 is a partially enlarged portion of FIG. 1,
【図３】図２に対応する部分の本実施形態の部分拡大
図、FIG. 3 is a partially enlarged view of a portion corresponding to FIG. 2 of the embodiment;
【図４】プリント配線基板に適用した場合の説明図、FIG. 4 is an explanatory diagram when applied to a printed wiring board,
【図５】チップサイズパッケージに適用した例を示す説
明図である。FIG. 5 is an explanatory diagram showing an example applied to a chip size package.
１０ ＢＧＡ型半導体パッケージ １２ 多層回路基板 １４ はんだボール（外部接続端子） １５ 半導体チップ搭載部 １６ 配線パターン １６ａ パッド部 １８ 無電解ニッケルめっき皮膜 ２０ 無電解金めっき皮膜 ２２ 絶縁層 ２４ ソルダーレジスト層 ２６ はんだ層 ３０ プリント配線基板 ４０ チップサイズパッケージ DESCRIPTION OF SYMBOLS 10 BGA type semiconductor package 12 Multilayer circuit board 14 Solder ball (external connection terminal) 15 Semiconductor chip mounting part 16 Wiring pattern 16a Pad part 18 Electroless nickel plating film 20 Electroless gold plating film 22 Insulating layer 24 Solder resist layer 26 Solder layer 30 printed wiring board 40 chip size package
Claims (3)
ルめっき皮膜が形成され、該無電解ニッケルめっき皮膜
上に金めっき皮膜が形成された回路基板において、 前記金めっき皮膜上に、形成すべきはんだボール等の錫
合金からなる外部接続端子の融点よりも高い融点を有
し、かつ該外部接続端子よりも錫含有量の低い錫合金か
らなる、前記外部接続端子接合用のはんだ層が形成され
ていることを特徴とする回路基板。1. A circuit board having an electroless nickel plating film formed on a pad portion of a wiring pattern and a gold plating film formed on the electroless nickel plating film, wherein a solder to be formed is formed on the gold plating film. The solder layer for joining the external connection terminals, which has a melting point higher than the melting point of the external connection terminals made of a tin alloy such as a ball and is made of a tin alloy having a lower tin content than the external connection terminals, is formed. A circuit board, comprising:
が接合されていることを特徴とする請求項１記載の回路
基板。2. The circuit board according to claim 1, wherein the external connection terminal is joined via the solder layer.
請求項２記載の回路基板。3. The circuit board according to claim 2, wherein said external connection terminals are solder balls.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30274598A JP2000133739A (en) | 1998-10-23 | 1998-10-23 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30274598A JP2000133739A (en) | 1998-10-23 | 1998-10-23 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000133739A true JP2000133739A (en) | 2000-05-12 |
Family
ID=17912645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30274598A Pending JP2000133739A (en) | 1998-10-23 | 1998-10-23 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000133739A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6548898B2 (en) | 2000-12-28 | 2003-04-15 | Fujitsu Limited | External connection terminal and semiconductor device |
-
1998
- 1998-10-23 JP JP30274598A patent/JP2000133739A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6548898B2 (en) | 2000-12-28 | 2003-04-15 | Fujitsu Limited | External connection terminal and semiconductor device |
| US6784543B2 (en) | 2000-12-28 | 2004-08-31 | Fujitsu Limited | External connection terminal and semiconductor device |
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