JP2000114173A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high-performance semiconductor device by providing the semiconductor film having the crystal property that can be practically regarded as the single crystal and assembling the circuit with a TFT. SOLUTION: In this manufacture, following steps are provided, in a first step, heat annealing is performed for the semiconductor film including germanium, and the semiconductor film including a crystal is formed; in a next step, oxidization is performed for the semiconductor film including the crystal; in a next step, laser annealing is performed for the semiconductor film, whose ixidization is performed; and in the last step, furnace annealing is performed for the semiconductor film after laser annealing. The laser annealing is performed under the energy density of 250-5,000 ml/cm2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique relating to a semiconductor device including a thin film transistor (hereinafter, referred to as a TFT) using a semiconductor thin film as a circuit and a method for manufacturing the same. Note that in this specification, a semiconductor device generally refers to a device that functions using a semiconductor.

Therefore, the term semiconductor device used in the claims includes not only a single semiconductor element such as a TFT but also a semiconductor device.
It also includes an electro-optical device having a TFT, a semiconductor circuit, and an electronic device equipped with the same.

[0003]

2. Description of the Related Art In recent years, TFTs used for electro-optical devices such as active matrix type liquid crystal display devices have been actively developed. An active matrix liquid crystal display device is a monolithic display device in which a pixel matrix circuit and a driver circuit are provided on the same substrate.

[0004] Recently, attempts have been made to form a semiconductor circuit having a function equivalent to that of a conventional IC using TFTs provided on a substrate. For example, development of a system-on-panel incorporating a logic circuit such as a gamma correction circuit, a memory circuit, and a clock generation circuit has been studied.

Since such driver circuits and logic circuits need to operate at high speed, it is inappropriate to use an amorphous semiconductor film (typically, an amorphous silicon film) as an active layer. Therefore, at present, a crystalline semiconductor film (typically, a polysilicon film) is being studied.

[0006]

SUMMARY OF THE INVENTION However, TFT
When circuit performance comparable to that of a conventional IC is required for a circuit assembled in the above, a crystalline semiconductor film formed by the conventional technology has sufficient performance to satisfy the specifications of the circuit. It has become difficult to manufacture TFTs.

Therefore, an object of the present invention is to realize a high-performance semiconductor device by fabricating a TFT having better electric characteristics than a TFT using a conventional polysilicon film and assembling a circuit with the TFT. .

[0008]

The gist of the present invention disclosed in this specification is a first step of adding germanium to a semiconductor film containing an amorphous, and after the first step, the step of adding the amorphous A second step of changing the semiconductor film including the crystal into a semiconductor film including the crystal, a third step of oxidizing the semiconductor film including the crystal to reduce the film thickness, and a semiconductor film including the crystal after the third step. A laser annealing process with an energy density of 250 to 5000 mJ / cm ² , and a fifth process of performing a furnace annealing process on the semiconductor film including the crystal after the fourth process. Features.

[0009] Another gist of the present invention is that a first step of adding germanium to a semiconductor film containing an amorphous phase, and that after the first step, the semiconductor film containing an amorphous phase is crystallized. A second step of changing the semiconductor film including the crystal, a third step of oxidizing the semiconductor film including the crystal to reduce the film thickness, and
250 to 5000 for the semiconductor film containing the crystal after the process
a fourth step of performing laser annealing at an energy density of mJ / cm ² , and a fifth step of performing a furnace annealing at 900 to 1200 ° C. in a reducing atmosphere on the semiconductor film including the crystal after the fourth step in a reducing atmosphere. , Are included.

In the second step, the semiconductor film containing a crystal includes all the semiconductor films containing a crystal component, and more specifically, a single crystal semiconductor film, a polycrystalline semiconductor film, a microcrystalline semiconductor film, and an amorphous semiconductor film. Refers to a semiconductor film in which only part of the film is crystallized, or a semiconductor film which can be substantially regarded as a single crystal.

Note that a semiconductor film that can be substantially regarded as a single crystal is a semiconductor film formed by assembling a plurality of crystal grains, but having a crystallinity such that the plane orientation of each crystal grain is uniform. Has a specific orientation on the entire film surface.

The semiconductor film containing amorphous includes all the semiconductor films containing an amorphous component, and only a part of the microcrystalline semiconductor film, the amorphous semiconductor film, and the amorphous semiconductor film is crystallized. Semiconductor film.

In this specification, a silicon film is taken as a typical example of the semiconductor film, but a germanium film or a silicon germanium film (represented by Si _1-x Ge _x (0 <X <1)) Needless to say, such a semiconductor film as described above can also be used in the present invention.

In the fourth step of performing the laser annealing, KrF (wavelength: 248 nm), XeCl
(Wavelength 308 nm), excimer laser light using ArF (wavelength 193 nm) or the like as an excitation gas may be used. The beam shape of the laser light may be linear or planar.

The light energy that can be used in the present invention is not limited to excimer laser light.
Ultraviolet light or infrared light may be used. In that case, strong light having the same light intensity as the laser light may be irradiated from an ultraviolet lamp or an infrared lamp.

Further, in the fifth step, the furnace annealing treatment is not particularly limited to a treatment atmosphere, but is preferably performed in a reducing atmosphere. The reducing atmosphere refers to a hydrogen atmosphere, an ammonia atmosphere, or an inert atmosphere containing hydrogen or ammonia (such as a mixed atmosphere of hydrogen and nitrogen or a mixed atmosphere of hydrogen and argon). The processing temperature is 900 to 12
The temperature is preferably set to 00 ° C (preferably 1000 to 1100 ° C).

This step has the effect of first planarizing the surface of the semiconductor film containing crystals. This is the result of enhanced surface diffusion of semiconductor atoms in an attempt to minimize surface energy. At the same time, this step also has an effect of remarkably reducing crystal grain boundaries and defects existing in crystal grains. This is due to the effect of terminating dangling bonds by hydrogen, the effect of removing impurities by hydrogen, and the resulting recombination of semiconductor atoms. In order to obtain these effects, 900
Heat treatment at ~ 1200 ° C is required.

Note that the surface of the semiconductor film including crystals can be planarized even in an inert atmosphere (nitrogen atmosphere, helium atmosphere, or argon atmosphere). However, it is preferable to reduce the natural oxide film by using a reducing action, since many silicon atoms having high energy are generated, and as a result, the flattening effect is enhanced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention having the above configuration will be described in detail with reference to the following examples.

[0020]

[Embodiment 1] In this embodiment, a process of manufacturing a TFT on a substrate by implementing the present invention will be described.
FIG. 1 is used for the description.

First, a quartz substrate 101 was prepared. A material having high heat resistance must be selected for the substrate. Instead of a quartz substrate, a highly heat-resistant material such as a silicon substrate, a ceramic substrate, a crystallized glass substrate, or a metal substrate can be used.

However, when a quartz substrate is used, a base film may or may not be provided, but when another material is used, an insulating film is preferably provided as a base film. As the insulating film, a silicon oxide film (SiOx), a silicon nitride film (Six N
y), a silicon oxynitride film (SiOxNy), an aluminum nitride film (AlxNy), or a laminated film thereof.

It is effective to use a base film in which a heat-resistant metal layer and a silicon oxide film are laminated because the heat radiation effect is greatly increased. The heat dissipation effect is sufficient even with the above-described laminated structure of the aluminum nitride film and the silicon oxide film.

When the quartz substrate 101 is prepared in this way,
A semiconductor film (amorphous silicon film in this embodiment) 102 having a thickness of 90 nm was formed. In this embodiment, disilane (Si ₂ H ₆ ) is used as a film forming gas for the amorphous silicon film 102.
And a film was formed by a reduced pressure thermal CVD method at 450 ° C. At this time, C (carbon), N (nitrogen) and O
It is important to thoroughly control the concentration of impurities such as (oxygen). This is because the presence of many of these impurities hinders the progress of crystallization.

The applicant has determined that the concentration of carbon and nitrogen is 5 × 10
¹⁸ atoms / cm ³ or less (preferably 5 × 10 ¹⁷ atoms / cm ³ or less) and oxygen concentration of 1 × 10 ¹⁹ atoms / cm ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less). The impurity concentration was controlled. The metal element was controlled to be 1 × 10 ¹⁷ atoms / cm ³ or less. If such concentration control is performed at the film formation stage, the impurity concentration will not increase during the TFT manufacturing process as long as external contamination is prevented.

Also, a plasma CVD method may be used as long as film quality equivalent to that of an amorphous silicon film formed by a low pressure thermal CVD method can be obtained. Further, the semiconductor does not need to be completely amorphous, and a microcrystalline silicon film or the like may be formed.

Further, instead of the silicon film, silicon germanium (Si) containing germanium in the silicon film is used.
A semiconductor film such as xGe1-x (represented by 0 <X <1) may be used. In that case, it is desirable that the germanium contained in the silicon germanium be 5 atomic% or less.

Next, germanium (Ge) was added to the amorphous silicon film 102. In this embodiment, an ion implantation method (with mass separation) is used as a method for adding germanium, but a plasma doping method (without mass separation) or a laser doping method can also be used. (Fig. 1 (A))

In this embodiment, germane (Ge) is used as the excitation gas.
Using H ₄ ), germanium is added by an ion implantation method at an acceleration voltage of 30 keV, an RF power of 5 W, and a dose of 1 × 10 ¹⁴ atoms / cm ² . Of course, it is not necessary to limit to this condition, and 1 × 10 ^{14 to} 5 × 10 ¹⁹ atoms / cm ³ (typically 1 × 10 ¹⁹ atoms / cm ³ )
It may be adjusted so that germanium is added at a concentration of 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ ).

If the amount of germanium added to the amorphous silicon film is not more than 1 × 10 ¹⁴ atoms / cm ³ (typically, not less than 1 × 10 ¹⁶ atoms / cm ³ ), the effect of promoting crystallization is utilized as a catalyst. Can not do. On the other hand, if the addition exceeds 5 × 10 ¹⁹ atoms / cm ³ , the melting point of the amorphous silicon film is too low, and even at a temperature of about 900 ° C., it is not preferable. Therefore, it is desirable to set the upper limit of the addition amount to about 1 × 10 ¹⁸ atoms / cm ^{3 for} safety.

Further, a method of adding in advance when forming the morphous silicon film may be used. In that case, germane (GeH ₄ ) may be used as a deposition gas.

After the germanium addition step was completed, a heat treatment was performed at 450 ° C. for about one hour to remove hydrogen from the amorphous silicon film 102. Thereafter, a heat treatment was performed at a temperature of 500 to 700 ° C. (typically 550 to 650 ° C.) for 4 to 24 hours in an inert atmosphere, a reducing atmosphere, or an oxidizing atmosphere to obtain a polysilicon film 103. The polysilicon film 103 contains germanium at a concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ . (FIG. 1 (B))

When the state shown in FIG. 1B is obtained,
A furnace annealing treatment (heat treatment using an electric furnace) was performed at 1000 ° C. for 30 minutes in an oxidizing atmosphere. At this time, the thickness of the polysilicon film 103 was reduced by a thermal oxidation process (thinning process), and a polysilicon film 104 thinner than the polysilicon film 103 was formed. (Fig. 1 (C))

Although not shown in FIG. 1C,
On the polysilicon film 104, a thermal oxide film is formed. This thermal oxide film may be removed or may be used as a protective film in the next laser annealing step.

In the thermal oxidation step, defects and the like in the polysilicon film were repaired by excess silicon atoms generated when the oxidation reaction progressed, and a polysilicon film with very few defects could be obtained. Further, by reducing the thickness of the polysilicon film, the thickness was initially 90 nm, but was increased to 60 nm.

Further, the oxidation reaction proceeds while shaving the surface layer of the polysilicon film, so that the formed polysilicon film 104 becomes a semiconductor film having a very flat surface. This will work effectively in reducing the level at the interface between the active layer and the gate insulating film of the TFT in the future.

If the thinning step is performed a plurality of times, the flatness of the polysilicon film is further improved. In that case, the thermal oxidation step and the step of removing the thermal oxide film are alternately repeated.

In this embodiment, a thinning process is employed because an amorphous silicon film having a thickness of 90 nm is used as the initial film. However, if it is not necessary to reduce the thickness of the initial film to 50 nm or less and to make it thinner, the thinning process is performed. It is also possible to omit the step.

Further, germanium easily becomes germanium oxide and sublimates by heat treatment at 700 ° C. or higher.
That is, germanium inevitably sublimes when the thinning step of FIG. 1C is performed, and is removed or reduced from the polysilicon film 104.

It is confirmed by differential thermal analysis that the temperature at which the amorphous silicon film is crystallized is around 600 ° C. when germanium is used as a catalyst element for promoting the crystallization of the amorphous silicon film.
Actually, it varies somewhat depending on the processing temperature.
650 ° C. may be considered as the temperature required for crystallization. That is, if the temperature at the time of crystallization is raised only to 650 ° C., it is almost impossible for germanium to sublime at the time of crystallization.

As described above, the catalyst element (germanium) used in the crystallization of the amorphous silicon film can be removed from the polysilicon film at the same time as performing the thinning step without increasing the number of steps. This is a feature of the present invention.

Also, a halogen element may be added to the heat treatment atmosphere. Since the halogen element combines with germanium to form a volatile germanium halide, the gettering effect can be promoted.

When the state shown in FIG. 1C is obtained,
Next, the polysilicon film 104 was irradiated with excimer laser light. In this embodiment, laser annealing was performed by pulse oscillation type excimer laser light using XeCl (wavelength 308 nm) as an excitation gas. The beam shape of the excimer laser may be a linear beam, but a planar beam may be used to enhance the uniformity of processing. (Figure 1
(D))

Note that an excimer laser beam using KrF, KrCl, ArF or the like as an excitation gas or another ultraviolet laser may be used. When infrared light is used, the polysilicon film 104 may be irradiated with strong light emitted from an infrared lamp.

In this embodiment, a linear laser beam having an oscillation frequency of 30 Hz and a beam shape of 145 × 0.41 mm was used. Also,
The laser beam scans from one end to the other end of the substrate at 1.2 mm / sec, and the overlap between adjacent linear laser beams is
%.

In this embodiment, the laser energy density is 250 to 5000 mJ / cm ² (preferably 450 to
It is preferably performed under the condition of 1000 mJ / cm ² ). In this embodiment, the laser energy density was set to 550 mJ / cm ² .
Here, a method for measuring the laser energy density in this specification will be described.

First, the light intensity (E ₀ ) of the laser light oscillated from the laser oscillator is actually measured by a power meter. However, the laser light after passing through the power meter is dimmed according to the transmittance (a) of the attenuator, and further dimmed according to the transmittance (b) of the optical system. The value obtained by dividing the light intensity of the laser light thus reduced by the laser irradiation area (A) is the laser energy density (E). This can be expressed as E = (E ₀ × a × b) / A.

Next, the polysilicon film 105 obtained by performing the laser annealing process was subjected to furnace annealing at 1000 ° C. for 2 hours. In this embodiment, the processing atmosphere is a hydrogen atmosphere, but there is no problem as long as the atmosphere is a reducing atmosphere. Further, the object of improving the crystallinity even in an inert atmosphere such as a nitrogen atmosphere is achieved. (Figure 1
(E))

It is desirable that the surface of the polysilicon film 105 be cleaned with a hydrofluoric acid-based etchant before performing the furnace annealing step. That is, it is effective to remove the natural oxide film and terminate the silicon atoms on the surface with hydrogen to prevent the natural oxide film from being formed before the actual processing.

However, it is particularly necessary to keep the concentration of oxygen or oxygen compounds (for example, OH groups) contained in the atmosphere at 10 ppm or less (preferably 1 ppm or less). Otherwise, the flattening effect by heat treatment in a reducing atmosphere will be weakened.

Thus, a polysilicon film 106 was obtained. The polysilicon film 106 had a very flat surface by hydrogen annealing at a temperature as high as 1000 ° C. Further, since annealing was performed at a high temperature, almost no stacking faults or the like were present in the crystal grains.

Further, as a result of the applicant's observation of the polysilicon film obtained in the steps of this embodiment by Raman measurement, the Raman peak value was 517 to 520 cm ^-1 (typically 518 to 51 cm ^-1 ).
9 cm ^-1 ). The half width at half maximum is 2.2 to 3.0 cm.
^-1 (typically 2.4 to 2.6 cm ^-1 ).

The Raman peak value of 518 to 519 cm ^-1 is on the very high wavenumber side, which indicates that the polysilicon film obtained in this embodiment has a crystal very close to a single crystal. In addition, the value of 2.4 to 2.6 cm ^-1 is very small (a single crystal silicon film measured as a reference has a value of 2.
It was 1 cm ^-1 . ), That is, high crystallinity.

In this specification, the Raman peak value refers to an Ar laser having a wavelength of 514.5 cm ^{-1 at} a wavelength of 1.0 × 1.
A Lorentz distribution fitting is performed on a Raman spectrum obtained when the semiconductor film including the crystal (polysilicon film in this embodiment) is irradiated with a light intensity of 0 ^{5 to} 1.3 × 10 ⁵ W / cm ^2. This is the peak value obtained when In addition, a Raman measuring device called “Ramascope microscope Raman device system 2000” of Renishaw was used for the actual measurement.

Further, the half width at half maximum means that an Ar laser having a wavelength of 514.5 cm ^-1 is used in an amount of 1.0 × 10 ^{5 to} 1.3 × 10 ⁵ W / cm ^2.
This is a half of the half-width obtained when the fitting by Lorentz distribution is performed on the Raman spectrum obtained when the semiconductor film including the crystal is irradiated with the light intensity. This was also measured with the above-mentioned Raman measuring device.

Although the Raman peak value and the half width at half maximum defined by the above definitions, the ratio between the Raman peak value and the half width at half maximum (Raman peak value / half width at half maximum) of the polysilicon film 106 of this embodiment is 170 to 240 (representative). Specifically 190 to 220).

When the polysilicon film 106 having extremely high crystallinity was thus obtained, the polysilicon film 106 was patterned to form an active layer 107. In this embodiment, the heat treatment is performed in a hydrogen atmosphere before forming the active layer. However, the heat treatment may be performed after forming the active layer. In that case, it is preferable that the patterning reduces the stress generated in the polysilicon film.

Then, a silicon oxide film 108 having a thickness of 10 nm was formed on the surface of the active layer 107 by performing a thermal oxidation process. This silicon oxide film 108 functions as a gate insulating film. The thickness of the active layer 107 was reduced to 45 nm because the thickness of the active layer 107 was reduced by 5 nm due to the oxidation. Finally 10
The thickness of the initial semiconductor film (semiconductor film formed first) must be determined in consideration of film reduction due to thermal oxidation so that an active layer (especially a channel formation region) having a thickness of about 50 nm remains. is necessary.

After the gate insulating film 108 was formed, a conductive polysilicon film was formed thereon, and a gate wiring 109 was formed by patterning. (Fig. 2 (A))

In this embodiment, polysilicon having N-type conductivity is used as the gate wiring, but the material is not limited to this. In particular, it is effective to use tantalum, a tantalum alloy, or a stacked film of tantalum and tantalum nitride to reduce the resistance of the gate wiring. If a low-resistance gate wiring is aimed at, it is effective to use copper or a copper alloy.

When the state shown in FIG. 2A was obtained, an impurity imparting N-type conductivity or P-type conductivity was added to form an impurity region 110. At this time, the impurity concentration is
It was determined in consideration of the impurity concentration in the region. In this embodiment, 1 ×
Although arsenic was added at a concentration of 10 ¹⁸ atoms / cm ³ , neither the impurity nor the concentration need be limited to this embodiment.

Next, 5 to 10
A thin silicon oxide film 111 of about nm was formed. This may be formed using a thermal oxidation method or a plasma oxidation method. This silicon oxide film 111 functions as an etching stopper in the next sidewall formation step.

After the silicon oxide film 111 serving as an etching stopper was formed, a silicon nitride film was formed and etched back to form a sidewall 112. Thus, the state shown in FIG. 2B was obtained.

Although the silicon nitride film is used as the sidewall in this embodiment, a polysilicon film or an amorphous silicon film can be used. Needless to say, if the material of the gate wiring changes, the material that can be used as the sidewall changes accordingly.

Next, impurities of the same conductivity type as above were added again. The concentration of the impurity added at this time was higher than that in the previous step. In the present embodiment, arsenic is used as an impurity and the concentration is 1 × 10 ²¹ atoms / cm ³ , but it is not necessary to limit to this. The source region 113, the drain region 114, the LDD region 115, and the channel formation region 116 were defined by the impurity doping process. (Fig. 2 (C))

After the respective impurity regions were formed, the impurities were activated by heat treatment such as furnace annealing, laser annealing or lamp annealing.

Next, the gate wiring 109 and the source region 11
3 and the silicon oxide film formed on the surface of the drain region 114 were removed to expose those surfaces. And
A heat treatment process was performed by forming a cobalt film (not shown) of about 5 nm. This heat treatment causes a reaction between cobalt and silicon to form a silicide layer (cobalt silicide layer).
117 was formed. (FIG. 2 (D))

This technique is a known salicide technique.
Therefore, titanium or tungsten may be used instead of cobalt, and annealing conditions and the like may be referred to a known technique. In this embodiment, the lamp annealing process is performed by irradiating infrared light.

After the formation of the silicide layer 117, the cobalt film was removed. Thereafter, an interlayer insulating film 118 having a thickness of 1 μm was formed. As the interlayer insulating film 118, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a resin film (polyimide, acrylic, polyamide, polyimide amide, benzocyclobutene (BCB), or the like) may be used. Further, these insulating films may be stacked in any combination.

Next, a contact hole was formed in the interlayer insulating film 118 to form a source wiring 119 and a drain wiring 120 made of a material containing aluminum as a main component. Finally, the entire device was subjected to furnace annealing at 300 ° C. for 2 hours in a hydrogen atmosphere to complete hydrogenation.

Thus, a TFT as shown in FIG. 2D was obtained. The structure described in this embodiment is an example, and the TFT structure to which the present invention can be applied is not limited to this. Therefore, the present invention can be applied to any known TFT. Also, the numerical conditions in the steps after the formation of the polysilicon film 106 need not be limited to the present embodiment. Furthermore, there is no problem if a known channel doping step (an impurity adding step for controlling a threshold voltage) is introduced somewhere in this embodiment.

In this embodiment, the concentration of impurities such as C, N and O is thoroughly controlled at the stage of forming an amorphous silicon film as an initial film.
The concentration of each impurity contained in the T active layer is such that the concentration of carbon and nitrogen is 5 × 10 ¹⁸ atoms / cm ³ or less (preferably 5 × 1
0 ¹⁸ atoms / cm ³ or less), and the oxygen concentration is 5 × 10 ¹⁸ atoms / c
m ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less). The metal element except nickel is 1 × 10 ¹⁷
atoms / cm ³ or less.

It is needless to say that the present invention can be easily applied not only to a top gate structure but also to a bottom gate structure represented by an inverted staggered TFT.

In this embodiment, an N-channel TFT has been described as an example. However, a P-channel TFT can be easily manufactured by combining with a known technique. Furthermore, if known techniques are combined, an N-channel TF
It is also possible to form a CMOS circuit by forming and combining T and P-channel TFTs complementarily.

Further, a pixel electrode (not shown) electrically connected to the drain wiring 120 in the structure of FIG.
Is formed by known means, it is easy to form a pixel switching element of an active matrix display device. That is, the present invention can be implemented when an active matrix type electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device is manufactured.

(Embodiment 2) In this embodiment, the crystallization of an amorphous silicon film as an initial film is described in Japanese Patent Application Laid-Open No. 8-7832.
An example in the case of performing the technique described in Japanese Patent Application Publication No. 9-No. 9 will be described with reference to FIG.

First, a quartz substrate 30 provided with an insulating film on its surface
1 is prepared, and an amorphous silicon film (not shown) and a silicon oxide film (not shown) are continuously formed thereon without opening to the atmosphere. Next, the silicon oxide film is patterned to form a mask 302 having an opening.

Next, a germanium addition step is performed using the ion implantation method under the conditions described in the first embodiment. Of course, a plasma doping method or a laser doping method may be used. By this step, a germanium added region 303 is formed. (FIG. 3 (A))

Next, a furnace annealing step of 570 ° C. for 14 hours is performed to form a lateral growth region 304 made of polysilicon.
Get. Since the rod-shaped crystal grows in a direction substantially parallel to the substrate, the lateral growth region 304 becomes a semiconductor film having less defects and trap levels than a polysilicon film in which nuclei are randomly generated. (FIG. 3 (B))

Further, in the state of FIG. 3B, a semiconductor film in which a region which remains as an amorphous component and a lateral growth region (a region having a crystalline component) is obtained. In this specification, such a film is also referred to as a semiconductor film (or a semiconductor film including crystals).

When the state shown in FIG. 3B is obtained,
The mask 302 is removed with a hydrofluoric acid-based etchant. After that, furnace annealing is performed in an oxygen atmosphere at 1000 ° C. for 30 minutes to perform a thermal oxidation step (thinning step).
The thermal oxide film (not shown) formed at this time may be removed here or may be left until the next laser annealing process is performed. (FIG. 3 (C))

In this step, germanium contained in the lateral growth region 304 becomes germanium oxide and sublimates. Thus, the concentration of germanium in the film was 1 × 10 ¹⁷ at
A lateral growth region 305 reduced by m below oms / cm ³ is obtained.

After the step of FIG. 3C is completed, a laser annealing process is performed using XeCl excimer laser light to obtain a lateral growth region 306. The laser irradiation conditions in this embodiment are the same as those in the first embodiment. (FIG. 3
(D))

After the lateral growth region 306 that has undergone the laser annealing process is obtained, a furnace annealing process is further performed at 1100 ° C. for 2 hours in an atmosphere in which hydrogen and nitrogen are mixed. Thus, a lateral growth region 307 is obtained. (FIG. 3
(E))

Thereafter, an active layer formed using only the lateral growth region 307 by patterning is formed.
The TFT may be completed through the same steps as described above. Since the detailed description has been made in the first embodiment, the description is omitted here.

The lateral growth region 30 formed as described above
7 has the same crystallinity as the polysilicon film described in the first embodiment. That is, the entire film surface shows a specific orientation,
This is a semiconductor film which can be substantially regarded as a single crystal.

The Raman peak value and the half width at half maximum obtained by the Raman measurement are the same as those described in the first embodiment.

Embodiment 3 In this embodiment, an example of a reflection type liquid crystal display device manufactured according to the present invention is shown in FIG.
A well-known means may be used for a method of manufacturing a pixel TFT (pixel switching element) and a cell assembling step, and a detailed description thereof will be omitted.

In FIG. 4A, reference numeral 11 denotes a substrate having an insulating surface (ceramic substrate provided with a silicon oxide film);
Is a pixel matrix circuit, 13 is a source driver circuit,
14 is a gate driver circuit, 15 is a counter substrate, 16 is an FPC (flexible printed circuit), and 17 is a signal processing circuit. As the signal processing circuit 17, D / A
Conventional ICs such as converters, gamma correction circuits, and signal division circuits
Thus, a circuit for performing the processing similar to the above can be formed. Of course, it is also possible to provide an IC chip on a substrate and perform signal processing on the IC chip.

Further, in this embodiment, a liquid crystal display device is described as an example. However, if the display device is an active matrix type display device, the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromics) display device. It goes without saying that the invention can be applied.

Here, the driver circuit 13 shown in FIG.
FIG. 4B shows an example of a circuit constituting the circuit 14. In addition,
Since the TFT portion has already been described in the first embodiment, only necessary portions will be described here.

In FIG. 4B, 401 and 402 indicate N
A channel TFT 403 is a P-channel TFT, and a TFT 401 and a TFT 403 constitute a CMOS circuit. Reference numeral 404 denotes an insulating layer formed of a laminated film of a silicon nitride film / silicon oxide film / resin film, on which a titanium wiring 405 is provided, and the above-described CMOS circuit and the TFT 402 are electrically connected. The titanium wiring is further covered with an insulating layer 406 made of a resin film. The two insulating layers 404 and 406 also have a function as a planarization film.

The pixel matrix circuit 1 shown in FIG.
FIG. 4C shows a part of the circuit constituting the second circuit. FIG.
In FIG. 4C, reference numeral 407 denotes a pixel TFT formed of an N-channel TFT having a double gate structure, and a drain wiring 408 is formed so as to largely spread in a pixel region. Note that a single gate structure, a triple gate structure, or the like may be employed in addition to the double gate structure.

An insulating layer 404 is provided thereon, and a titanium wiring 405 is provided thereon. At this time, a recess is formed in a part of the insulating layer 404, and only the lowermost silicon nitride and silicon oxide are left.
Thus, an auxiliary capacitance is formed between the drain wiring 408 and the titanium wiring 405.

Further, the titanium wiring 405 provided in the pixel matrix circuit has an electric field shielding effect between the source wiring or the drain wiring and a pixel electrode to be provided later. Further, in a gap between a plurality of provided pixel electrodes, it also functions as a black mask.

Then, an insulating layer 406 is provided to cover the titanium wiring 405, and a pixel electrode 409 made of a reflective conductive film is formed thereon. Of course, the surface of the pixel electrode 409 may be devised to increase the reflectance.

Further, although an alignment film and a liquid crystal layer are actually provided on the pixel electrode 409, the description is omitted here.

The reflection type liquid crystal display device having the above configuration can be manufactured by using the present invention. Of course, a transmission type liquid crystal display device can be easily manufactured by combining with a known technique.

Although not distinguished in the drawings, the thickness of the gate insulating film can be made different between a pixel TFT forming a pixel matrix circuit and a CMOS circuit forming a driver circuit or a signal processing circuit.

In the pixel matrix circuit, since the driving voltage applied to the TFT is high (10 V or more), it is 50 to 200 nm.
A gate insulating film having a thickness (preferably 100 to 150 nm) is required. On the other hand, in a driver circuit or a signal processing circuit, a driving voltage applied to a TFT is low (1 to 5 V), and a high-speed operation is required.
It is effective to make the thickness 30 nm (preferably 5 to 10 nm) smaller than the pixel TFT.

(Embodiment 4) The present invention can be applied to all conventional IC technologies. That is, the present invention can be applied to all semiconductor circuits currently on the market. For example, RISC processor integrated on one chip, ASIC
It may be applied to a microprocessor such as a processor, a signal processing circuit typified by a liquid crystal driver circuit (D / A converter, γ correction circuit, signal division circuit, etc.), and a portable device (cellular phone, PHS, mobile computer) ) May be applied to the high frequency circuit.

FIG. 5 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.

Of course, the microprocessor shown in FIG. 5 is a simplified example, and an actual microprocessor is designed for various circuits depending on the application.

However, even if a microprocessor having any function functions as a center, it is an IC (Integer).
grated circuit) 28. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected by ceramic or the like.

An integrated circuit formed on the semiconductor chip 29 is composed of an N-channel TFT 30 and a P-channel TFT 31 having the structure of the present invention. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.

The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Representative electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (an automobile, a train, or the like) is also included.

(Embodiment 5) The electro-optical device of the present invention is
It is used as a display for various electronic devices. Such electronic devices include video cameras, digital cameras, front projectors, rear projectors (projection TVs), goggle displays,
Examples include a car navigation system, a personal computer, and a portable information terminal (mobile computer, mobile phone, electronic book, and the like). One example is shown in FIG.

FIG. 6A shows a mobile phone, and a main body 200.
1, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 2006
It consists of. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.

FIG. 6B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 6C shows a mobile computer (mobile computer), which includes a main body 2201 and a camera section 2.
202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 and other signal control circuits.

FIG. 6D shows a goggle type display, which includes a main body 2301, a display device 2302, and an arm 230.
3 The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 6E shows a rear type projector, which includes a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The present invention can be applied to the display device 2403 and other signal control circuits.

FIG. 6F shows an electronic book, which has a main body 250.
1, display devices 2502, 2503, storage medium 2504,
It is composed of an operation switch 2505 and an antenna 2506. The present invention can be applied to the display devices 2502 and 2503 and other signal control circuits.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields.

(Embodiment 6) A semiconductor film containing crystals obtained by the steps shown in Embodiments 1 to 4 shows a specific orientation over the entire film surface. That is, even if the crystal grains have a form such as a polycrystalline semiconductor film formed by assembling individual crystal grains, 80% or more (typically 90% or more) of the entire crystal grains have the same crystal plane (orientation). Surface). Such a crystal plane occupying 80% or more of the whole is referred to as a main orientation plane.

The main crystal planes that can be taken by the semiconductor film (semiconductor film including crystals) formed by the process of the present invention are as follows:
{110} plane, {100} plane, {111} plane, {31}
1｝, {511}, or {110} and {100}
It is one of the crystal faces where the face and the face are mixed. At present, it is not known which crystal plane is the main orientation plane.

That is, in the semiconductor film (semiconductor film containing crystals) formed by the process of the present invention, any one of the above six types of crystal planes is 80% or more of the total crystal planes that can be present on the film plane (typically). 90% or more).

As is well known using single crystal silicon as an example, the interface properties vary depending on the crystal plane. The plane orientation at which the interface state density (Qss) becomes the smallest is the {100} plane, followed by the {511} plane, the {311} plane, and the {111} plane.
Plane, a mixed crystal plane of {110} plane and {100} plane,
It becomes larger in the order of the {110} plane. It is known that the {511} plane has an interface state density comparable to the {100} plane.

Therefore, if the main orientation plane of the semiconductor film formed by the process of the present invention is the {100} plane, the interface state density between the active layer and the gate insulating film becomes very small. In that case, a semiconductor device having performance comparable to a conventional IC can be realized. As will be described later, the TFT actually manufactured using the present invention can form a circuit having electrical characteristics comparable to those of a conventional IC.

Further, in the process of the present invention, furnace annealing in a reducing atmosphere or in an inert atmosphere performed after the laser annealing is very effective in flattening the interface between the active layer and the gate insulating film. . In particular, when the treatment is performed in a reducing atmosphere, an extremely flat surface can be obtained by accelerated surface diffusion of semiconductor atoms on the surface of the semiconductor film.

The present applicant measured the surface unevenness using an AFM (intermolecular force microscope). As a result, the PV value of the unevenness within the range of 1 μm ² (the height between the top of the protrusion and the bottom of the recess) was measured. Is 10 nm or less (typically 5 nm or less), and the PV value of unevenness is 20 nm or less (typically 10 nm or less) within a range of 10 μm ^2.
nm or less).

(Example 7) Representative electrical characteristics of a TFT manufactured by carrying out the present invention were as follows. (1) When the drain voltage is 1 V, the sub-threshold coefficient as an index of the switching performance (the agility of switching on / off operation) is 60 to 150 mV / decade for both the N-channel TFT and the P-channel TFT (typically, 80-10
0mV / decade). (2) The field effect mobility (μFE) which is an index of the operation speed of the TFT is 200 to 500 cm ² / Vs (typically 300 to 400 cm ² / V) for an N-channel TFT when the drain voltage is 1 V.
s), which is as large as 100 to 300 cm ² / Vs (typically 150 to ²⁰⁰ cm ² / Vs) for a P-channel TFT. (3) The threshold voltage (V
th) is an N-channel type T when the drain voltage is 14V.
-1.0 to 2.5 V (typically -0.5 to 1.5 V) for FT, -2.5 to 1.0 V (typically -1.5 to 0.5 V) for P-channel TFT
And small.

Further, a normal probability graph was created based on data obtained by measuring 500 TFTs of the present invention, and the characteristic variation was estimated using the graph. As a result, it was found that 90 out of 100 pieces (typically 95 pieces) fall within the range of the electric characteristics.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

(Embodiment 8) In this embodiment, a shift register as a liquid crystal driver circuit was manufactured and the operating frequency was confirmed. As a result, an output pulse with an operating frequency of 80 to 200 MHz (typically 100 to 150 MHz) was obtained in a shift register circuit with a power supply voltage of 5 V and 50 stages.

(Embodiment 9) In Embodiments 1 and 2, the case where an ion implantation method or the like is used as a means for adding germanium to an amorphous silicon film has been described. In this embodiment, a germanium film is formed. An example in which the compound is added later by thermal diffusion will be described.

In the case of this embodiment, after forming the amorphous silicon film, 1 to 50 nm (typically, 10 to 50 nm) is formed thereon.
A 20 nm) germanium film is formed. As a film formation method, a gas phase method such as a plasma CVD method, a low pressure thermal CVD method, or a sputtering method can be used.

Note that the germanium film may be formed so as to directly touch the amorphous silicon film, or may be provided via an insulating film. In the case where an insulating film is formed, if the insulating film is too thick, thermal diffusion of germanium into the silicon film is hindered. Therefore, the thickness is preferably set to 10 to 30 nm.

When the crystallization step is performed in a state where the germanium film is provided, the germanium is thermally diffused into the amorphous silicon film by being heated, and functions as a catalytic element for promoting crystallization.

The germanium film after the crystallization step may be oxidized and removed, or a sulfuric acid peroxide solution (H ₂ SO ₄ : H ₂ O ₂ =
1: 1). Thereafter, by performing a heat treatment at 700 ° C. or more, germanium in the formed polysilicon film is removed or reduced.

The configuration of this embodiment can be combined with any of the first to eighth embodiments, and can be applied to any of the embodiments.

(Embodiment 10) In this embodiment, a case where a spin coating method by a solution coating and a thermal diffusion method are used as means for adding germanium to an amorphous silicon film will be described.

In this embodiment, after forming the amorphous silicon film, a solution containing germanium is applied thereon. Such solutions include germanium oxide (GeOx,
Typically, GeO ₂ ), germanium chloride (GeCl ₄ ), germanium bromide (GeBr ₄ ), germanium sulfide (GeS ₂ )
There is an aqueous solution of a germanium salt such as germanium acetate (Ge (CH ₃ CO ₂ )).

Further, an alcohol solvent such as ethanol or isopropyl alcohol may be used as the solvent.

In the present embodiment, a germanium oxide layer is formed by preparing a 10 to 100 ppm aqueous solution of germanium oxide, applying the solution on an amorphous silicon film (an insulating film may be interposed), and spin-coating.

Since the amorphous silicon film exhibits hydrophobicity, it is effective to form an insulating film on the surface of the silicon film before spin coating to enhance wettability. In this case, if the insulating film is too thick, thermal diffusion of germanium into the silicon film will be hindered.
Preferably, it is set to 30 nm.

When the crystallization step is performed in the state where the germanium-containing layer is provided, germanium is thermally diffused into the amorphous silicon film by heating, and functions as a catalyst element for promoting crystallization.

The configuration of this embodiment can be combined with any of the first to eighth embodiments, and can be applied to any of the embodiments.

[0139]

According to the present invention, a semiconductor film having crystallinity that can be regarded as substantially a single crystal can be obtained. And a TFT using such a semiconductor film as an active layer.
And a high-performance semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a thin film transistor.

FIG. 2 illustrates a manufacturing process of a thin film transistor.

FIG. 3 illustrates a manufacturing process of a thin film transistor.

FIG. 4 is a diagram illustrating a configuration of a semiconductor device (electro-optical device).

FIG. 5 illustrates a structure of a semiconductor device (semiconductor circuit).

FIG. 6 illustrates a structure of a semiconductor device (electronic device).

Claims (7)

[Claims] A first step of adding germanium to a semiconductor film containing an amorphous; and a step of changing the semiconductor film containing an amorphous to a semiconductor film containing a crystal after the first step. Two steps; a third step of oxidizing the semiconductor film containing the crystal to reduce the film thickness;
A semiconductor comprising: a fourth step of performing laser annealing at an energy density of 5000 mJ / cm ² ; and a fifth step of performing furnace annealing on a semiconductor film containing crystals after the fourth step. Method for manufacturing the device. 2. A first step of adding germanium to a semiconductor film containing an amorphous, and after the first step, a step of changing the semiconductor film containing an amorphous to a semiconductor film containing a crystal. Two steps; a third step of oxidizing the semiconductor film containing the crystal to reduce the film thickness;
A fourth step of performing laser annealing at an energy density of 5000 mJ / cm ² , and a fifth step of performing a furnace annealing at 900 to 1200 ° C. in a reducing atmosphere on the semiconductor film containing crystals after the fourth step. A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 1, wherein
A method for manufacturing a semiconductor device, wherein the step is a step of crystallizing the semiconductor film containing amorphous by a thermal annealing treatment. 4. The semiconductor device according to claim 1, wherein the germanium is added to the amorphous-containing semiconductor film by an ion implantation method, a plasma doping method, or a laser doping method. Method of manufacturing. 5. The method according to claim 1, wherein the third
A method for manufacturing a semiconductor device, wherein the step is performed by a plurality of thermal oxidation steps. 6. The method according to claim 1, wherein the energy density (E) is a light intensity (E ₀ ) of a laser beam oscillated from a laser oscillator, a transmittance of an attenuator (a), and a transmittance of an optical system. (B) A method for manufacturing a semiconductor device, wherein E = (E ₀ × a × b) / A using a laser irradiation area (A). 7. The method for manufacturing a semiconductor device according to claim 2, wherein the reducing atmosphere is a hydrogen atmosphere, an ammonia atmosphere, a mixed atmosphere of hydrogen and nitrogen, or a mixed atmosphere of hydrogen and argon.