JP2000040812A - Forming method of soi substrate and porming method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means for forming a very thin single crystalline semiconductor thin film. SOLUTION: A single crystalline silicon substrate 101 is anodized, and a porous silicon layer 102 is formed. After that, thermal treatment process at 900-1200 deg.C is performed in an reducing atmosphere. By this thermal treatment process, surface holes of the porous silicon layer 102 are covered, and a thin single crystalline silicon layer 103 is formed in the vicinity of the surface. The single crystalline silicon layer 103 is used as an active layer of an TFT(thin film transistor).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI (Silicon on Silicon) having a single crystal semiconductor thin film on a substrate having an insulating surface.
Insulator) relates to a method for manufacturing a substrate. Further, the present invention relates to a method for manufacturing a semiconductor device including a thin film transistor (hereinafter, referred to as a TFT) formed using such an SOI substrate.

[0002] In this specification, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics. Therefore, an electro-optical device typified by a liquid crystal display device or a photoelectric conversion device, a semiconductor circuit in which TFTs are integrated, and an electronic device including such an electro-optical device or a semiconductor circuit as a component are also semiconductor devices.

[0003]

2. Description of the Related Art In recent years, as VLSI technology has made remarkable progress, SOI (Silicon on Ins.
ulator) structure is drawing attention. This technique is a technique in which an active region (channel formation region) of an FET conventionally formed of bulk single crystal silicon is made into thin film single crystal silicon.

In an SOI substrate, a buried oxide film made of silicon oxide exists on single crystal silicon, and a single crystal silicon thin film is formed thereon. Although various methods are known for manufacturing such an SOI substrate, recently, a bonded SOI substrate has been receiving attention. A bonded SOI substrate realizes an SOI structure by bonding two silicon substrates as the name implies. Using this technique, a single-crystal silicon thin film can be formed on a ceramic substrate or the like.

[0005] Among the bonded SOI substrates, a technique called ELTRAN (registered trademark of Canon Inc.) has recently attracted particular attention. This technique is a method for manufacturing an SOI substrate using selective etching of a porous silicon layer. Regarding the detailed technology of the ELTRAN method, see `` T. Yonehara, K. Sakaguchi and T. Hamaguchi: Appl.
Phys. Lett. 43 [3], 253 (1983) ".

[0006]

In the conventional ELTRAN method, a single crystal silicon layer epitaxially grown on a porous silicon layer is used for a semiconductor device. However, when the thickness of the epitaxial silicon layer is reduced to less than 50 nm, it is difficult to secure a uniform film thickness and film quality.

An object of the present invention is to provide means for solving the above-mentioned problems, and to provide means for forming an extremely thin single crystal semiconductor thin film of 5 to 30 nm. Another object is to provide a method for manufacturing a semiconductor device using an SOI substrate having such an extremely thin single crystal semiconductor thin film.

[0008]

Means for Solving the Problems The constitution of the invention disclosed in the present specification comprises a step of forming a porous semiconductor layer on a first single crystal semiconductor substrate and a step of performing a first heat treatment in a reducing atmosphere. Forming a single crystal semiconductor layer by closing the vicinity of the surface of the porous semiconductor layer, forming a first silicon oxide layer on the main surface of the single crystal semiconductor layer, and forming a second silicon oxide layer on the main surface of the second substrate. Forming a silicon oxide layer, bonding the first silicon oxide layer and the second silicon oxide layer to bond the first single crystal semiconductor substrate to the second substrate, Grinding the crystalline semiconductor substrate from the back side to expose the porous semiconductor layer,
Removing the exposed porous semiconductor layer and exposing the single crystal semiconductor layer.

The present invention is a technique for improving the conventional ELTRAN method, and is 5 to 30 nm (typically 5 to 10 nm).
nm) to form an extremely thin single crystal semiconductor thin film. Note that the single crystal semiconductor thin film is not limited to a single crystal silicon thin film, but also includes a single crystal silicon germanium thin film.

In the conventional ELTRAN method, after a porous silicon layer is formed, heat treatment is performed in a hydrogen atmosphere to flatten the surface of the porous silicon layer. At that time, the natural oxide film is reduced and removed on the surface of the porous silicon layer, and accelerated surface diffusion of silicon atoms occurs with the driving capability of minimizing the surface energy. As a result, surface pores (fine pores observed on the surface) near the surface of the porous silicon layer
Disappears.

This means a state in which individual surface pores are closed by silicon atoms near the surface of the porous silicon layer, and the surface pores are no longer observed. Therefore, the porous silicon layer remains as it is in a portion deeper than the vicinity of the surface.

Conventionally, a single-crystal semiconductor layer is epitaxially grown thereafter to obtain a single-crystal semiconductor thin film. In the present invention, however, an extremely thin single-crystal semiconductor thin film formed by closing the surface pores of the porous semiconductor layer To
It is characterized in that it is used as it is as an active layer of a thin film transistor. That is, it is significantly different from the conventional ELTRAN method in that there is no step of epitaxially growing a semiconductor thin film.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described.
A detailed description will be given using the embodiments described below.

[0014]

(Embodiment 1) FIG.
This will be described with reference to FIG. First, a single crystal silicon substrate 101 is prepared as a first substrate. Here, a P-type substrate is used, but an N-type substrate may be used. Of course, a single crystal silicon germanium substrate can also be used.

Next, a porous silicon layer 102 is formed by anodizing the main surface. The anodic oxidation step may be performed in a mixed solution of hydrofluoric acid and ethanol. The porous silicon layer 102 has a columnar surface pore having a surface density of 10%.
^It is considered a single crystal silicon layer provided about ¹¹ pieces / cm ³ ,
The crystal state (orientation etc.) of the single crystal silicon substrate 101 is inherited as it is. Since the ELTRAN method itself is publicly known, a detailed description is omitted here.

After the formation of the porous silicon layer 102, a heat treatment is performed in a reducing atmosphere at a temperature in the range of 900 to 1200 ° C. (preferably 1000 to 1150 ° C.). Here, heat treatment is performed at 1050 ° C. for 2 hours in a hydrogen atmosphere. (Fig. 1 (A))

The reducing atmosphere is preferably a hydrogen atmosphere, an ammonia atmosphere, or an inert atmosphere containing hydrogen or ammonia (such as a mixed atmosphere of hydrogen and nitrogen or a mixture of hydrogen and argon). Even in an inert atmosphere, the surface of the crystalline silicon film is flat. Is possible. However, it is preferable to reduce the natural oxide film by utilizing the reducing action, since many silicon atoms having high energy are generated, and as a result, the flattening effect is enhanced.

However, it is particularly necessary to keep the concentration of oxygen or oxygen compounds (for example, OH groups) contained in the atmosphere at 10 ppm or less (preferably 1 ppm or less). Otherwise, the reduction reaction by hydrogen will not occur.

At this time, the vicinity of the surface of the porous silicon layer 102 (5 to 30 nm deep from the main surface, typically 5 to 10 nm)
To the extent) surface pores are closed by the movement of silicon atoms, resulting in an extremely thin single crystal silicon layer 1.
03 is formed.

After the single crystal silicon layer 103 is formed, the vicinity of the surface is oxidized to form an extremely thin silicon oxide layer (first silicon oxide layer) 104. Silicon oxide layer 104
Must be formed with care so that the single crystal silicon layer 103 is not lost. As a formation method, thermal oxidation, plasma oxidation, laser oxidation, or the like can be used. However, microwave oxidation plasma oxidation is preferable for forming an extremely thin silicon oxide layer. Note that a thickness of the silicon oxide layer 104 of 5 to 15 nm is sufficient. (FIG. 1 (B))

Next, a ceramic substrate 1 is used as a second substrate.
06 is prepared. Instead of ceramic substrates, quartz substrates, glass ceramic substrates, and semiconductor substrates (including single crystals and polycrystals)

A second silicon oxide layer 1 is formed on the main surface.
07 is formed. As a method for forming the second silicon oxide layer 107, a gas phase method such as a low pressure thermal CVD method, a sputtering method, or a plasma CVD method may be used, or a thermal oxidation method if the second substrate is a semiconductor substrate (for example, a silicon substrate). Alternatively, a plasma oxidation method may be used.

When the preparation of the first substrate and the second substrate is completed in this way, the two substrates are bonded together such that their main surfaces face each other. In this case, the first silicon oxide layer 104 and the second silicon oxide layer 107 are bonded. (Figure 1
(C))

When the bonding is completed,
A heat treatment process is performed at a temperature of 1150 ° C. to stabilize a bonding interface made of silicon oxides. In this embodiment, this heat treatment step is performed at 1100 ° C. for 2 hours. In addition, what is shown by the dotted line is a completely bonded bonding interface. The buried insulating layer 108 including the first silicon oxide layer and the second silicon oxide layer finally functions as a buried insulating layer of the SOI substrate. (Figure 1
(D))

Next, the single crystal silicon substrate 101 is ground from the back side by mechanical polishing such as CMP, and the grinding step is completed when the porous silicon layer 102 is exposed.
Thus, the state shown in FIG.

Next, the porous silicon layer 102 is selectively removed by wet etching. The etchant used is preferably a mixed solution of a hydrofluoric acid aqueous solution and a hydrogen peroxide aqueous solution. A solution in which 49% HF and 30% H ₂ O ₂ are mixed at a ratio of 1: 5 forms a solution between the single crystal silicon layer and the porous silicon layer.
It has been reported to have a selectivity of more than 10,000 times.

Thus, the state shown in FIG. 2B is obtained. In this state, a buried insulating layer 108 is provided over a ceramic substrate 106, and a single crystal silicon layer 109 is formed thereon.

Although the SOI substrate has been completed at this point, since the surface of the single-crystal silicon layer 109 has minute irregularities, it is desirable to perform a heat treatment in a hydrogen atmosphere to planarize the SOI substrate. This flattening phenomenon is due to the accelerated surface diffusion of silicon atoms by reducing the natural oxide film as described above.

At this time, there is also an effect that boron (contained in the P-type silicon substrate) contained in the single crystal silicon layer 109 is released into the gas phase by hydrogen atoms, so that it is also effective in reducing impurities. It is.

Thus, the film thickness is 5 to 30 nm (typically 5 to 30 nm).
(10 to 10 nm). When a TFT is formed, the off-current value (corresponding to a leak current when the TFT is in an off-state) can be reduced by reducing the thickness of the active layer. The effect can be demonstrated.

Embodiment 2 In this embodiment, a case where a TFT is manufactured using an island-shaped semiconductor layer formed using the structure of Embodiment 1 will be described with reference to FIGS.

First, through the steps shown in the first embodiment, the SOI
Form a substrate. Reference numeral 301 denotes a substrate having an insulating surface, which actually has a configuration in which a buried insulating layer is provided on a silicon substrate or a ceramic substrate. When an SOI substrate is obtained, the island-shaped silicon layer 302 is formed by patterning the single crystal silicon layer.

Next, a 10-nm-thick silicon oxide film 303 is formed on the surface of the island-shaped silicon layer 302 by performing a thermal oxidation process. This silicon oxide film 303 functions as a gate insulating film. After the gate insulating film 303 is formed, a conductive polysilicon film is formed thereon, and the gate wiring 304 is formed by patterning. (FIG. 3 (A))

In this embodiment, a polysilicon film having N-type conductivity is used as the gate wiring, but the material is not limited to this. In particular, it is effective to use tantalum, a tantalum alloy, or a stacked film of tantalum and tantalum nitride to reduce the resistance of the gate wiring. If a low-resistance gate wiring is aimed at, it is effective to use copper or a copper alloy.

When the state shown in FIG. 3A is obtained, an impurity imparting N-type conductivity or P-type conductivity is added to form an impurity region 306. LDD at the impurity concentration at this time
The impurity concentration of the region is determined. In this embodiment, 1 × 10 ¹⁸
Although arsenic is added at a concentration of atoms / cm ³ , neither the impurity nor the concentration need be limited to this embodiment.

Next, a thin silicon oxide film 307 of about 5 to 10 nm is formed on the surface of the gate wiring. This may be formed using a thermal oxidation method or a plasma oxidation method. The purpose of forming the silicon oxide film 307 is to function as an etching stopper in the next sidewall formation step.

After the formation of the silicon oxide film 307 serving as an etching stopper, a silicon nitride film is formed and etched back to form a sidewall 308. Thus, the state shown in FIG. 3B is obtained.

Although the silicon nitride film is used as the sidewall in this embodiment, a polysilicon film or an amorphous silicon film may be used. Of course, if the material of the gate wiring changes, it goes without saying that the selection range of the material that can be used as the sidewall is expanded accordingly.

Next, impurities of the same conductivity type as above are added again. The concentration of the impurity added at this time is higher than that in the previous step. In the present embodiment, arsenic is used as an impurity and the concentration is 1 × 10 ²¹ atoms / cm ³ , but it is not necessary to limit to this. The source region 309, the drain region 310, the LDD region 311 and the channel formation region 312 are defined by the impurity doping process. (FIG. 3 (C))

After the respective impurity regions are formed, the impurities are activated by means such as furnace annealing, laser annealing or lamp annealing.

Next, the gate wiring 304 and the source region 30
9 and the silicon oxide film formed on the surface of the drain region 310 are removed to expose those surfaces. And
A cobalt film 313 of about 5 nm is formed and a heat treatment step is performed. This heat treatment causes a reaction between cobalt and silicon, whereby a silicide layer (cobalt silicide layer) 314 is formed. (FIG. 3 (D))

This technique is a known salicide technique.
Therefore, titanium or tungsten may be used instead of cobalt, and the heat treatment conditions and the like may be referred to a known technique. In this embodiment, the heat treatment step is performed using lamp annealing.

After the formation of the silicide layer 314, the cobalt film 313 is removed. Thereafter, an interlayer insulating film 315 having a thickness of 1 μm is formed. As the interlayer insulating film 315, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a resin film may be used. Further, these insulating films may be stacked.

Next, a contact hole is formed in the interlayer insulating film 315 to form a source wiring 316 and a drain wiring 317 made of a material containing aluminum as a main component. Finally, the entire device is subjected to furnace annealing at 300 ° C. for 2 hours in a hydrogen atmosphere to complete hydrogenation.

Thus, a TFT as shown in FIG. 3E is obtained. The structure described in this embodiment is an example, and the TFT structure to which the present invention can be applied is not limited to this. Therefore, the present invention can be applied to any known TFT.

Of course, the present invention can be easily applied not only to the top gate structure but also to a bottom gate structure typified by an inverted staggered TFT.

In this embodiment, an N-channel TFT has been described as an example. However, it is easy to manufacture a P-channel TFT. Further, an N-channel type T on the same substrate
An FT and a P-channel TFT can be formed and complementarily combined to form a CMOS circuit.

Further, a pixel electrode (not shown) electrically connected to the drain wiring 317 in the structure of FIG.
Is formed by known means, it is easy to form a pixel switching element of an active matrix display device.

That is, the present invention is a very effective technique as a method for manufacturing an electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device.

Embodiment 3 In this embodiment, an example in which a single-crystal silicon thin film is formed by a method different from that in Embodiment 1 will be described. FIG. 7 is used for the description.

In this embodiment, a porous silicon layer 702 is formed on an N-type or P-type single-crystal silicon substrate 701 by the same anodic oxidation method as in the first embodiment. Then, an amorphous silicon layer 703 is formed on the porous silicon layer 702. As a method for forming the amorphous silicon layer 703, any of a low-pressure thermal CVD method, a plasma CVD method, and a sputtering method may be used.

The thickness of the amorphous silicon layer 703 may be 15 to 100 nm (typically 25 to 70 nm).

When an amorphous silicon layer is formed on the porous silicon layer as in this embodiment, amorphous silicon fills the inside of the surface holes of the porous silicon layer (however, to a depth of about 10 to 50 nm from the main surface). You. The situation is as shown in the enlarged view surrounded by the dotted line in FIG.

Next, after providing the amorphous silicon layer 703, a heat treatment step in a reducing atmosphere (1100 ° C. for 1 hour in a hydrogen atmosphere in this embodiment) is performed. In this step, the amorphous silicon layer 703 is crystallized. At this time, the crystallization proceeds in accordance with the crystal state of the porous silicon layer 702, so that a single crystal silicon layer 704 can be obtained as a result. Of course, the heat treatment step may be performed under the other conditions described in the first embodiment.

After the single-crystal silicon layer 704 is formed in this manner, an SOI substrate having a single-crystal silicon layer may be manufactured according to the steps of the first embodiment, and a TFT may be formed according to the steps of the second embodiment. Then, a circuit may be assembled on the substrate using the TFT, and various semiconductor devices may be manufactured.

(Embodiment 4) In this embodiment, an example in which a single crystal silicon layer is selectively formed on a porous silicon layer will be described. FIG. 8 is used for the description.

First, a porous silicon layer 802 is formed on a single crystal silicon substrate 801 according to the first embodiment. Then, the porous silicon layer 802 is exposed to plasma formed in an oxygen atmosphere, and a 50 nm thick silicon oxide layer 80 is formed on the surface.
Form 3 This step is called a plasma oxidation step.
(FIG. 8A)

The thickness of the silicon oxide layer 803 is 50 to 10
It is only necessary to have 0 nm. Although the plasma oxidation method is used in this embodiment, a thermal oxidation method may be used, or a CVD method or a sputtering method may be used.

Further, in this embodiment, a silicon oxide layer is described as an example, but a silicon nitride layer or a silicon oxynitride layer (indicated by SiOxNy) may be formed by a CVD method or a sputtering method.

Next, a mask 804 is formed by patterning the silicon oxide layer 803. Note that the silicon oxide layer 803 is preferably etched by wet etching using a hydrofluoric acid aqueous solution. With a hydrofluoric acid aqueous solution, the silicon oxide layer 803 can be etched without substantially etching the porous silicon layer 802.

The opening 805 is simultaneously formed with the mask 804.
Is formed. This opening 805 is provided at a position where a single crystal silicon layer is to be formed later. (FIG. 8 (B))

When the state shown in FIG. 8B is obtained,
1150 in an atmosphere containing 3% hydrogen added to a nitrogen atmosphere.
A heat treatment step at 1 ° C. for one hour is performed to form a single-crystal silicon layer 806 near the main surface of the porous silicon layer 802 exposed in the opening 805 (region where the mask 804 is not formed). Detailed heat treatment conditions may be in accordance with the first embodiment.
(FIG. 8 (C))

The single-crystal silicon layer 80 thus formed
Since 6 is selectively formed, there is no need to pattern it later as an active layer.

Next, after removing the mask 804, a silicon oxide film 807 necessary for the bonding step is formed. In this step, an extremely thin silicon oxide layer having a thickness of about 5 to 10 nm may be formed. Therefore, a means capable of forming a silicon oxide film as thin as possible with good controllability is desirable. In that sense, the plasma oxidation method is the most preferable. Of course, a thermal oxidation method may be used, or a film may be formed using a CVD method or a sputtering method. (FIG. 8 (D))

When the state shown in FIG. 8D is obtained,
After that, an SOI substrate having a single crystal silicon layer is manufactured by bonding to a second substrate having an insulating surface according to the steps of Embodiment 1, and a TFT may be formed according to the steps of Embodiment 2. Then, a circuit is assembled on the substrate with the TFT,
Various semiconductor devices may be manufactured.

(Embodiment 5) In this embodiment, the S
FIG. 4 shows an example of a reflective liquid crystal display device manufactured using an OI substrate. A well-known means may be used for a method of manufacturing a pixel TFT (pixel switching element) and a cell assembling step, and a detailed description thereof will be omitted.

In FIG. 4A, 11 is a substrate having an insulating surface, 12 is a pixel matrix circuit, 13 is a source driver circuit, 14 is a gate driver circuit, 15 is a counter substrate, 16 is an FPC (flexible printed circuit), 17 Is a signal processing circuit. As the signal processing circuit 17, it is possible to form a circuit such as a D / A converter, a gamma correction circuit, a signal dividing circuit, etc., which performs processing which has been substituted by a conventional IC. Of course, it is also possible to provide an IC chip on a glass substrate and perform signal processing on the IC chip.

Further, in this embodiment, a liquid crystal display device is described as an example, but the present invention is applied to an EL (electroluminescence) display device or an EC (electrochromics) display device as long as it is an active matrix type display device. It goes without saying that the invention can be applied.

Here, the driver circuit 13 shown in FIG.
FIG. 4B shows an example of a circuit constituting the circuit 14. In addition,
Since the TFT portion has already been described in the second embodiment, only necessary portions will be described here.

In FIG. 4B, 401 and 402 indicate N
A channel TFT 403 is a P-channel TFT, and a TFT 401 and a TFT 403 constitute a CMOS circuit. Reference numeral 404 denotes an insulating layer composed of a stacked film of a silicon nitride film / silicon oxide film / resin film, and a titanium wiring 405 on the insulating layer.
Are provided, and the above-described CMOS circuit and the TFT 402 are electrically connected. The titanium wiring is further covered with an insulating layer 406 made of a resin film. Two insulating layers 404,
Reference numeral 406 also has a function as a flattening film.

The pixel matrix circuit 1 shown in FIG.
FIG. 4C shows a part of the circuit constituting the second circuit. FIG.
In FIG. 4C, reference numeral 407 denotes a pixel TFT formed of an N-channel TFT having a double gate structure, and a drain wiring 408 is formed so as to largely spread in a pixel region.

An insulating layer 404 is provided thereon, and a titanium wiring 405 is provided thereon. At this time, a recess is formed in a part of the insulating layer 404, and only the lowermost silicon nitride and silicon oxide are left.
Thus, an auxiliary capacitance is formed between the drain wiring 408 and the titanium wiring 405.

Further, the titanium wiring 405 provided in the pixel matrix circuit provides an electric field shielding effect between the source / drain wiring and the subsequent pixel electrode. Further, in a gap between a plurality of provided pixel electrodes, it also functions as a black mask.

Then, an insulating layer 406 is provided to cover the titanium wiring 405, and a pixel electrode 409 made of a reflective conductive film is formed thereon. Of course, the surface of the pixel electrode 409 may be devised to increase the reflectance.

Although an alignment film and a liquid crystal layer are actually provided on the pixel electrode 409, the description is omitted here.

The reflection type liquid crystal display device having the above configuration can be manufactured by using the present invention. Of course, a transmission type liquid crystal display device can be easily manufactured by combining with a known technique. Further, an active matrix EL display device can be easily manufactured by combining with a known technique.

Embodiment 6 The present invention can be applied to all conventional IC technologies. That is, the present invention can be applied to all semiconductor circuits currently on the market. For example, RISC processor integrated on one chip, ASIC
The present invention may be applied to a microprocessor such as a processor, or may be applied to a signal processing circuit such as a D / A converter to a high-frequency circuit for a portable device (a mobile phone, a PHS, a mobile computer).

FIG. 5 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.

Of course, the microprocessor shown in FIG. 5 is a simplified example, and an actual microprocessor may be designed in various circuits depending on the application.

However, a microprocessor having any function functions as a center only when an IC (Integer) is used.
grated circuit) 28. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected by ceramic or the like.

The integrated circuit formed on the semiconductor chip 29 is composed of the N-channel TFT 30 and the P-channel TFT 31 having the structure of the present invention. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.

The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Representative electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (an automobile, a train, or the like) is also included.

(Embodiment 7) The electro-optical device of the present invention is
It is used as a display for various electronic devices. Such electronic devices include video cameras, still cameras,
Projectors, projection TVs, head-mounted displays, car navigation, personal computers, personal digital assistants (mobile computers, mobile phones, etc.)

FIG. 6A shows a portable telephone, and the main body 200 is shown.
1, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 2006
It consists of. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.

FIG. 6B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6. The present invention is applied to a display device 2102, a voice input unit 2103, and other signal control units.

FIG. 6C shows a mobile computer (mobile computer), which includes a main body 2201 and a camera section 2.
202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 and other signal control circuits.

FIG. 6D shows a head mounted display, which includes a main body 2301, a display device 2302, and a band 2
303. The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 6E shows a rear type projector, which includes a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The present invention can be applied to the display device 2403 and other signal control circuits.

FIG. 6F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The present invention can be applied to the display device 2503 and other signal control circuits.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields.

[0091]

By implementing the present invention, the conventional EL
It is possible to realize an SOI substrate having an extremely thin single crystal silicon thin film of 5 to 30 nm (typically 5 to 10 nm) which cannot be achieved by the TRAN method.

Then, it is possible to manufacture a high performance thin film transistor having a small off-state current value by using the SOI substrate, and it is possible to improve the performance of all semiconductor devices in which a circuit is formed by a plurality of TFTs. .

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of an SOI substrate.

FIG. 2 illustrates a manufacturing process of an SOI substrate.

FIG. 3 illustrates a manufacturing process of a TFT.

FIG. 4 is a diagram illustrating a configuration of a semiconductor device (electro-optical device).

FIG. 5 illustrates a structure of a semiconductor device (semiconductor circuit).

FIG. 6 illustrates a structure of a semiconductor device (electronic device).

FIG. 7 illustrates a manufacturing process of an SOI substrate.

FIG. 8 illustrates a manufacturing process of an SOI substrate.

Claims (6)

[Claims] A step of forming a porous semiconductor layer on a first single-crystal semiconductor substrate; and a step of performing a first heat treatment in a reducing atmosphere to close a surface of the porous semiconductor layer and thereby form the single-crystal semiconductor layer. Forming a first silicon oxide layer on a main surface of the single crystal semiconductor layer; forming a second silicon oxide layer on a main surface of a second substrate; Bonding the first single-crystal semiconductor substrate to the second substrate by bonding the first single-crystal semiconductor substrate to the second silicon oxide layer, and grinding the first single-crystal semiconductor substrate from the back side to form the porous semiconductor layer. And a step of removing the exposed porous semiconductor layer and exposing the single crystal semiconductor layer. 2. The method for manufacturing an SOI substrate according to claim 1, wherein the first heat treatment is performed in an atmosphere containing hydrogen at a temperature of 900 to 1200 ° C. 3. The method for manufacturing an SOI substrate according to claim 1, wherein the step of forming the first silicon oxide layer is performed by a plasma oxidation method. 4. A step of forming a porous semiconductor layer on a first single-crystal semiconductor substrate, and performing a first heat treatment in a reducing atmosphere to close a surface of the porous semiconductor layer and thereby form the single-crystal semiconductor layer. Forming a first silicon oxide layer on a main surface of the single crystal semiconductor layer; forming a second silicon oxide layer on a main surface of a second substrate; Bonding the first single-crystal semiconductor substrate to the second substrate by bonding the first single-crystal semiconductor substrate to the second silicon oxide layer, and grinding the first single-crystal semiconductor substrate from the back side to form the porous semiconductor layer. Exposing, removing the exposed porous semiconductor layer, exposing the single crystal semiconductor layer, and forming a plurality of thin film transistors using the single crystal semiconductor layer as an active layer,
A method for manufacturing a semiconductor device, comprising: 5. The method for manufacturing a semiconductor device according to claim 4, wherein the first heat treatment is performed in an atmosphere containing hydrogen at a temperature in a range of 900 to 1200 ° C. 6. The method for manufacturing a semiconductor device according to claim 4, wherein the step of forming the first silicon oxide layer is performed by a plasma oxidation method.