JP2000164709A - Chip size package and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To improve the reliability of a chip size package. SOLUTION: An Si3N4 film SN is formed at an interface between a wiring layer 16 made of Cu and a polyimide resin 17 to prevent a reaction between the imide resin and Cu before thermosetting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a chip size package and a method for manufacturing the same. The chip size package (Chip Size Package) is also referred to as a CSP, and is a general term for packages having a size equal to or slightly larger than the chip size, and is a package for high-density mounting. The present invention relates to a barrier metal for a plating electrode used in a CSP.

[0002]

2. Description of the Related Art Conventionally, in this field, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, a fine pitch BGA, a structure in which the ball pitch of the BGA is further narrowed and the outer shape is close to the chip size, etc. Are known.

Recently, there is a wafer CSP described in “Nikkei Microdevice”, August 1998, pp. 44-71. This wafer CSP is basically a CSP in which wiring or array-like pads are formed by a wafer process (pre-process) before dicing a chip.
It is expected that this technology will integrate the wafer process and the package process (post-process), thereby greatly reducing the package cost.

There are two types of wafer CSP: a sealing resin type and a rewiring type. The sealing resin mold has a structure in which the surface is covered with a sealing resin, similarly to a conventional package, and has a structure in which metal posts are formed on a wiring layer on the chip surface and the periphery thereof is solidified with the sealing resin.

It is generally said that when a package is mounted on a printed circuit board, stress generated due to a difference in thermal expansion between the printed circuit board and the printed circuit board is concentrated on the metal posts. It is believed to be decentralized.

On the other hand, the rewiring type has a structure in which a rewiring is formed without using a sealing resin as shown in FIG. That is, an Al electrode 52, a wiring layer 53, and an insulating layer 54 are stacked on the surface of the chip 51, a metal post 55 is formed on the wiring layer 53, and a solder bump 56 is formed thereon.
The wiring layer 53 is used as rewiring for arranging the solder bumps 56 on the chip in a predetermined array.

[0007] The sealing resin mold has a metal post of 100 μm.
By lengthening it and reinforcing it with sealing resin,
High reliability is obtained. However, the process of forming the sealing resin needs to be performed using a mold in a later step, and the process becomes complicated.

On the other hand, the rewiring type has an advantage that the process is relatively simple and most of the steps can be performed by a wafer process. However, there is a need to relieve stress in some way to increase reliability.

[0009]

However, in FIG. 7, the wiring layer 53 is formed by Cu plating, and the insulating layer 54 is
Apply a liquid polyimide resin before curing, and apply
It is imidized at about 00 to 400 ° C. and thermally cured.

However, at the time of this imidization, there is a problem that Cu reacts with the resin before imidization and the film quality of the polyimide resin is deteriorated.

Accordingly, there has been a problem that the adhesiveness and moisture resistance between the polyimide resin and the wiring layer are deteriorated.

[0012]

SUMMARY OF THE INVENTION A chip size package and a method of manufacturing the same according to the present invention have been made in view of the above problems, and
This problem can be solved by providing a Si3N4 film at the interface between the wiring mainly composed of Cu and the polyimide resin covering the wiring.

The Si3N4 film is superior as a barrier material to the SiO2 film, and the plasma CVD method has excellent step coverage. Therefore, the wiring made of Cu is
If covered with the N4 film, the imide resin will not react with Cu due to the high-temperature reaction during imidization.

[0014]

Next, an embodiment of the present invention will be described.

FIG. 6 shows a two-layer metal transistor, in which 10 and 11 are source and drain regions, and 12 is a gate. 13 is a source electrode and its wiring, 14
Is a drain electrode and its wiring. The Al electrode 1 is in contact with the drain electrode 14 as a second layer metal.

Here, in a normal wire bonding type IC chip, the metal of the uppermost layer (the portion which also functions as a bonding pad) is shown in FIG.
The interlayer insulating film in which the contact hole C of the electrode 1 is formed is shown in FIG. Furthermore, the passivation film is
Indicated by Here, the passivation film 3 is a Si nitride film,
It is made of epoxy resin or PIX.

Here, a Ti nitride film 5 is formed on the Al electrode 1.

Subsequently, the passivation film 3 is formed with an opening 5 exposing the TiN film 5.
A Cu thin film layer 6 is formed as a plating electrode for the wiring layer. Then, a wiring layer 16 is formed thereon by Cu plating.

Subsequently, the entire surface including the wiring layer 16 is covered with the Si3N4 film SN which is the point of the present invention, and the resin layer 17 made of a polyimide resin is formed.

The polyimide resin 17 is prepared from a liquid imide resin, is spun on over the entire surface of the wafer, and has a thickness of 20 to
It is formed with a thickness of about 60 μm. Thereafter, the imide resin is polymerized by a thermosetting reaction. Temperature is 300-4
It is about 00 ° C. However, imide resin before thermosetting,
Although it is very active and reacts with Cu, the reaction with Cu can be prevented since the surface of the wiring layer is covered with the Si3N4 film SN. Here, the thickness of the Si3N4 film is about 1000 to 3000 degrees. Also, the film SN is
An insulating film having an excellent barrier property may be used, but an SiO2 film is inferior in the barrier property.
It is necessary to make the film thickness thicker than the N4 film. Also Si3
Since the N4 film can be formed by the plasma CVD method, its step coverage is excellent and is preferable.

Subsequently, an opening 18 is formed at an end of the wiring layer 16, and a thin film layer 19 of Cu is formed in the opening 18 as a plating electrode of the metal post 7.
A metal post 7 made of u is formed. On the metal post 7, a Ni thin film layer 20, a Cu thin film layer (or an Au layer in consideration of oxidation) 21 from below.
Are formed. These metals 19,7,20,2
1 is patterned so as to extend into and around the opening.

The solder balls 8 are formed on the Cu thin film layer 21 (or Au thin film layer). Here, the solder balls 8 are formed by electrolytic plating using the underlying Cu thin film layer 21 as an electrode.

Here, it is not necessary to form an Si3N4 film at the interface between the Cu thin film layer 19 and the polyimide resin 17. That is, when the Cu thin film layer 19 is formed, the thermosetting reaction of the polyimide resin has been completed, and there is almost no reaction with Cu.

Next, a method of manufacturing the structure of FIG. 6 will be described more simply than FIG.

First, a semiconductor substrate (wafer) on which an LSI having an Al electrode 1 is formed is prepared. Here, as described above, the source electrode 13 and the drain electrode 14 of the transistor are formed as the first layer metal, and the Al electrode 1 in contact with the drain electrode 14 is formed as the second layer metal. ing.

Here, after the opening C of the interlayer insulating film 2 from which the drain electrode 14 is exposed is formed, an electrode material mainly composed of Al and a Ti nitride film 5 are formed on the entire surface of the wafer, and the photoresist PR1 is used as a mask. The Al electrode 1 and the Ti nitride film 5 are dry-etched into a predetermined shape.

Here, a passivation film 3 is formed,
Unlike the case where a barrier metal is formed in the opening 18 which is opened thereafter, it can be formed at once with the photoresist PR1 including the Ti nitride film as the barrier metal, and the number of steps can be simplified.

The Ti nitride film 5 functions as a barrier metal for a Cu thin film layer 6 to be formed later. Moreover, attention is paid to the fact that the TiN film is effective as an antireflection film. That is, it is also effective for preventing halation of the resist used in patterning. To prevent halation, a minimum of about 1200 ° to 1300 ° is required, and in order to provide a barrier metal function, it is preferably about 2000 ° to 3000 °. If the film is formed to be thicker than this, a stress occurs due to the Ti nitride film. Subsequently, the surface of the semiconductor substrate is covered with a passivation film 3 such as a SiN film or PIX.

The Al electrode 1 also serves as a pad for external connection of the LSI, and functions as a wire bonding pad when not formed as a chip size package composed of solder balls.

In order that a part of the Al electrode 1 is exposed,
A portion of the passivation film 3 is removed by etching, and a Cu thin film layer 6 is formed on the entire surface. This Cu thin film layer 6 will later become a plating electrode for the wiring layer 16.

Subsequently, for example, a photoresist layer PR is formed on the entire surface.
2 and a photoresist PR2 corresponding to the wiring layer 16
Is removed, and the wiring layer 16 is formed using the Cu thin film layer 6 exposed in the opening as a plating electrode. This wiring layer 16
Needs to be formed as thick as about 5 μm in order to secure mechanical strength. Here, it is formed using a plating method, but may be formed by vapor deposition, sputtering, or the like. Thereafter, the photoresist layer PR2 is removed, and the Cu thin film layer 6 is etched away using the wiring layer 16 as a mask.

The following step is a point of the present invention, in which the Si3N4 film SN is deposited on all surfaces including the wiring layer 16 and the Cu thin film layer by the plasma CVD method.

The imide resin formed in a later step is active and reacts with Cu. Therefore, it is necessary to cover the entire wiring layer 16 with this Si3N4 film. It is also necessary to protect the side surface M which is exposed by being patterned together with the wiring layer of Cu, here, the wiring layer. here,
Since the Si3N4 film is coated after patterning both, the side surface M is also protected.

Subsequently, an imide resin 17 is applied over the entire surface in a state protected by the Si 3 N 4 film SN, cured by a thermosetting reaction, and then exposed and developed to form an opening 18 in the polyimide layer 17 on the wiring layer 16. To form Film thickness up to 20
μm to 25 μm. The diameter of the opening is 50 μm.
About m is good.

After the development, the polyimide layer may be baked at a temperature of about 200 ° C.

Further, the opening 18 has a Si 3 N 4 film SN
Is exposed, the Si3 N4 film SN is removed using the opening 18 of the polyimide layer 17 as a mask.

Next, a Cu thin film layer 19 is formed on the entire surface as a plating electrode of the metal post 7. (Refer to FIG. 3 above.) Subsequently, a photoresist layer PR3 in which a metal post region to be formed is exposed is formed, and a metal post 7 made of Cu is formed via an electrode 19 for plating. Further, a Ni thin film layer 20 and a Cu thin film layer 21 are formed on the metal posts 7. (See FIG. 4 above.) Further, the solder plating layer 8 is formed via the photoresist layer PR3.
To form Finally, the photoresist layer PR3 is removed, and unnecessary portions of the seed layer 19 are removed by etching using the solder plating layer 8, the thin film layers 20, 21 as a mask. Then, the semiconductor substrate is divided into chips along the scribe lines by a dicing process, thereby completing a chip-size package.

Here, the timing of melting the solder into a spherical solder ball is before the dicing after the removal of the seed layer or after the dicing.

Although the present invention has been described with reference to the rewiring type, it goes without saying that the present invention can also be implemented with a resin-sealed type.

[0040]

According to the present invention, since the Si3N4 film is provided at the interface between the wiring layer and the polyimide resin 17,
The reaction between the imide resin before curing and Cu can be prevented. The side surfaces of the Cu thin film layer patterned together with the wiring layer are also covered with the Si3N4 film, so that the above reaction can be prevented.

Therefore, the interface between the Cu wiring layer, the Cu thin film layer and the polyimide resin is formed in a stable state without any reaction, so that moisture resistance, swelling and the like can be prevented.
The yield can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a chip size package according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a chip size package according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for manufacturing a chip size package according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing a chip size package according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a method of manufacturing a chip size package according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a method of manufacturing a chip size package according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating a conventional chip size package.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Toshige Toshishige 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. 5F033 JJ11 JJ33 KK08 PP26 QQ37 QQ90 RR06 RR22 SS15 SS22 XX18

Claims (3)

[Claims] In a chip size package in which a wiring mainly composed of Cu is formed on a chip and a thermosetting polyimide resin is coated on the wiring, an interface between the wiring and the polyimide resin is A chip size package characterized by being provided with a Si3N4 film. 2. A wiring layer mainly composed of Cu connected to a metal electrode pad mainly composed of Al and extending on a chip surface, and a thermosetting polyimide resin covering the chip surface including the wiring layer. A chip size package comprising: an insulating layer made of: an opening formed in the insulating layer on the wiring layer; a metal post formed in the opening; and a solder bump fixed to the metal post. Wherein a Si3N4 film is provided at an interface between the insulating layer and the wiring layer. 3. A first insulating layer having a first opening for forming a metal electrode pad by depositing and patterning an electrode material mainly composed of Al, and exposing a part of the metal electrode pad. Forming a wiring layer made of Cu extending on the chip surface on the metal electrode pad exposed from the first opening; and forming a Si layer on the chip surface including the wiring layer by plasma CVD.
After covering the chip surface with a thermosetting polyimide film, forming a second opening exposing a part of the wiring layer, forming a metal post in the second opening. And then forming a solder bump on the metal post.