JP2001168126A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To improve the reliability of a chip size package. SOLUTION: A wiring layer 7 made of Cu connected to an Al electrode 1 and extending on the chip surface is formed on the wiring layer 7 via a resin layer R so as to be located on the wiring layer 7. A metal post 8, a photosensitive block copolymerized polyimide layer P formed on the resin layer R excluding the head of the metal post, and Pd9, Ni10, Au1 on the metal post 8.
1 and a solder ball 12 formed therethrough.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a chip size package (Chip
Size Package, hereinafter referred to as CSP. ), Which is a general term for packages equal to or slightly larger than the chip size, and relates to package technology for high-density mounting.

[0002]

2. Description of the Related Art Conventionally, in this field, BGA (Ba
ll Grid Array), a structure with a plurality of solder balls arranged in a plane, a fine pitch BGA, a structure in which the ball pitch of the BGA is further narrowed and the outer shape is close to the chip size, etc. Are known.

Recently, there is a wafer CSP described in “Nikkei Microdevice”, August 1998, pp. 44-71. This wafer CSP is basically
This is a CSP in which wiring and array-like pads are formed by a wafer process (pre-process) before dicing a chip. It is expected that this technology will integrate the wafer process and the package process (post-process), thereby greatly reducing the package cost.

[0004] There are two types of wafer CSP: a resin sealing type and a rewiring type. The resin-sealed type has a structure in which the surface is covered with a sealing resin, similarly to a conventional package, in which metal posts are formed on a wiring layer on the chip surface, and the periphery thereof is solidified with the sealing resin.

It is generally said that when a package is mounted on a printed circuit board, stress generated due to a difference in thermal expansion between the printed circuit board and the printed circuit board is concentrated on the metal posts. It is believed to be decentralized.

On the other hand, in the rewiring type, as shown in FIG.
This is a structure in which rewiring is formed without using a sealing resin. That is, the Al electrode 52, the wiring layer 53, and the insulating layer 54 are stacked on the surface of the chip 51, and the metal posts 55 are formed on the wiring layer 53.
Is formed, and a solder ball 56 is formed thereon. Although not shown, for example, Pd, Ni, and Au are formed on the metal posts 55 on which the solder balls 56 are formed. The wiring layer 53 is used as a rewiring for arranging the solder balls 56 on the chip in a predetermined array.

[0007] In the resin sealing type, a metal post is 100 μm
By lengthening it and reinforcing it with sealing resin,
High reliability is obtained. However, the process of forming the sealing resin needs to be performed using a mold in a later step, and the process becomes complicated.

On the other hand, the rewiring type has an advantage that the process is relatively simple and most of the steps can be performed by a wafer process. However, there is a need to relieve stress in some way to increase reliability.

FIG. 12 is a view in which the wiring layer 53 of FIG. 11 is omitted, and an opening in which the Al electrode 52 is exposed is formed. In this opening, the metal post 55 and the aluminum electrode 5 are formed.
At least one barrier metal 58 is formed between
A solder ball 56 is formed on the metal post 55.

[0010]

Here, after the metal post 55 is formed as described above, the periphery thereof is sealed with, for example, an epoxy resin layer 54 or the like, and the resin layer 54 is polished to form the metal post 55. When the post 55 is exposed, as shown in FIG. 13, a streak or a scratch (hereinafter, referred to as a scratch S) formed on a surface of the resin layer by a grindstone during polishing.
Remains. 13A is a plan view showing the metal post 55 and a part of the resin layer 54 sealing the periphery thereof, and FIG. 13B is a sectional view taken along line XX.

When such scratches S are present on the surface of the resin layer, Pd of the pretreatment for electroless plating remains on the metal posts 55 on the scratches S, and Ni grows during Ni electroless plating and short-circuits. It was the cause of the failure.
Therefore, a step of cleaning the surface of the resin layer using, for example, hydrochloric acid (HCl) was required to remove the scratches S before forming Pd.

The effect of the scratches S can be reduced by reducing the particle size of the grindstone (diamond). However, in this case, the throughput is reduced, which is not practical.

[0013]

In view of the above problem, a semiconductor device according to the present invention comprises an Al electrode 1 as shown in FIG.
A wiring layer 7 made of Cu connected to the chip surface and extending on the chip surface; a metal post 8 formed on the wiring layer 7 via a resin layer R so as to be located on the wiring layer 7; A photosensitive block copolymer polyimide layer P formed on the resin layer R excluding the post head, and a solder ball 12 formed on the metal post 8 with Pd9, Ni10, and Au11 interposed therebetween. And

The manufacturing method is such that a wiring layer 7 made of Cu connected to the Al electrode 1 and extending on the chip surface is formed, and a photoresist layer PR2 having an opening k so as to cover the wiring layer 7 is formed. Is formed, and the photoresist layer P is formed.
A metal post 8 made of Cu is formed on the wiring layer 7 via R2. Subsequently, a resin layer R is formed so as to cover the metal posts 8, and the resin layers R are polished to expose the heads of the metal posts 8, and then formed on the resin layer R excluding the metal post heads. A photosensitive block copolymer polyimide layer P is formed. Then, P is placed on the metal post 8.
forming a solder ball 12 via d9, Ni10, and Au11.

Still another manufacturing method is to form a wiring layer 7 made of Cu connected to the Al electrode 1 and extending on the chip surface, and to form a photoresist layer having an opening k so as to cover the wiring layer 7. PR2 is formed, and the photoresist layer P is formed.
A metal post 8 made of Cu is formed on the wiring layer 7 via R2. Subsequently, a first photosensitive block copolymerized polyimide layer P is formed so as to cover the metal post 8, and the block copolymerized polyimide layer P is polished to expose the head of the metal post. A second photosensitive polyimide layer is formed on the first photosensitive polyimide layer P excluding the metal post head. And forming a solder ball 12 on the metal post 8 with Pd9, Ni10, and Au11 interposed therebetween.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described.

In FIG. 10, reference numeral 1 denotes the uppermost layer of metal (a portion which also functions as a bonding pad) in a normal wire bonding type IC chip. The interlayer insulating film in which the hole C is formed is shown in FIG.

In the lower layer of the contact hole C, a metal is formed in a plurality of layers, for example, in contact with a transistor (MOS type transistor or BIP type transistor), a diffusion region, a poly-Si gate or poly-Si. I have.

Here, the present embodiment has been described as a MOS type, but it is needless to say that the present invention can also be implemented with a BIP.

This structure is an IC generally called a one-layer metal, a two-layer metal, or the like.

FIG. 3 shows a passivation film. Here, the passivation film 3 is made of a Si nitride film, an epoxy resin, a polyimide layer, or the like, and is further covered with an insulating resin layer r. This insulating resin layer r
Realizes flatness as described later and keeps the height of the solder ball constant.

On the Al electrode 1, a TiN film (TiN) 5 is formed as a cap metal.

The passivation film 3 and the insulating resin layer r
An opening K exposing the TiN film 5 (TiN) 5 is formed, in which a Cu thin film layer 6 is formed as a plating electrode (seed layer) of a wiring layer. And on top of this is Cu
The wiring layer 7 formed by plating is formed.

Then, on the entire surface of the chip including the wiring layer 7,
A resin layer R made of resin is formed. However, although omitted in the drawing, the resin layer R and the Cu layer are provided at the interface between the resin layer R and the wiring layer 7 and between the resin layer R and the metal post 8 as described later.
Silicon nitride film (hereinafter referred to as Si
Of ₃ N ₄ film. ) May be provided.

The resin layer R can be implemented as long as it is a thermosetting or thermoplastic resin. In particular, the thermosetting resin is preferably an amic acid film, a polyimide, or an epoxy resin. Further, if it is a thermoplastic resin, a thermoplastic polymer (Hitachi Chemical Co., Ltd .: Himal) or the like is preferable. The amic acid film has a shrinkage of 30 to 50%.

Here, the resin layer R is made of a liquid amic acid.
Prepared as main material, spin-coated on the entire surface of wafer
It is formed with a thickness of about 20 to 60 μm. Then
Is polymerized by a thermosetting reaction. The temperature is
300 ° C. or higher. However, amic acid before heat curing
The resulting resin becomes very active under the above temperature, and Cu
And the problem of deteriorating the interface. But,
The above-mentioned Si ₃N₄By coating the membrane
Thus, the reaction with Cu can be prevented. here
Si₃N₄The thickness of the film is about 1000 to 3000
You.

The Si ₃ N ₄ film may be an insulating film having an excellent barrier property, but the SiO ₂ film is inferior in the barrier property. However, when using an SiO ₂ film, it is necessary to make the film thickness thicker than that of the Si ₃ N ₄ film. In addition, since the Si ₃ N ₄ film can be formed by a plasma CVD method, the step coverage thereof is excellent, which is preferable. Further, since the resin layer R is covered after the metal post 8 is formed, the Si ₃ N ₄
The formation of the film not only prevents the reaction between the wiring layer 7 made of Cu and the resin layer containing amic acid as a main material, but also prevents
Between the metal post 8 and the resin layer R containing amic acid as a main material can also be prevented.

On the head of the metal post 8 exposed from the resin layer R, a solder ball 12 is formed via Pd9, plated Ni10 and Au11 as described later. Then, a photosensitive polyimide layer P is formed on the surface of the resin layer R other than the head of the metal post 8.
Is formed.

In this embodiment, the photosensitive polyimide layer P
A so-called block copolymerized polyimide layer (made by P.I. R & D Co., Ltd .: trade name: Cupilon) which has been imidized before being applied as a coating is used (see JP-A-4-306232).

This block copolymerized polyimide layer is a polyimide solution which has already been imidized when spin-coated on the wiring layer 7 and is a material which is unlikely to react with Cu, thus deteriorating the interface. The fear can be suppressed. That is, it is not necessary to perform the heat imidization treatment of about 250 or more unlike the conventionally used polyamic acid solution, and it is possible to avoid the reaction with Cu occurring during this treatment.

On the head of the metal post 8 not covered with the polyimide layer P, the aforementioned Pd9, Ni
10 and Au11 are formed.

The purpose of forming the photosensitive block copolymerized polyimide layer P is to prevent Pd from entering polishing scratches and scratches S (see FIG. 13), which are conventionally generated during polishing of the resin layer 54. The polyimide layer P is used to repair the scratches S into which Pd enters.

The above Pd9, Ni10 and Au11
Is formed because of the metal post 8 made of Cu.
When a solder ball is formed directly on the substrate, the connection strength with the solder ball is degraded due to oxidized Cu, and when Au is directly formed to prevent oxidation, Au is diffused, so Ni Is inserted. Pd is used to selectively grow Ni, Ni prevents oxidation of Cu,
Au prevents oxidation of Ni.

Therefore, deterioration of the solder ball and deterioration of the strength are suppressed.

Here, Ni10 and Au11 are formed by electrolytic plating, but may be formed by electroless plating.

Next, a method of manufacturing the structure shown in FIG. 10 will be described.

First, a semiconductor substrate (wafer) on which an LSI having an Al electrode 1 is formed is prepared. Here, as described above, a single-layer metal, a two-layer metal IC, for example, the source electrode and the drain electrode of the transistor are formed as the first layer metal, and the Al electrode 1 in contact with the drain electrode is the second layer metal. It is formed as a metal.

Here, after forming a contact hole C of the interlayer insulating film 2 from which the drain electrode is exposed, A
An electrode material mainly composed of 1 and a Ti nitride film 5 are formed, and the Al electrode 1 and the Ti nitride film 5 are dry-etched into a predetermined shape using a photoresist layer as a mask.

Here, unlike the case where the passivation film 3 is formed and the barrier metal is formed in the contact hole C which is opened thereafter, the passivation film 3 can be formed at once with a photoresist layer including a Ti nitride film as a barrier metal. Can be simplified.

The Ti nitride film 5 functions as a barrier metal for a Cu thin film layer 6 to be formed later. Moreover, attention is paid to the fact that the TiN film is effective as an antireflection film. That is, it is also effective for preventing halation of the resist used in patterning. To prevent halation, a minimum of about 1200 ° to 1300 ° is required, and in order to provide a barrier metal function, it is preferably about 2000 ° to 3000 °. If the film is formed to be thicker than this, stress is generated due to the Ti nitride film.

After the Al electrode 1 and the Ti nitride film 5 are patterned, the entire surface is covered with a passivation film 3. As a passivation film, here, Si ₃ N ₄
Although a film is employed, a polyimide layer or the like is also possible (see FIG. 1 above).

Subsequently, the surface of the passivation film 3 is covered with an insulating resin layer r. In this embodiment, a positive photosensitive polyimide film is used for the insulating resin layer.
About μm is coated. Then, an opening K is formed.

By employing this photosensitive polyimide film, it is not necessary to form a separate photoresist layer to form the opening K in the patterning of the opening K in FIG. 2, and the use of a metal mask simplifies the process. Can be realized. Of course, a photoresist layer is also possible. Moreover, this polyimide film is also used for the purpose of flattening.
That is, in order for the height of the solder ball 12 to be uniform in all regions, the height of the metal post 8 needs to be uniform in all regions, and the wiring layer 7 also needs to be formed flat and accurately. For this purpose, a polyimide layer is applied, and since the resin is a resin having a certain viscosity and fluidity, its surface can be made flat.

Here, the Al electrode 1 also serves as a pad for external connection of the LSI, and functions as a wire bonding pad when not formed as a chip size package composed of solder balls (solder bumps) (see FIG. 2 above). ).

Subsequently, a Cu thin film layer 6 is formed on the entire surface.
The thin film layer 6 of Cu later becomes a plating electrode of the wiring layer 7 and is, for example, approximately 1000 to 2000 by sputtering.
It is formed with a thickness of about Å.

Subsequently, for example, a photoresist layer PR is formed on the entire surface.
1 and a photoresist layer PR1 corresponding to the wiring layer 7
(See FIG. 3).

Subsequently, the wiring layer 7 is formed by using the Cu thin film layer 6 exposed in the opening of the photoresist layer PR1 as a plating electrode. The wiring layer 7 needs to be formed to be as thick as about 2 to 5 μm in order to secure mechanical strength. Here, it is formed using a plating method, but may be formed by vapor deposition, sputtering, or the like.

Thereafter, the photoresist layer PR1 is removed (see FIG. 4).

Subsequently, a photoresist layer PR2 exposing a region where the metal post 8 is formed on the wiring layer 7 is formed, and a Cu metal post 8 is formed on the exposed portion by electrolytic plating. Also in this case, the Cu thin film layer 6 is used as a plating electrode (see FIG. 5).

Subsequently, the photoresist layer PR2 is removed (see FIG. 6).

After the epoxy resin layer R is formed so as to cover the metal post 8 via the photoresist layer PR2, the resin layer R is polished by a predetermined amount to expose the head of the metal post 8. (See FIG. 7 above).

At this time, a scratch S formed during polishing remains on the surface of the resin layer R as in the conventional case. Therefore, in the present invention, a photosensitive polyimide layer P is formed on the surface of the resin layer R other than the head of the metal post 8 so that the resin layer R
To repair the scratches S on the surface.

That is, after the photosensitive polyimide layer P is formed on the entire surface of the resin layer R including the metal posts 8, the polyimide layer P on the metal posts 8 is removed by exposure and development. The thickness of the polyimide layer P at this time may be, for example, 100 to 100 because the scratch S on the surface of the resin layer R may be filled.
It may be as thin as 500 ° (see FIG. 8).

Here, a feature of the present invention lies in the formation of the polyimide layer P. When the polyimide layer P is spin-coated, a so-called block copolymerized polyimide layer which has already been imidized is formed. First, a positive photosensitive polyimide was spin-coated on the entire surface of the wafer to a thickness of 100
After the formation of the polyimide layer P
Is polymerized by a thermosetting reaction to form a copolymerized polyimide layer. The temperature is at most about 200 ° C.

The block copolymerized polyimide layer is formed by spin coating at a high temperature (3
(50 ° C. or more) Since imidization by heat treatment (dehydration) is not necessary, spin coating on the metal post 8
It is cured only by applying heat treatment at a low temperature (200 ° C. or lower). Therefore, a reaction with Cu constituting the metal post 8 is unlikely to occur, and the risk of deteriorating the interface is small.

The object of the present invention can be achieved by using, for example, a Si ₃ N ₄ film instead of using the polyimide layer P. In this case, the metal post 8 is used.
When the photosensitive polyimide layer P is used, only the exposure and development steps are required via the resist film, whereas the Si ₃ N ₄ film requires only metal exposure via the resist film. Processes such as etching and removing the Si ₃ N ₄ film on the head of the post 8, ashing the resist film, and cleaning are required, and there is a problem that the number of working steps increases.

Subsequently, Pd9 is formed on the metal post 8 by about 1000 °, Ni10 is formed by about 1000 °, and Au11 is formed by about 5000 °, respectively, by electrolytic plating. Here, Pt and Pd may be used instead of Au (see FIG. 9).

Finally, the prepared solder balls 12 are aligned and mounted, and reflowed (see FIG. 10). Then, the semiconductor substrate is divided into chips along a scribe line by a dicing process, thereby completing a chip size package.

It is to be noted that the block copolymer polyimide layer may be used instead of the resin layer R for solidifying the periphery of the metal post 8. In this case, after the polishing step is completed, the block copolymer polyimide layer is used for repairing the scratches as described above. What is necessary is just to form a thin polyimide layer.

[0060]

According to the present invention, a photosensitive polyimide layer having a film thickness enough to fill a scratch formed during polishing for exposing the head of a metal post is formed, so that a plating is formed on the metal post. Short-circuit failure due to the remaining metal film remaining in the scratch can be suppressed.

Particularly, by using a photosensitive block copolymer polyimide layer, the reaction with Cu constituting the metal post can be suppressed, and the head of the metal post can be exposed only by exposure and development. Good workability.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 11 is a sectional view showing a conventional chip size package.

FIG. 12 is a sectional view showing a conventional chip size package.

FIG. 13 is a diagram for explaining a problem of a conventional chip size package.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Nobuyuki Takai 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. 5F033 HH07 HH08 HH11 HH13 JJ08 JJ11 JJ33 KK01 KK08 KK33 MM01 MM05 MM08 NN03 NN07 PP15 PP19 PP27 PP28 QQ03 QQ11 QQ37 QQ48 RR04 RR06 RR22 RR27 SS15 SS22 TT01 TT04

Claims (5)

[Claims] A wiring layer connected to the electrode pad and extending on the chip surface; a metal post formed on the wiring layer via a resin layer so as to be located on the wiring layer; A semiconductor device comprising: a block copolymer polyimide layer formed on a resin layer excluding a head; and a solder ball formed on a metal post. 2. The semiconductor device according to claim 1, wherein the block copolymer polyimide layer has photosensitivity. 3. A step of forming a wiring layer connected to the electrode pad and extending on the chip surface, forming a photoresist layer having an opening so as to cover the wiring layer, and forming the photoresist layer through the photoresist layer. Forming a metal post on the wiring layer, forming a resin layer so as to cover the metal post, and then polishing the resin layer to expose the head of the metal post; A method for manufacturing a semiconductor device, comprising: a step of forming a block copolymerized polyimide layer on a resin layer to be removed; and a step of forming solder balls on the metal posts. 4. A step of forming a wiring layer connected to the electrode pad and extending on the chip surface, forming a photoresist layer having an opening so as to cover the wiring layer, and forming the photoresist layer through the photoresist layer. Forming a metal post on the wiring layer, forming a first block copolymerized polyimide layer so as to cover the metal post, and then polishing the block copolymerized polyimide layer to expose the head of the metal post. A step of forming a second block copolymerized polyimide layer on the first block copolymerized polyimide layer excluding the metal post head, and a step of forming solder balls on the metal post. A method for manufacturing a semiconductor device, comprising: 5. The block copolymer polyimide layer has photosensitivity, and a solder ball is formed on the metal post exposed by exposing and developing the photosensitive block copolymer polyimide on the metal post. The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is formed.