JP2000022150A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To ensure the consistency of salicide technology with respect to the process of an analog device, completely suppress silicidation of an input / output unit, and improve the reliability and yield of the device. A titanium film is formed on the entire surface of a semiconductor substrate.
Is formed thereon, a titanium nitride film 313 is formed thereon, and a resist 310 is further formed thereon except for the resistance portion 304b and the input / output region (a). Using the resist 310 as a mask, the titanium nitride film 313 in the opening is removed (b).
After removing the resist 310, the titanium film 308 in the opening is removed using the titanium nitride film 313 as a mask (d). Gate electrode 1 of logic part where titanium film 308 remains
The silicon substrate 04a and the semiconductor substrate 301 are silicided by heat treatment to form a titanium silicide layer 311 (e). The unreacted titanium film 308 and titanium nitride film 313 are removed.
(f).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which is being miniaturized, and more particularly, to polycrystalline or single crystal silicon silicided at a gate electrode and a source / drain electrode for the purpose of lowering resistance. And a method of manufacturing a semiconductor device including both non-silicidized polycrystalline or single-crystal silicon such as a resistance element. Such a semiconductor device is a DS device mounted on a low-voltage driven, low-power-consumption semiconductor device, such as a portable device (pager, PHS) or the like, which has been commercialized in recent years.
It is used as a semiconductor device such as a P (digital signal processor) and an image processing chip.

[0002]

2. Description of the Related Art In recent years, along with the demand for miniaturization and high-speed operation of a semiconductor device, it has been necessary to form a transistor on a gate electrode and a source electrode.
A salicide technique for forming a silicide in a self-aligned manner on a drain electrode has been generally used. The surface where the polycrystalline or single-crystal silicon represented by the gate electrode, the source electrode, and the drain electrode is exposed is all silicided by salicide technology, and the formed silicide layer is 2 to 5 Ω / sheet. Since a layer resistance with a low resistance can be obtained, it is becoming an indispensable technique for reducing the parasitic resistance of a device.

However, when the salicide technique is applied to an analog device having a capacitance element or a resistance element, a problem in manufacturing occurs. That is, in a conventional analog device, particularly when a resistance element is formed, 1
Use an n-type or p-type high-concentration impurity diffusion layer region of about 00Ω / sheet, use an n-type or p-type well region of about 1000Ω / sheet, or use a two-layer polysilicon process of 20 to 50Ω / sheet. Or polycrystalline silicon. In particular, in recent years, in order to miniaturize the resistance element, polycrystalline silicon having a relatively low resistance value is often used. When the salicide technique is combined with such an analog process, the polycrystalline silicon for the resistance element is also silicided, and the resistance is reduced to about 2 to 5 Ω / sheet. Therefore, in order to obtain a necessary resistance, it is necessary to perform control such as further reducing the line width of the resistance element.

Further, the silicide layer has a difficulty in controlling the resistance value due to a large variation in layer resistance due to low thermal stability and the like. For this reason, when the salicide technique is applied to an analog device, it is necessary to prevent silicidation from occurring in polycrystalline silicon constituting the resistance element.

Further, not only analog devices, but also input / output circuit portions of semiconductor devices cause a relatively large current to flow, so that the gate oxide film is damaged by static electricity. To solve the problem, generally, the layout of the high-concentration impurity diffusion layer region forming the source / drain electrodes is considered,
Efforts are made to minimize the concentration of the electric field in the gate oxide film at the end of the gate electrode of the transistor in the input / output section. As a method therefor, there is a method of alleviating the electric field concentration utilizing the fact that the layer resistance of the high concentration impurity diffusion layer region of the source / drain is relatively high, about 100Ω / sheet.

However, when the salicide technique is combined with such an input / output circuit device, the high-concentration impurity diffusion region of the source / drain is also silicided,
Since the resistance is reduced to about 2 to 5 Ω / sheet, the electric field cannot be sufficiently reduced. Therefore, the resistance of the gate oxide film to electrostatic breakdown is reduced, which causes a failure. For this reason, it is necessary to prevent silicidation from occurring even on the high-concentration diffusion layer region in the specific region of the input / output circuit section.

As a conventional example for solving these problems, a silicide layer forming process is changed, a silicon oxide film is formed on the upper surface of a refractory metal film, and the silicon oxide film where no silicide layer is formed is removed. FIG. 1 shows a method of removing a high melting point metal film using an oxide film as a mask.
(Prior art 1).

In FIG. 1A, an element isolation region 102 made of a silicon oxide film, a gate oxide film 103, a gate electrode 104a made of polycrystalline silicon thereon, and a resistance portion are formed on a semiconductor substrate 101 made of single crystal silicon. , A gate sidewall insulating film 106 made of a silicon oxide film, a low-concentration impurity diffusion layer region 105,
In addition, a high concentration impurity diffusion layer region 107 is formed.
The low-concentration impurity diffusion layer region 105 and the high-concentration impurity diffusion layer region 107 serve as a source electrode or a drain electrode in the transistor portion. Semiconductor substrate 101
After performing a hydrofluoric acid-based solution pretreatment on the entire surface, titanium 108 as a high melting point metal is formed by a sputtering method. A silicon oxide film 109 is formed thereon by a plasma CVD method or the like. Furthermore, a resist 11
0 is formed by photolithography so as to open on the input / output unit and the resistance unit.

In FIG. 1B, using the resist 110 as an etching mask, the silicon oxide film 109 on the input / output part and the resistance part is etched away by the dry etching technique with the etching selectivity to the titanium layer 108. . Thereafter, in FIG. 1C, after the resist 110 is removed by plasma processing, the titanium film on the input / output part and the resistance part is etched with a chemical solution containing ammonia and hydrogen peroxide using the silicon oxide film 109 as an etching mask. 108 is removed. At this time, the resist film is generally sharply etched by the above-mentioned chemical solution, and thus the silicon oxide film 109 is required as a mask.

Next, in FIG. 1D, the silicon oxide film 109 is removed by wet etching or dry etching. Next, in FIG. 1 (e), a heat treatment at about 650 ° C. is performed by a normal rapid heat treatment (abbreviated as RTA), and the polycrystalline silicon surface of the gate electrode 104 where the titanium remains is removed. The single-crystal silicon surfaces of the source / drain electrodes 105 and 107 are silicided. At this time, a relatively high-resistance silicide layer 111 (30 to 50 Ω / sheet) is formed.

Next, referring to FIG.
02, the gate sidewall insulating film 106 and the silicide layer 1
The unreacted titanium film 108 remaining on the silicon nitride film 11 and the titanium nitride film formed during the heat treatment are selectively removed by etching. At this time, etching is performed by a wet etching technique using a chemical solution containing ammonia and aqueous hydrogen peroxide as an etchant. Next, in FIG. 1 (g), a heat treatment at about 850 ° C. is performed by a normal RTA method to transfer the phase of the silicide layer 111 to the low-resistance silicide layer 112 of about 2 to 5 Ω / sheet.

Next, another conventional technique for suppressing the silicidation of the resistance portion will be introduced (see Japanese Patent Application Laid-Open No. 7-202012, prior art 2). As shown in FIG. 2, a silicon oxide film 206 is left on the surface of the polycrystalline silicon 204b on the resistance portion so that only the resistance portion is not silicided at the time of silicidation by the salicide technique. First, in FIG. 2A, on the semiconductor substrate 201, an element isolation region 202 and a gate oxide film 203 made of a silicon oxide film, a gate electrode 204a and a resistance part 204b made of polycrystalline silicon, A low concentration impurity diffusion layer region 205 is formed. next,
In FIG. 2B, a silicon oxide film 206 is formed on a semiconductor substrate 201 made of single crystal silicon. Then, in order to leave the silicon oxide film 206 on the resistance portion 204b, that is, to prevent the formation of a silicide layer in the resistance portion 204b, the resist film 2 is formed by photolithography.
10 is formed on the resistance element.

Thereafter, as shown in FIG. 2C, the silicon oxide film 206 is etched by anisotropic etching using a dry etching technique to form a gate side wall insulating film 206a on the side wall of the gate electrode 204a.
The silicon oxide film 206 is left on 04b. Thereafter, the resist film 210 is removed by plasma etching, and the high-concentration impurity diffusion layer region 207 is formed by ion implantation and heat treatment. The low concentration impurity diffusion layer region 2
05 and the high concentration impurity diffusion layer region 207 play a role of a source electrode or a drain electrode in the transistor portion. Thereafter, after performing a hydrofluoric acid-based solution pretreatment on the entire surface of the semiconductor substrate 201, titanium 2 which is a high melting point metal is used.
08 is formed by a sputtering method.

Next, in FIG. 2D, a heat treatment at about 650 ° C. is performed by a normal RTA method, and the polycrystalline silicon surface of the gate electrode 204a where the titanium 208 remains and the source / drain electrodes 205, The single crystal silicon surface 207 is silicided. At this time, a relatively high-resistance silicide layer 211 (30 to 50 Ω / sheet) is formed. Next, in FIG.
On the gate sidewall insulating film 206a and the silicide layer 21
The unreacted titanium film 208 remaining on the substrate 1 and the titanium nitride film formed during the heat treatment are selectively removed by etching. At this time, etching is performed by a wet etching technique using a chemical solution containing ammonia and aqueous hydrogen peroxide as an etchant. Next, in FIG.
A heat treatment at about 850 ° C. is performed by a normal RTA method to transfer the phase of the silicide layer 211 to the low-resistance silicide layer 212 of about 2 to 5 Ω / sheet.

[0015]

In the prior art 1, in FIG. 1D, the silicon oxide film 109 remaining on the semiconductor substrate 101 is removed by wet etching or dry etching. At this time, when the etching is performed by wet etching, the selectivity with respect to the exposed portions of the titanium film 108, the polycrystalline silicon film of the gate electrode 104a, and the single crystal silicon film forming the source / drain electrodes 107 is determined. Although it is possible to perform etching while maintaining the same, it is impossible to perform etching selectivity with the exposed gate sidewall insulating film 106 because the same material is used. Therefore, the gate sidewall insulating film 106 is also isotropically etched, and the gate oxide film 1 is removed.
03 has the drawback of lowering the electrical reliability and lowering the device yield.

When the etching of the silicon oxide film 109 is performed by dry etching, the titanium film 108 and the gate electrode 104a are etched similarly to the case of wet etching.
It is possible to perform etching while maintaining the selectivity with respect to the exposed portion of the polycrystalline silicon film or the polycrystalline silicon film or the single crystal silicon film constituting the source / drain electrodes 107, Damage to the titanium film 108, the gate electrode 104a, and the like occurs. Further, the etching selectivity with the exposed gate side wall insulating film 106 is impossible because the same material is used, and the gate side wall insulating film 106 is etched though having anisotropy. For the above reasons, there is a disadvantage that the electrical reliability of the gate oxide film 103 is lowered and the yield of the device is lowered.

Next, in the prior art 2, as shown in FIG. 2, when forming the gate sidewall insulating film 206, the silicon oxide film 206 is left on the resistance portion 204b, and the resistance portion 204b is silicided. It does not happen. However, on the other hand, the source and
Silicidation also occurs in the drain region, which reduces the resistance to electrostatic breakdown and lowers the yield of the device. If the silicon oxide film 206 is left in the input / output section in order to suppress silicidation in the input / output section, ion implantation for forming the high-concentration impurity diffusion layer region 207 shown in FIG. In some cases, the silicon oxide film serves as an implantation mask, so that the high-concentration impurity diffusion layer region 207 cannot be formed. Therefore, the silicon oxide film 10 is formed in a region where the silicidation is not desired to occur in an arbitrary portion of the input / output portion.
6 cannot be left.

Accordingly, an object of the present invention is to solve these problems of the prior art and to suppress the occurrence of silicidation at an arbitrary position on a semiconductor substrate in a salicidation process.

[0019]

The present invention comprises the following steps:
A MOS transistor having a salicide structure in which (A) to (H) are silicidized, and the gate electrode and the source and drain electrodes are self-aligned and have low resistance on the source and drain electrodes by a silicide film of a high melting point metal. This is a method for manufacturing a semiconductor device. (A) a step of forming a refractory metal film on the entire surface of a semiconductor substrate;
(B) a step of forming a refractory metal nitride film on the refractory metal film, (C) a step of forming a resist film on the refractory metal nitride film except for a region that is not to be silicided, and (D) masking the resist film. Removing the refractory metal nitride film in the region that is not silicided, (E) removing the resist film, and then removing the refractory metal film in the non-silicide region using the refractory metal nitride film as a mask;
(F) a step of silicidizing the semiconductor member where the refractory metal film remains by heat treatment, (G) a step of removing unreacted refractory metal film and refractory metal nitride film,
(H) a step of reducing the layer resistance of the silicified refractory metal film by heat treatment.

The configuration of the method for manufacturing a semiconductor device according to the present invention will be described below. FIG. 3 is a process cross-sectional view illustrating a configuration of a method for manufacturing a semiconductor device of the present invention. In FIG. 3A, an element isolation region 302 made of a silicon oxide film, a gate oxide film 303, a gate electrode 304a made of polycrystalline silicon thereon, a polycrystalline silicon 304b for a resistance portion, A gate sidewall insulating film 306 made of a silicon oxide film, a low-concentration impurity diffusion layer region 305, and a high-concentration impurity diffusion layer region 307 are formed. Low concentration impurity diffusion layer region 305 and high concentration impurity diffusion layer region 30
Reference numeral 7 plays a role of a source electrode or a drain electrode in the transistor portion. After the refractory metal 308 is formed on the entire surface of the semiconductor substrate 301, a refractory metal nitride film 313 is further formed thereon. Next, by photolithography technology, a resist 310 is formed so as to open the input / output section and the resistance section and cover the logic section.

Next, referring to FIG.
Is used as an etching mask to remove the high melting point metal nitride film 313 of the input / output portion and the resistance portion by etching with the lower high melting point metal film 308 having etching selectivity. FIG. 3 (c)
Then, the resist 310 is removed by etching. In FIG. 3D, the high melting point metal film of the input / output section and the resistance section is removed using the high melting point metal nitride film 313 as an etching mask.

In FIG. 3E, a heat treatment is performed to silicide the upper surface of the gate electrode 304a and the surface of the source / drain electrode 307 where the refractory metal film 308 and the refractory metal nitride film 313 are laminated and left. And a relatively high-resistance silicide layer 311 is formed. In FIG. 3F, the gate sidewall insulating film 306 is formed on the element isolation region 302.
The unreacted refractory metal 308 and refractory metal nitride film 313 remaining on the upper and silicide layers are selectively etched with respect to the silicide layer, the silicon oxide film and the like. In FIG. 3G, a heat treatment is performed to
11 is transferred to the low-resistance silicide layer 312. After that, an interlayer insulating film, a connection hole with a metal wiring, several layers of metal wiring, and a protective film are formed in the same manner as in a normal manufacturing method of a MOS semiconductor device to complete a semiconductor device.

The above is the configuration of the method for manufacturing a semiconductor device according to the present invention. In this way, the silicidation of the resistance portion is suppressed without lowering the reliability and yield of the gate oxide film of the transistor, and the resistance element is formed with good yield and uniformity. Of the gate oxide film at the end of the gate electrode without silicidation of the source / drain electrodes of the input / output section The electrostatic breakdown resistance of the film can be improved, and the reliability and yield of the device can be improved.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS It is preferable to use a titanium film and a nitride film of a titanium film as a refractory metal film and its nitride film. As described above, it is preferable to use a refractory metal film and a nitride film of the refractory metal because they can be formed by continuous processing in the same apparatus. As a result, the throughput is improved, and the yield is improved because the semiconductor substrate is not exposed to the air between the steps. It is preferable that the thickness of the refractory metal nitride film be 30 to 70 nm. As a result, when the refractory metal nitride film is etched using the refractory metal nitride film as an etching mask, damage to the refractory metal film due to the reduction of the refractory metal nitride film is suppressed, and the unreacted metal film after the silicide layer is formed is suppressed. When the reactive high-melting point metal film and high-melting point metal nitride film are removed by etching, the etching time is optimized, preventing damage to the silicide layer due to long exposure of the silicide layer to the chemical solution, and lowering the resistance of the silicide layer. Can be planned.

A resistive element region using the resist film as a mask,
The step of removing the high melting point metal nitride film in the capacitor element region or the input / output element region is preferably performed by plasma treatment using a gas system containing at least fluorine, carbon, and oxygen. As a result, etching selectivity between the high melting point metal film and the nitride film can be secured. The step of removing the resist film is preferably performed by plasma treatment using a gas system containing oxygen without containing fluorine. As a result, since the lower refractory metal nitride film is not etched, the refractory metal film at an arbitrary position on the semiconductor substrate can be etched using the refractory metal nitride film as an etching mask. It is preferable that the step of removing the refractory metal nitride film at a part of the semiconductor substrate using the resist film as a mask and the step of removing the resist film are performed by continuous plasma processing in the same apparatus. As a result, the throughput is improved, and the yield is improved because the semiconductor substrate is not exposed to the air between the steps.

The step of removing the high-melting-point metal film in the resistance element region, the capacitor element region or the input / output element region using the high-melting-point metal nitride film as a mask may be performed by a wet process using a chemical solution containing ammonia and hydrogen peroxide. preferable. As a result, since etching can be performed with high etching selectivity, no etching damage occurs to the refractory metal film below the refractory metal nitride film, and the formation of a silicide layer in a later step is promoted. In addition, since etching damage to the lower semiconductor substrate and the silicon oxide film after the etching of the high melting point metal film does not occur, it is possible to prevent a decrease in the electrical reliability of the gate oxide film at the end of the transistor and the gate electrode in that region.

Prior to the step of forming a refractory metal film on the entire surface of the semiconductor substrate, arsenic, argon or silicon is ion-implanted on the entire surface of the semiconductor substrate by ion implantation to form polycrystalline silicon constituting a gate electrode and source / drain electrodes. And a step of amorphizing single crystal silicon. As a result, since the vicinity of the surface of the region to be silicided is amorphous, the formation of the silicide layer is promoted,
In particular, an increase in resistance is suppressed by a thin gate electrode having a thickness of 1.0 μm or less, and uniformity is improved.

The step of silicidizing the portion where the high melting point metal film remains by heat treatment is performed by performing a relatively low temperature RTA process at 400 ° C. to 550 ° C., and subsequently at 600 ° C. to 7 ° C.
It is preferably performed by a two-stage continuous heat treatment in which a relatively high temperature RTA treatment of 50 ° C. is performed. As a result, a fine amorphous silicide layer is formed in the initial stage of silicidation, and the formation of a C49 phase silicide layer is promoted. In particular, a rise in resistance is suppressed by a thin gate electrode of 1.0 μm or less. And the uniformity is improved.

The step of removing the refractory metal nitride film by using the resist film as a mask is performed by plasma processing. As a gas used in the plasma processing, a gas system containing at least fluorine, carbon and oxygen is used, and preferably at least carbon and fluorine are used. Is used, more preferably, a mixed gas of CF ₄ or CHF ₃ and oxygen is used. More preferably, the volume ratio of the fluorine-based gas to oxygen gas is 0.05 to 0.2. Preferably, the processing pressure during the plasma processing is more preferably set to 50 Pa or more. As a result, it is possible to prevent the lower refractory metal film from being etched and the gate oxide film and the like constituting the transistor from being damaged by etching.

In the composition of the refractory metal nitride film formed on the refractory metal film, it is preferable that the volume content of nitrogen with respect to the refractory metal is 0.4 to 0.6. as a result,
The etching rate of the refractory metal nitride film when etching the refractory metal nitride film using the resist as an etching mask is increased, and the refractory metal when the refractory metal nitride film is etched using the refractory metal nitride film as an etching mask. By reducing the etching rate of the nitride film, etching selectivity in both steps can be ensured, damage to the transistor can be suppressed, and silicidation can be promoted.

[0031]

Next, examples will be described. As Example 1,
The case where a titanium film is used as a high melting point metal film and a titanium nitride film is used as a high melting point metal nitride film will be described. Since the configuration is the same as that of FIG. 3, it will be described with reference to FIG. FIG.
(a), a semiconductor substrate 30 made of single crystal silicon;
A well for forming an n-type transistor and a p-type transistor is formed on 1, and a silicon oxide film as an element isolation region 302 is formed by a LOCOS method. After that, ion implantation for determining the threshold voltage of the transistor is performed, and then a silicon oxide film serving as the gate oxide film 303 is formed with a thickness of 9 nm by thermal oxidation.

Next, a polycrystalline silicon film containing phosphorus is formed to a thickness of 200 nm by a normal pressure CVD method, and the gate electrode 30 is formed by photolithography and dry etching.
Process into 4a. At the same time, a polycrystalline silicon film is processed and left at an arbitrary position on the element isolation region 302 for forming the resistance portion 304b. At this time, the layer resistance of the polycrystalline silicon film forming the resistance portion 304b finally becomes 20 to 5
The impurity concentration of phosphorus is controlled so as to have an arbitrary resistance of 0Ω / sheet. In the first embodiment, the resistance portion 304b is formed at the same time when the gate electrode 304a is formed. However, when a two-layer process for forming a capacitance is performed, the resistance portion 304b can be formed in another step.

Next, arsenic and boron are ion-implanted into the n-type transistor region and the p-type transistor region of the semiconductor substrate 301, respectively, using the gate electrode 304a and the element isolation region 302 as implantation masks.
05 is formed. Thereafter, a silicon oxide film is deposited on the entire surface of the semiconductor substrate by a thermal CVD method at about 800 ° C., and a gate sidewall insulating film 306 is formed by etch-back using a dry etching technique. Next, arsenic is implanted into the n-type transistor region of the semiconductor substrate 301 and boron difluoride is implanted into the p-type transistor region, thereby forming a high-concentration impurity diffusion layer region 307. After that, heat treatment,
The implanted impurities are activated.

Next, after a hydrofluoric acid-based solution pretreatment is performed on the entire surface of the semiconductor substrate 301, a titanium film 308 and a titanium nitride film 313 are formed thereon by a magnetron sputtering method using the same apparatus as a 30 nm and 50 nm film, respectively. It is formed continuously with a thickness. At this time, the volumetric content of nitrogen in the titanium nitride film is about 0.5. Next, on the titanium nitride film 313, a resist film 310 is formed by spin coating and photolithography to open a portion where the silicide layer is not formed in the input / output portion and the resistor portion, and cover the logic portion where the silicide layer is formed. It is formed as follows.

Next, referring to FIG.
Is used as an etching mask to etch the titanium nitride film 313 of the input / output portion and the resistance portion with the etching selectivity to the titanium film 308 of the lower layer. The etching at this time is performed by plasma treatment of a binary gas of CF ₄ and O ₂ , and the etching rate of the titanium film 308 is much lower than the etching rate of the titanium nitride film 313, so that the etching selectivity is secured. ing.

Thereafter, in FIG.
0 is removed by plasma processing using only oxygen gas (synonymous with dry etching). By using this gas, the titanium nitride film 313 is not etched. The etching of the titanium nitride film 313 and the resist 310
Was removed by continuous plasma treatment in the same apparatus. Next, in FIG. 3D, using the titanium nitride film 313 as an etching mask, the titanium film 308 of the input / output portion and the resistance portion is removed by wet etching. At this time,
By using a chemical solution containing ammonia and hydrogen peroxide, the etching rate of the titanium nitride film 313 is about 1/20 of the etching rate of the titanium film 308, so that the titanium nitride film 313 is effective as an etching mask. To contribute.

Next, in FIG. 3E, a rapid thermal treatment at 700.degree. C. is performed by the RTA method, and the polycrystalline layer above the gate electrode 304a is left where the titanium film 308 and the titanium nitride film 313 are laminated. Silicon and single crystal silicon on the source / drain electrode 307 are silicided,
A titanium silicide layer 311 made of a C49 phase of a relatively high-resistance TiSi ₂ layer is formed. Next, in FIG. 3F, the unreacted titanium film 308 remaining on the element isolation region 302, the gate sidewall insulating film 306 and the titanium silicide layer 311 and the titanium nitride film 313 are replaced with the titanium silicide layer 311, The element isolation region 302, the gate sidewall insulating film 306, and the semiconductor substrate 301 are selectively etched. At this time, removal is performed by a wet process using a chemical solution containing ammonia and hydrogen peroxide as an etching solution. However, as described above, the etching speed of the titanium film and the titanium nitride film with respect to the chemical solution is different. It is necessary to adjust to a titanium nitride film having a low etching rate. However, since the etching selectivity between the titanium nitride film 313 and the titanium silicide layer 311 is much larger than that, there is no damage to the titanium silicide layer 311 and the transistor region.

Next, in FIG. 3 (g), a rapid heat treatment at 850 ° C. is performed by the RTA method to form a titanium silicide layer 311 composed of a TiSi ₂ C49 phase into a titanium silicide layer TiSi ₂ C54 having a low resistance of about 5 Ω / sheet. Phase 312
Phase transition. After that, as in a normal manufacturing method of a MOS type semiconductor device, an interlayer insulating film, a connection hole with a metal wiring,
And a metal wiring are formed to complete the semiconductor device.

According to the first embodiment, a region where a silicide layer is not formed can be formed at an arbitrary position on a semiconductor substrate, and a decrease in electrical reliability of a transistor region where a silicide layer is not formed can be prevented. Further, since the input / output area is not silicided, the occurrence of defects due to electrostatic breakdown of the semiconductor device can be suppressed. Further, by not forming silicide on the polycrystalline silicon which is the resistance of the resistance part, a resistance part having a layer resistance value of about 40Ω / sheet and good uniformity can be supplied.

Table 1 shows the evaluation results of the yield of the breakdown voltage of the gate oxide film according to the first embodiment in comparison with the above-mentioned conventional technology 2 and the case where the salicide technology is not used.
In the evaluation, the ratio of the element exhibiting a deteriorated withstand voltage to the element satisfying the specified withstand voltage in the gate oxide withstand voltage evaluation element having the area of 10000 μm ² is shown.

[0041]

[Table 1]

From Table 1, it is considered that in the prior art 2, the yield is reduced due to the damage in the step of removing the silicon oxide film for forming the silicide non-forming region. As in the case where the salicide technique is not used, the yield is high, indicating that no damage to the gate oxide film occurs.

Table 2 shows the yield of non-defective products with respect to the destruction of the electrostatic breakdown evaluation element installed in the input / output section, when the gate electrode and the source / drain electrodes of the input / output section are all silicided, and 1 is shown in comparison with FIG.

[0044]

[Table 2]

In Table 2, in Example 1 where the source / drain electrodes of the input / output section were not silicided, the resistance was not reduced by silicidation of the diffusion layer region forming the source / drain electrodes, and was approximately 100 Ω / cm. Since the resistance is relatively high as in the sheet, the electric field concentration on the gate oxide film at the end of the gate electrode is reduced, and the yield of non-defective products against electrostatic breakdown is improved. On the other hand, when the gate electrode and the source / drain electrodes of the input / output part are all silicided, the electric field concentration on the gate oxide film at the end of the gate electrode is reduced because the resistance of the diffusion layer region is reduced to 5Ω / sheet. Increasing yields have significantly reduced yields.

Table 3 shows the resistance values of the resistance portions and their variations by comparing the case where all the resistance portions are silicified with the first embodiment.

[0047]

[Table 3]

In Table 3, when all the resistance portions were silicided, the polycrystalline silicon for resistance was also silicided, the layer resistance dropped to 5 Ω / sheet, and the variation increased. This is presumably because silicidation has occurred unevenly. On the other hand, in Example 1, since the resistance portion was not silicided, the layer resistance was 40 Ω / sheet, and the variation was as low as 2% or less.

In the first embodiment, in the region to be silicided shown in FIG. 3E, an RTA process for forming a titanium silicide layer 311 is performed in a state where the titanium film 308 and the titanium nitride film 313 are laminated. Is performed. This suppresses an increase in resistance particularly at a gate electrode of a thin line of 1.0 μm or less. FIG. 4 shows the layer resistance of the silicide layer with respect to the line width of the gate electrode in comparison with the case where the titanium nitride film 313 is not provided and the case of the first embodiment. The result indicated by the dotted line is the case where the titanium nitride film 313 is not provided, and the result indicated by the solid line is the case of the first embodiment. The layer resistance is a value when the semiconductor device is finally completed through all processes.

As shown in FIG. 4, it can be seen that the semiconductor device according to Example 1 suppresses a rise in resistance in a thin wire as compared with the case where no titanium nitride film is provided. The reason why the layer resistance of the thin wire is increased is due to the non-uniformity of the titanium silicide layer 311 to be formed and the low heat resistance.
In the case of the first embodiment, the titanium nitride film 3
13 are stacked, the titanium silicide layer 311 is more uniformly formed during the silicidation shown in FIG.
This suppresses an increase in the layer resistance.

Next, as a second embodiment, a method for further suppressing an increase in the layer resistance of the silicide layer in the fine wire will be described with reference to FIG. The method for manufacturing the semiconductor device according to the second embodiment includes:
Since it is almost the same as the first embodiment, only the characteristic steps will be described below. In FIG. 3A, as a pre-process for depositing a titanium film 308 by a magnetron sputtering method, arsenic is implanted into the entire surface of the semiconductor substrate 301 at a dose of 5 × 10 ¹⁴ cm ⁻² to form a region to be silicided. Was made amorphous near the surface. Thereby, the formation of the C49 phase of the titanium silicide layer 311 in FIG. 3E was promoted, and the uniformity was improved.

FIG. 5 shows the layer resistance of the titanium silicide layer with respect to the line width of the gate electrode, comparing the case without the arsenic implantation (Example 1) and the example 2. The result shown by the dotted line is the case without arsenic implantation, and the result shown by the solid line is the case of Example 2. The layer resistance is a value when the semiconductor device is finally completed through all processes. As shown in FIG. 5, it can be seen that the increase in the resistance of the thin wire is suppressed as compared with the case where arsenic is not implanted. This is because, in the case of the second embodiment, the titanium nitride film 313 is laminated on the titanium film 308 and the surface to be silicided is amorphous, so that the titanium film 308 in FIG. This is because the titanium silicide layer 311 was more uniformly formed at the time of silicidation, and the silicidation itself was promoted. It is considered that the increase in the layer resistance was thereby suppressed. For this reason, ions are implanted into the entire surface of the semiconductor substrate 301 as a pre-process for depositing the titanium film 308,
Preferably, the vicinity of the surface of the region to be silicided is made amorphous.

Next, as a third embodiment, another method for further suppressing an increase in the layer resistance of the titanium silicide layer in a thin wire will be described with reference to FIG. Since the manufacturing method of the semiconductor device of the third embodiment is almost the same as that of the first embodiment, only the characteristic steps will be described below. In FIG. 3A, arsenic is implanted at a dose of 5 × 10 ¹⁴ cm ⁻² as in the second embodiment.
The vicinity of the surface of the region to be silicided was made amorphous. Then, in FIG. 3E, when the laminated titanium nitride film and titanium film are heat-treated by the RTA method to form the C49 phase of the titanium silicide layer 311, the RTA treatment is performed at 500 ° C. for 60 seconds. After performing the RTA process, 7
RTA treatment at 00 ° C. for 30 seconds was continuously performed. 500
The addition of the relatively low-temperature RTA process at 60 ° C. for 60 seconds promoted the formation of the C49 phase of the titanium silicide layer 311 and improved the uniformity.

FIG. 6 shows the layer resistance of the titanium silicide layer with respect to the line width of the gate electrode.
A case where the A process is not performed (Example 2) and Example 3 are shown in comparison. The result shown by the dotted line is the RTA at 500 ° C. for 60 seconds.
In the case where there is no processing, the result shown by the solid line is the case of the third embodiment. The layer resistance is a value when the semiconductor device is finally completed through all processes.

As shown in FIG. 6, it can be seen that the increase in the resistance of the thin wire is suppressed as compared with the case where the RTA treatment at 500 ° C. for 60 seconds is not performed. This is in the case of Example 3.
Since the titanium nitride film 313 is stacked on the titanium film 308 and the surface to be silicided is amorphous, a relatively low temperature of 500 ° C. is required before the RTA treatment of silicidation at 700 ° C. for 30 seconds. By adding the RTA treatment at 60 ° C. for 60 seconds, a fine amorphous titanium silicide layer 311 is formed at the beginning of the silicidation start, whereby the silicidation by the RTA treatment at 700 ° C. for 30 seconds is performed. This is because the titanium silicide layer 311 was formed uniformly and the silicidation itself was promoted, and it is considered that the increase in the layer resistance was thereby suppressed. For this reason, when forming the C49 phase of the titanium silicide layer 311, the RTA process is performed at a low temperature of about 500 ° C. and then at a temperature of about 700 ° C.
Preferably, the treatment is performed continuously.

Next, as a fourth embodiment, in FIG. 3B, the processing gas type and processing pressure of dry etching when the titanium nitride film 313 of the input / output section and the resistance section is etched using the resist 310 as an etching mask. Stipulates,
A method of improving the etching selectivity with the lower titanium film 308 to prevent the lower titanium film from being etched to prevent etching damage to a gate oxide film and the like constituting a transistor will be described with reference to FIG. I do. The manufacturing method of the semiconductor device of the fourth embodiment is almost the same as that of the first embodiment, and only the characteristic steps will be described below.

In FIG. 3B, the titanium nitride film 31 is formed.
3 is performed by dry etching, and carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) are used as etching gases.
₂ ) was used. Table 4 shows the result of examining the etching selectivity of the titanium nitride film 313 with respect to the titanium film 308 when the volume ratio of carbon tetrafluoride to oxygen was changed to 0 to 0.3.

[0058]

[Table 4]

In Table 4, when the gas volume ratio of CF _{4 to} O ₂ is 0.05 to 0.20, the result that the etching selectivity of the titanium nitride film 313 to the titanium film 308 is good is obtained. If the gas volume ratio is smaller than 0.05, the etching rate of the titanium nitride film 313 is sharply reduced, and the etching does not proceed as in the case of the titanium film 308, and the selectivity is reduced. On the other hand, when the gas volume ratio is larger than 0.2, the etching rate of the titanium film 308 increases, and the titanium film 308 is etched similarly to the titanium nitride film 313, and the selectivity decreases. For this reason, it is preferable to use a gas having a gas volume ratio of CF _{4 to} O ₂ of 0.05 to 0.20 as a processing gas for dry etching when the titanium nitride film 313 is etched.

The processing pressure in Example 4 was set to 20 to 300
Table 5 shows the results of examining the etching selectivity of the titanium nitride film 313 with respect to the titanium film 308 when Pa was changed.

[0061]

[Table 5]

In Table 5, when the processing pressure is in the range of 50 Pa or more, the titanium nitride film 3
13 shows that the etching selectivity is good. If the processing pressure is lower than 50 Pa, the etching rate of the titanium film is sharply increased due to ion bombardment and the titanium film is etched, and the selectivity is reduced. For this reason, it is preferable that the processing pressure of the dry etching when etching the titanium nitride film 313 be 50 Pa or more.

Next, as Example 5, by defining the composition of the titanium nitride film 313 formed on the titanium film 308, the input / output section and the input / output portion were formed using the resist 310 shown in FIG. Titanium nitride film 313 of resistance part
3D, the etching rate of the titanium nitride film 313 is increased, and when the titanium film 308 of the input / output portion and the resistance portion is etched using the titanium nitride film 313 as an etching mask as shown in FIG. A method for lowering the etching rate of the titanium nitride film 313 will be described with reference to FIG. This ensures etching selectivity in each step, suppresses damage to the transistor, and promotes silicidation. The manufacturing method of the semiconductor device of the fifth embodiment is almost the same as that of the first embodiment, and only the characteristic steps will be described below.

In FIG. 3A, as the composition of the titanium nitride film 313 deposited by the magnetron sputtering method, the nitrogen content of the titanium
Changed to 0.1 and 0.4 to 0.6. In that case, FIG.
Table 6 shows the etching selectivity of the titanium nitride film 313 with respect to the lower titanium film 308 in the case where the titanium nitride film 313 of the input / output portion or the resistance portion is etched using the resist 310 as an etching mask as described in FIG.

[0065]

[Table 6]

The titanium nitride film 3 shown in FIG.
13 is used as an etching mask to etch the titanium film 308 in the input / output section and the resistance section.
Table 7 shows the etching selectivity of the titanium film 308 with respect to No. 3.

[0067]

[Table 7]

When the titanium nitride film 313 is formed by a method such as magnetron sputtering, the volume content of nitrogen with respect to titanium is determined by the ratio of the nitrogen gas contained in the sputtering gas at the time of processing, and is generally 0 to 10.
It is divided into a case where the content ratio is 0.1 and a case where the content ratio is 0.4 to 0.6. In Tables 6 and 7, when the volume content of nitrogen with respect to titanium was set to 0.4 to 0.6, good results were obtained for the respective etching selectivity, but the volume content was 0 to 0.1. When the nitrogen content is low, the etching selectivity is both poor. This is because the etching characteristic of the formed titanium nitride film 313 is relatively close to that of the titanium film 308 when the content rate is 0 to 0.1. For this reason, the titanium nitride film 313 preferably has a volumetric content of nitrogen to titanium of 0.4 to 0.6.

Next, as a sixth embodiment, the titanium nitride film 31
3D, the thickness of the titanium nitride film 313 in the case of etching the titanium film 308 of the input / output part and the resistance part using the titanium nitride film 313 as an etching mask as shown in FIG. A method for preventing the lower titanium film 308 from being damaged due to the above will be described with reference to FIG.
Titanium film 3 only in the region where titanium nitride film 313 is open
08 is etched. The manufacturing method of the semiconductor device of the sixth embodiment is almost the same as that of the first embodiment, and only the characteristic steps will be described below. In FIG. 3A, the thickness of the titanium nitride film 313 deposited by the magnetron sputtering method was changed to 10 to 100 nm. Table 8 shows the results of evaluating the layer resistance of the titanium silicide layer in that case.

[0070]

[Table 8]

In Table 8, by setting the thickness of the titanium nitride film 313 to 30 to 70 nm, the layer properly functions as an etching mask, and the layer resistance of the titanium silicide layer 311 corresponds to the thickness of the titanium film 308 of 30 nm. 5Ω / s
In the case where the thickness of the titanium nitride film 313 is small while the thickness of the titanium nitride film 313 is small, the titanium nitride film 313 is slightly etched during the etching, thereby damaging the titanium film 308 and reducing the layer resistance of the titanium silicide layer 311. 10Ω / s
Heet and get higher. The thickness of the titanium nitride film 313 is 1
When the thickness is as thick as 00 nm, the etching time becomes longer when the unreacted titanium film 308 and the titanium nitride film 313 shown in FIG.
Due to an increase in the time during which the layer 11 is exposed to the chemical, the titanium silicide layer 311 is slightly damaged, and the layer resistance of the titanium silicide layer 311 is increased to 8Ω / sheet. For this reason, the thickness of the titanium nitride film 313 is preferably set to 30 to 70 nm.

[0072]

According to the present invention, at the time of silicidation by the salicide process, a refractory metal film is formed on the entire surface of a semiconductor substrate, a refractory metal nitride film is formed thereon, and a non-silicide region is further formed thereon. A resist film is formed by removing the high-melting-point metal nitride film in the non-silicidized region using the resist film as a mask, and then, using the high-melting-point metal nitride film as a mask, removing the high-melting-point metal film in the non-silicided region. The semiconductor member in the portion where the high melting point metal film remains is silicided by heat treatment, the unreacted high melting point metal film and high melting point metal nitride film are removed, and the layer resistance of the silicified high melting point metal film is removed. Is reduced by heat treatment, so that the occurrence of silicidation at an arbitrary position on the semiconductor substrate can be completely suppressed. It can be as Ido reduction is not occur.
As a result, occurrence of defects due to electrostatic breakdown of the semiconductor device can be suppressed. Further, by not forming silicide on polycrystalline silicon which can be a resistance of the resistance portion, it is possible to supply a resistance portion having a layer resistance value of about 20 to 50 Ω / sheet and good uniformity. Further, since the etching selectivity between the semiconductor substrate, the silicon oxide film, and the polycrystalline silicon film in the step of removing the high melting point metal film is good, the electrical reliability of the gate oxide film in the transistor portion and the input / output portion is improved. Can be prevented from lowering. Further, in a region to be silicided, a high melting point metal film and a nitride film of the high melting point metal film are laminated, and an R for forming a silicide layer is formed.
Since the TA treatment is performed, a silicide layer can be formed more uniformly, and a rise in resistance can be suppressed particularly with a thin-line gate electrode of 1.0 μm or less. As described above, the present invention completely suppresses silicidation of a resistance portion without lowering the reliability and yield of a gate oxide film of a transistor, and forms a resistance element with good yield and uniformity. To ensure the integrity of salicide technology,
In addition, the silicidation of the input / output section is completely suppressed, the concentration of the electric field on the gate oxide film at the end of the gate electrode is reduced without silicidizing the source / drain electrodes of the input / output section, and the static electricity of the gate oxide film is reduced. In this case, it is possible to improve the resistance to destruction and improve the reliability and yield of the device.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a conventional example.

FIG. 2 is a process sectional view showing another conventional example.

FIG. 3 is a process cross-sectional view illustrating one embodiment.

FIG. 4 is a diagram showing a layer resistance of a silicide layer with respect to a line width of a gate electrode, showing a case where a titanium nitride film is present and a case without a titanium nitride film.

FIG. 5 is a diagram showing a layer resistance of a titanium silicide layer with respect to a line width of a gate electrode, in comparison with a case where arsenic is implanted into a silicide region and a case without arsenic implantation.

FIG. 6 shows that the RTA process in the silicidation
RTA treatment at 00 ° C for 60 seconds and RT at 700 ° C for 30 seconds
A and RT at 700 ° C. for 30 seconds
FIG. 9 is a diagram showing a layer resistance of a titanium silicide layer with respect to a line width of a gate electrode, in comparison with a case where only A processing is performed.

[Explanation of symbols]

 301 semiconductor substrate 302 element isolation region 303 gate oxide film 304a gate electrode 304b resistance portion 305 low concentration impurity diffusion layer region 306 gate sidewall insulating film 307 high concentration impurity diffusion layer region 308 titanium film 310 resist 311 titanium silicide layer 312 low resistance titanium Silicide layer 313 Titanium nitride film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB01 BB25 CC01 CC05 DD04 DD37 DD64 DD65 DD80 DD84 DD88 DD89 FF14 GG10 HH15 HH16 HH18 5F040 DA00 DA10 DA23 DB03 DB10 DC01 EC01 EC04 EC07 EC13 EF02 EF11 EH05 EK01 FA03 FA03 FA FB04 FC00 FC19 FC22

Claims (7)

[Claims] 1. A salicide in which silicidation is performed by including the following steps (A) to (H), and a resistance is reduced in a self-aligned manner on a gate electrode, a source electrode, and a drain electrode by a silicide film of a refractory metal. A method for manufacturing a semiconductor device including a MOS transistor having a structure. (A) a step of forming a refractory metal film on the entire surface of a semiconductor substrate;
(B) a step of forming a high-melting-point metal nitride film on the high-melting-point metal film; (C) a step of forming a resist film on the high-melting-point metal nitride film except for regions that are not to be silicided;
Removing the refractory metal nitride film in a region not to be silicided by using the resist film as a mask; (E) removing the resist film and then refractory metal in a region not to be silicided by using the refractory metal nitride film as a mask An etching step of removing the film; (F) a step of silicidizing the semiconductor member in a portion where the high melting point metal film remains by heat treatment; (G) an unreacted high melting point metal film and the high melting point metal nitride film. (H) a step of reducing the layer resistance of the silicidized high melting point metal film by heat treatment. 2. The method according to claim 1, wherein a titanium film is used as the refractory metal film and a titanium nitride film is used as the refractory metal nitride film. 3. The thickness of the titanium nitride film is 30 to 70 n.
3. The method of manufacturing a semiconductor device according to claim 2, wherein m is m. 4. The method according to claim 1, wherein the step of removing the refractory metal nitride film in a region not to be silicided by using the resist film as a mask is performed by a plasma treatment using a gas system containing fluorine, carbon and oxygen. 13. A method for manufacturing a semiconductor device according to 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the resist film is performed by a plasma treatment using a gas system containing oxygen and not containing fluorine. 6. The method according to claim 1, wherein the step of removing the refractory metal film in a region not to be silicided using the refractory metal nitride film as a mask is performed by a wet process using a chemical solution containing ammonia and hydrogen peroxide. 13. A method for manufacturing a semiconductor device according to 7. The composition of the refractory metal nitride film,
The volume content of nitrogen with respect to the high melting point metal is 0.4 to 0.4.
7. The method of manufacturing a semiconductor device according to claim 2, wherein