JP2000099361A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To increase the product yield of semiconductor integrated circuit devices such as microprocessors, which are becoming larger and more multifunctional, and to reduce the cost. SOLUTION: A primary cache memory FCACH and a code cache memory CCA each having a different function.
CH, a data cache memory DCACH, a microprocessor MP having a plurality of macro cells or cores such as a floating-point operation unit FPU formed on the same chip surface, a function control memory such as a flash memory, and a static type memory. A field control gate array including a gate control memory including a RAM or the like and a gate array receiving a holding signal for selectively stopping operation of a macro cell or a whole core or a part thereof in which a failure is detected; Function control signal F0
To F7, C0 to C3, D0 to D3 and a function control unit FCU for selectively forming FRUE are provided. Products are shipped as partially non-defective products such as processors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a microprocessor having a plurality of macrocells or cores having different functions, and is particularly effective when used for improving the product yield and reducing the cost. About technology.

[0002]

2. Description of the Related Art A plurality of functional blocks having different functions, such as a real number unit including an arithmetic logic unit, a floating point arithmetic unit, a cache memory, and the like, that is, a macrocell or a core obtained by integrating the same is integrated into one chip (semiconductor). There is a semiconductor integrated circuit device such as a microprocessor formed on a (substrate) surface.

[0003]

In recent years, the technology for miniaturization and high integration of semiconductor integrated circuits has been remarkable, and there has been a demand for even higher performance in microprocessors and the like, so that the scale and function have been increased. In the end. However, the increase in the chip area due to the increase in the scale and the number of functions of microprocessors and the like has a great effect on the product yield, and the product yield, the defect density, and the chip area are reduced by Y and Y, respectively.
When the D and A, becomes Y = e ^-DA, product yield, such as a microprocessor, reduced exponentially by receiving an increase in chip area. The same is true for each functional block in which macro cells and cores are advanced.In a conventional manufacturing method in which a chip in which an abnormality is detected in a part of macro cells or cores as a whole is defective, a microprocessor or the like is used. The product yield is remarkably reduced, which hinders cost reduction.

[0004] It is an object of the present invention to increase the yield of products such as microprocessors, which are becoming larger and more multifunctional, and to reduce the cost.

[0005] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of typical inventions disclosed in the present application. That is, a semiconductor integrated circuit device such as a microprocessor having a plurality of macro cells or cores having different functions formed on the same chip surface,
For example, a macro cell including a function control memory such as a flash memory and a field programmable gate array (FPGA) including a gate control memory such as a static RAM and a gate array receiving a signal held by the function control memory, Alternatively, a function control unit for selectively forming a function control signal for selectively stopping the operation of the entire core or a part thereof is provided.

According to the above means, the microprocessor or the like including the macrocell or core in which the fault is detected is partially non-defective while the operation of the entire macrocell or core in which some fault is detected is selectively stopped, or the operation of the macrocell or core is partially stopped. As the product can be shipped. As a result, the scale and the number of functions are increased, and the yield of products such as microprocessors including a large number of macrocells or cores can be increased, and the cost can be reduced.

[0008]

FIG. 1 is a block diagram showing an embodiment of a microprocessor MP (semiconductor integrated circuit device) to which the present invention is applied. First, an outline of the configuration and operation of the microprocessor MP of this embodiment and features thereof will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are known MOSFETs.
(Metal oxide semiconductor type field effect transistor. In this specification, MOSFET is collectively referred to as insulated gate type field effect transistor). It is formed.

In FIG. 1, a microprocessor MP of this embodiment includes a real number unit IU for performing various real number operations.
And a floating point arithmetic unit FPU for performing various floating point arithmetic operations, and a control unit CTLU for controlling and controlling the operation of each unit of the microprocessor MP including these arithmetic units. Further, a code cache memory CCACH for prefetching and holding a code, that is, an instruction for the control unit CTLU in a predetermined unit, and a data cache memory DCACH for prefetching and holding data for the real number unit IU and the floating point arithmetic unit FPU in a predetermined unit. And a primary cache memory FCACH for prefetching and holding codes or data for these cache memories in larger units.

The primary cache memory FCACH is connected to the code cache memory CCACH and the data cache memory DC via the internal bus IBUS in the upper part of the figure.
It is coupled to the ACH and, at the bottom of the figure, to the external bus EBUS via the bus unit BUSU. For example, a dynamic RA
A main memory (main storage device) composed of M (random access memory) and various input / output control devices are connected. Between the code cache memory CCACH and the control unit CTLU, a prefetch unit PFU for prefetching several codes corresponding to pipeline processing
And a decode unit DECU for decoding a code supplied to the control unit CTLU.

The control unit CTLU is further connected with a micro ROM μROM (read only memory) for decomposing a given code (instruction) into some basic processes and executing the code, and a code cache memory CCACH.
A code address translation buffer CTLB and a data address translation buffer DTLB for converting a logical address used for internal processing of the microprocessor MP into a physical address are provided in the data cache memory DCACH.
Are combined.

Here, the real number unit IU includes a real number register file IRF and a real number execution unit IEU,
The floating-point operation unit FPU includes a floating-point register file FRF, an adder ADD, a divider DIV, and a multiplier MUL. The input terminals of the real number register file IRF of the real number unit IU and the floating point register file FRF of the floating point arithmetic unit FPU are coupled to the data cache memory DCACH via the data bus DBUS, and the real number execution unit IEU of the real number unit IU is connected. Output terminals of the adder ADD, the divider DIV, and the multiplier MUL of the floating-point operation unit FPU are also coupled to the data cache memory DCACH via the data bus DBUS.

The control unit CTLU has a function of generating a code address including a branch decision, and the real number execution unit IEU of the real number unit IU has a function of generating a data address according to the operation result. As described above, these code addresses and data addresses are in the form of logical addresses, and the code cache memory CCACH and the data cache memory DCACH have a code address translation buffer CTLB or a data address translation buffer D in advance.
Based on the translation information written in the TLB, these logical addresses are translated into predetermined physical addresses.

Thus, the components constituting the microprocessor MP operate synchronously according to a clock signal (not shown), and constitute one computer system together with a main memory and an input / output device coupled to the external bus EBUS.

In this embodiment, relatively small functional blocks constituting the microprocessor MP, for example, micro ROM μROM, control unit CTLU, decode unit DECU, prefetch unit PF
U, code address translation buffer CTLB, data address translation buffer DTLB, and bus unit BUS
U and the like are designed in advance as macro cells and have relatively large-scale functional blocks, for example, a real number unit IU, a floating point arithmetic unit FPU, and a code cache memory C
The CACH, the data cache memory DCACH, the primary cache memory FCACH, and the like have different functions or are designed in advance as a core in which a plurality of macro cells divided as a memory bank or the like are combined.

By the way, in the microprocessor MP of this embodiment, a large number of functional blocks as described above are mounted on the same chip surface in accordance with the recent development of the miniaturization and high integration technology of the semiconductor integrated circuit. Therefore, the chip has a relatively large area. Also, for example, a primary cache memory FCAC constituting the microprocessor MP
H, the code cache memory CCACH and the data cache memory DCACH
P has a relatively large storage capacity in order to improve the performance of P, and includes a plurality of memory banks as described later.

As described above, the microprocessor MP
The product yield Y, then the defect density and the chip area and D and A, respectively, Y = e ^-DA next, decreases exponentially receives an increase in chip area due to scale and multifunctional . The same is true for each functional block in which macro cells and cores are being advanced.If the conventional manufacturing method in which the entire chip in which an abnormality is detected in a part of the macro cells or the core is defective is inherited as it is, the micro The product yield of the processor MP is significantly reduced, and its cost reduction is hindered.

To cope with this, the microprocessor MP of this embodiment is provided with a function control unit FCU, and function control signals generated by this function control unit FCU, for example, F0 to F7, C0 to C3 and D0. ＤD3 or FRUE, for example, the primary cache memory FCAC in which some failure is detected
H, the operations of the code cache memory CCACH and the data cache memory DCACH are selectively and partially stopped in units of memory banks, or the operation of the entire floating point arithmetic unit FPU is stopped. As a result, the microprocessor MP has a partially good product, that is, a relatively small-capacity primary cache memory FCACH, code cache memory CCACH, or data cache memory DCAC despite having some trouble.
The microprocessor is shipped as a microprocessor MP having a built-in H or not having a floating-point arithmetic function, whereby the product yield is increased and the cost is reduced.

The function control unit FCU includes a function control memory F composed of a flash memory as described later.
ROM, gate control memory SRAM consisting of static RAM, and gate array G receiving information held by the gate control memory SRAM
Field programmable gate array F including A
The PGA is provided, and information for managing the operation state of each function block is written into the function control memory FROM in response to the effective level of the internal control signal FW, which is the output signal of the control unit CTLU. Function control unit FC
The specific configuration of U will be described in detail below.

FIG. 2 shows the microprocessor MP of FIG.
Is a block diagram of an embodiment of the function control unit FCU included in the first embodiment. FIG. 3 also shows a primary cache memory FCA included in the microprocessor MP of FIG.
A block diagram of one embodiment of a CH is shown. With reference to these figures, the specific configuration and operation of the function control unit FCU and the primary cache memory FCACH included in the microprocessor MP of this embodiment and the features thereof will be described.

First, referring to FIG. 2, the function control unit FCU of the microprocessor MP of this embodiment includes, but is not limited to, a function control memory FROM composed of a nonvolatile memory such as a flash memory, and a static RAM.
And a field programmable gate array FPGA including a gate array GA for receiving information held by the gate control memory and a function control memory FROM and a gate control memory SR
A memory read / write control circuit FRWC for controlling data write / read operation to the AM is provided.

As will be described later, the function control memory FROM constituting the function control unit FCU receives a result of a probe test performed in a wafer state in a previous process of the microprocessor MP, and receives the results of the primary cache memory FCACH,
Inspection data on a memory bank in which an abnormality of the code cache memory CCACH and the data cache memory DCACH has been detected, and a floating point arithmetic unit FP
The overall functional test result of U is written. While these test data are written, the internal control signal FW, which is the output signal of the control unit CTLU, is kept at the valid level, that is, high level, and the write control is performed by the memory read / write control circuit FRWC.

The test data written in the function control memory FROM is read from the function control memory FROM under the control of the memory read / write control circuit FRWC when the power is turned on or at the time of reset.
The data is transferred to the gate control memory SRAM of the gate array FPGA. Then, according to the information held in the gate control memory SRAM, that is, the inspection data, the connection form of a number of logic gates constituting the gate array GA is switched,
As a result, the function control signals F0 to F7, C0 to C3, D0 to D3 as output signals of the function control unit FCU, and the combination of FRUE are selectively set to an effective level or an invalid level.

In the microprocessor MP of this embodiment, the primary cache memory FCACH is not particularly limited, but as shown in FIG. 3, eight memory banks FBANK0 to FBANK7 and the operation of these memory banks are controlled. Supervised cache control circuit FCCTL
And Among them, the cache control circuit FCCTL
Is supplied with an address signal of a predetermined bit and a control signal (not shown) via an internal bus IBUS,
A predetermined-bit address signal and a control signal (not shown) are supplied from the external bus EBUS via the bus unit BUSU, and 8-bit function control signals F0 to F7 are supplied from the function control unit FCU. Further, the internal bus IBU is connected to the memory banks FBANK0 to FBANK7.
A predetermined bit of data is supplied via S,
Data of a predetermined bit is supplied from the external bus EBUS via the bus unit BUSU, and a read / write signal R / W and an address signal AD are commonly supplied from the cache control circuit FCCTL, and a bank enable signal FBE is provided.
0 to FBE7 are supplied.

The cache control circuit FCCTL of the primary cache memory FCACH reads a code or data stored in an external main memory in a relatively large unit in accordance with a predetermined algorithm, and reads out the data in a memory bank FBAN.
Write and hold in K0 to FBANK7. In addition, the main memory access instructed by the control unit CTLU of the microprocessor MP is replaced by a condition of tag matching to assist high-speed processing. At this time, the cache control circuit FCCTL selectively sets the corresponding bank enable signals FBE0 to FBE7 to valid levels according to the function control signals F0 to F7 supplied from the function control unit FCU, and sets the memory banks FBANK0 to FBANK7.
Are selectively activated, in other words, the operations of the memory banks FBANK0 to FBANK7 are selectively stopped. At this time, the corresponding address of the primary cache memory FCACH is invalidated, and the output signal of the memory bank in the stopped state is in a so-called high impedance state.

Similarly, the code cache memory CCACH and the data cache memory DCACH of the microprocessor MP of this embodiment each have four memory banks, and the operations of these memory banks are output from the function control unit FCU. Function control signals C0 to C3
Alternatively, the bits are selectively stopped by setting the corresponding bits of D0 to D3 to the valid level. At this time, the code cache memory CCACH and the data cache memory D
The corresponding address of the CACH is invalidated, and all the output signals are brought into a high impedance state.

On the other hand, the microprocessor M of this embodiment
The P floating point unit FPU, as described above,
The floating-point register file FRF, the adder ADD, the divider DIV and the multiplier MUL constitute one functional block, and the operation is performed by a function control signal FR which is an output signal of the function control unit FCU.
The UE is selectively and totally shut down by setting it to a valid level. At this time, the floating-point operation unit FPU does not receive any command related to the floating-point operation, and its output signal is set to a high impedance state.

As described above, the microprocessor MP of this embodiment has its primary cache memory FCAC
H, a primary cache memory having a smaller capacity than a partially good product, that is, a completely good product, despite having a partial or total failure in the code cache memory CCACH, the data cache memory DCACH, or the floating point arithmetic unit FPU FCACH, code cache memory CCACH or data cache memory D
It is shipped as a microprocessor MP having a built-in CACH or not having a floating-point operation function, whereby the product yield is increased and the cost is reduced.

FIG. 4 shows the microprocessor MP of FIG.
A partial manufacturing process diagram of one embodiment is shown in FIG.
A processing flow diagram of one embodiment when the power is turned on is shown. With reference to these drawings, the outline of the manufacturing process of the microprocessor MP of this embodiment, the processing at the time of turning on the power, and the features thereof will be described.

First, in FIG. 4, the microprocessor MP undergoes a chemical process in a wafer state in a process prior to step ST1 to form elements constituting each functional block and to connect elements and between functional blocks. Will be Then, in a state in which each functional block, that is, the microprocessor MP can logically function, step ST2
, A probe test is performed, and a chip having a good result is subjected to non-defective processing in step ST53, and then the previous process is terminated.

On the other hand, the chip for which an abnormality has been detected in the probe test in step ST2 is determined in step ST3 as to whether the detected fault can be remedied.
For the unrepairable chip, the defective process is performed in step ST51, and then the previous process ends. If it is determined in step ST3 that the detected failure can be remedied, that is, the main functional block is in a state where it can function normally and the microprocessor MP is in a state where the product can be shipped as a partially non-defective product, In step ST4, the inspection data for stopping the operation of the corresponding function block entirely or partially is written in the function control memory FROM of the function control unit FCU.
The chip that has finished writing to the function control memory FROM,
After receiving the partial non-defective processing in step ST52, the previous process is ended. Needless to say, the function control memory FRO
The test data written in M is retained by the function control memory FROM as a non-volatile memory even after the power is turned off.

Next, as shown in FIG. 5, in the microprocessor MP which is incorporated as a package after being determined as a non-defective product or a partially non-defective product, and has become a component of the computer system together with the main memory and the like, as shown in FIG.
In response to power-on of T11, inspection data is read from the function control memory FROM of the function control unit FCU in step ST12, and written in the gate control memory SRAM of the field programmable gate array FPGA in step ST13.

Thus, a number of logic gates constituting the gate array GA are combined according to the information held in the gate control memory SRAM, and the function control signals F0 to F7,
C0 to C3, D0 to D3 and FRUE are selectively set to an effective level or an invalid level in a predetermined combination.
In step ST14, invalid blocks, that is, the primary cache memory FCACH and the code cache memory C
The operation of the CACH or the corresponding memory bank of the data cache memory DCACH is selectively stopped, or the operation of the entire floating point arithmetic unit FPU is stopped.

Therefore, the microprocessor MP
Even if any failure is included, the primary cache memory FCAC has a smaller capacity than a partially good product, that is, a completely good product.
H, functions as a microprocessor that incorporates the code cache memory CCACH or the data cache memory DCACH, or does not include the floating-point operation unit FPU, and starts normal processing in step ST15. As a result, the product yield as the microprocessor MP is improved, and the cost of the microprocessor MP and, consequently, the computer system including it are reduced.

The operational effects obtained from the above embodiment are as follows. (1) A semiconductor integrated circuit device such as a microprocessor in which a plurality of macro cells or cores having different functions are formed on the same chip surface, a function control memory such as a flash memory, and a static type memory. R
Field programmable memory including a gate control memory composed of an AM or the like and a gate array receiving a holding signal thereof.
A gate array, and a function control unit for selectively forming a function control signal for selectively stopping the operation of the macro cell or the core in which the failure is detected or a part thereof is provided. In a state where the operation of the macro cell or the core or a part of the macro cell or the part thereof is selectively stopped, a product such as a microprocessor can be shipped as a partially good product.

(2) In the above item (1), the present invention is applied to, for example, a microprocessor provided with a floating-point arithmetic unit, and the operation of the floating-point arithmetic unit in which a failure is detected is stopped, so that the microprocessor is stopped. Etc. can be shipped as a partially good product having no floating point function. (3) In the above item (1), by applying the present invention to a microprocessor having a primary cache memory, a code cache memory, or a data cache memory including a plurality of memory banks, for example, the failure of these cache memories can be prevented. By partially or entirely stopping the operation of the detected memory bank, the microprocessor or the like can be shipped as a partially non-defective product having a relatively small-capacity primary cache memory, code cache memory or data cache memory. The effect that it can be obtained is obtained.

(4) According to the above items (1) to (3), the scale and the number of functions are increased, the product yield of microprocessors including a large number of macrocells or cores is increased, and the cost is reduced. The effect that it can be obtained is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the microprocessor MP can include other various functional blocks, and its block configuration, bus configuration, and the like can take various embodiments without being limited by the present embodiment. The function control memory FROM of the function control unit FCU is, for example, an EEPROM.
M (electrically erasable / programmable read-only memory) or a fuse that is selectively blown, and these nonvolatile memories and function stop circuits may be provided separately in each function block. Good. Among the function control signals which are output signals of the function control unit FCU,
For example, a signal for stopping the operation of the primary cache memory FCACH, the code cache memory CCACH or the data cache memory DCACH as a whole may be provided, and the type and combination of the functional blocks selectively stopped can be set arbitrarily. .

In FIG. 2, a function control memory FROM
Can be replaced with, for example, an EEPROM or a fuse that is selectively blown, as described above, or these nonvolatile memories and function stop circuits may be provided separately in each function block. Further, the field programmable gate array FPGA can be replaced with, for example, an antifuse. As described above, the function control signal which is the output signal of the gate array GA of the function control unit FCU includes, for example, the primary cache memory FCAC.
H, a signal for stopping the operation of the code cache memory CCACH or the data cache memory DCACH as a whole may be provided.

In FIG. 3, the primary cache memory FC
The number of memory banks provided in the ACH can be arbitrarily set, and various block configurations and bus configurations of the primary cache memory FCACH can be considered. FIG.
5 and FIG. 5, the manufacturing process of the microprocessor MP and the processing flow at the time of turning on the power are only examples, and do not affect the gist of the present invention.

In the above description, the case where the invention made by the present inventor is mainly applied to a microprocessor which is a field of application as a background has been described. However, the present invention is not limited to this. ASIC with logic integrated circuit mounted on the same chip surface
The present invention can also be applied to (application-specific integrated circuit devices) and system LSIs (large-scale integrated circuit devices) such as single-chip microcomputers. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device in which a plurality of functional blocks having at least different functions are mounted on the same chip surface, and a device or a system including such a semiconductor integrated circuit device.

[0042]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor integrated circuit device such as a microprocessor in which a plurality of functional blocks such as a plurality of macro cells or cores having different functions are formed on the same chip surface, for example, a function control memory such as a flash memory, And a field programmable gate array including a gate array receiving a signal held by the gate control memory such as a type RAM, etc., for selectively stopping the operation of a macrocell or a core or a part thereof in which a failure is detected. By providing a function control unit that selectively forms a function control signal,
In a state where the operation of a macro cell or a core in which a failure is detected or a part thereof is selectively stopped, a microprocessor or the like including the macro cell or the core in which the failure is detected can be shipped as a partially good product. As a result, large-scale and multi-functionalization has progressed, and the product yield of microprocessors including a large number of macrocells or cores has been increased,
The cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a microprocessor to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a function control unit included in the microprocessor of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of a primary cache memory included in the microprocessor of FIG. 1;

FIG. 4 is a partial manufacturing process diagram showing one embodiment of the microprocessor of FIG. 1;

FIG. 5 is a partial processing flowchart showing one embodiment when the power of the microprocessor of FIG. 1 is turned on.

[Explanation of symbols]

MP: microprocessor, EBUS: external bus,
BUSU: Bus unit, FCACH: Primary cache memory, IBUS: Internal bus, CCACH: Code cache memory, DCACH: Data cache memory, CTLB: Code address translation buffer,
DTLB… Data address translation buffer, PFU…
Prefetch unit, DECU ... Decode unit, CTLU ... Control unit, μROM ... Micro ROM, DBUS ... Data bus, IU ... Real number unit, IRF ... Real number register file, IEU ... Real number execution unit, FPU ... Floating point unit, F
RF: floating point register file, ADD: adder, DIV: divider, MUL: multiplier, FW: write control signal, FCU: function control unit, FRU
E, C0-C3, D0-D3, F0-F3 ... Function control signals. FRWC: Memory read / write control circuit, FR
OM: Function control memory, SRAM: Gate control memory, GA: Gate array. FCCTL Cache control circuit, FBANK0 to FBANK7 Memory bank, R / W Read / write signal, AD Address signal, FBE0 to FBE7 Bank enable signal. S
T1 to ST6, ST51 to ST53, ST11 to ST1
5 Steps.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kenichi Kikushima 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Fumio Otsuka 6-16 Shinmachi, Ome-shi, Tokyo (3) Inside the Device Development Center of Hitachi, Ltd. (72) Inventor Bungo Bungo 6-16-16, Shinmachi, Ome-shi, Tokyo 3) Inside the Device Development Center of Hitachi, Ltd. (72) Katsuhiko Ichinose Shinmachiroku, Ome-shi, Tokyo In the Device Development Center, Hitachi, Ltd. at 3-16 Chome (72) Inventor Masaya Iida In the Device Development Center, Hitachi, Ltd. at 6-16-16 Shinmachi, Ome-shi, Tokyo (72) Inventor Morio Nakamura, Ome-shi, Tokyo 6-16 Shinmachi 3 Device Development Center Hitachi, Ltd.

Claims (5)

[Claims] 1. A plurality of function blocks each having a different function, and a function control unit capable of selectively stopping operation of a function block or a part thereof which has become inoperable due to some failure among the plurality of function blocks. A semiconductor integrated circuit device comprising: 2. The floating-point arithmetic unit according to claim 1, wherein the semiconductor integrated circuit device is a microprocessor including a floating-point arithmetic unit, and the functional block of which operation is selectively stopped is the floating-point arithmetic unit. A semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a microprocessor including a cache memory including a plurality of memory banks, and a part of the operation is selectively stopped. A semiconductor integrated circuit device, wherein the functional block is the cache memory, and its operation is selectively stopped in units of the memory bank. 4. The semiconductor integrated circuit device according to claim 3, wherein said cache memory includes a primary cache memory and a secondary cache memory including a code cache memory and a data cache memory. 5. The function control unit according to claim 1, wherein the function control unit includes a function control memory using a flash memory as a basic element and a gate control using a static RAM as a basic element. A field programmable gate array that includes a memory and a gate array that receives the holding signal thereof, and that generates a function control signal for selectively stopping the operation of the functional block or a part thereof. Semiconductor integrated circuit device.