JP2000098428A - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of failures caused by aluminum wirings by processing a wiring end face formed by the sheath wiring material of a gate line and/or a data line into one body shape and specifying the angle which is produced between a wiring end face part and a substrate and in a side including the wiring. SOLUTION: A gate line(GL) 103 consists of a core wiring material made of aluminum or essentially composed of aluminum and a sheath wiring material formed so as to surround the lower, side and upper faces of the core wiring material by a material different from the core wiring material. The wiring end face formed by the sheath wiring material is worked into one body shape so that the angle which is produced between the wiring end face and a substrate and in a side including the wiring is less than 90. The data line(DL) 112 is formed on a gate insulating film (GI) 104 on a transparent glass substrate (SUB1) 101 and also formed on an i-type semiconductor layer (AS) 111 and an N-type semiconductor layer (d0) 110 on the gate insulating film (GI) 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix drive type liquid crystal display device using thin film transistors (TFTs) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a TFT used in a conventional active matrix type liquid crystal display device, a gate electrode connected to a scanning signal wiring (gate line) on an insulating transparent substrate, a gate insulating film on the gate electrode, and a gate insulating film on the gate electrode. Semiconductor layer,
On the semiconductor layer, there are a drain electrode connected to a data signal wiring (data line), and a source electrode in the same layer as the drain electrode. A transparent pixel electrode is connected to the source electrode, and the drain electrode (data line ) Is supplied with a video signal voltage. A TFT structure in which a gate electrode is first formed on a substrate is generally called an inverted staggered structure. Japanese Patent Application Laid-Open No. 2-48639 is known as such a TFT.

[0003] Such a liquid crystal display device is mainly applied to a notebook personal computer, but in recent years, the screen has been enlarged and the definition has been advanced, and it has been used as a desktop monitor. That is, a liquid crystal display device having a screen with a diagonal size of 15 inches or more has been developed. However, when the screen size is large and the definition is high, the wiring becomes long and thin, so that a signal delay due to a rise in resistance causes a problem of deterioration in image quality. Therefore, a low-resistance material such as aluminum is required for the wiring material. Regarding the reduction in the resistance of such wiring, see SID95 Digest, page 11 (SI
D95 DIGEST p.11).

[0004]

In order to use aluminum for a TFT panel wiring, particularly for a gate line, it is necessary to prevent the occurrence of hillocks caused by the low heat resistance of aluminum. For this purpose, Ti, Cu,
There is a method of adding a second element such as Pd, Ta, Zr, and Nd. However, although this method can suppress the generation of hillocks as compared with the case where the second element is not added, it is not perfect, and causes a problem that the specific resistance increases when the added amount is increased to promote the effect. The hillock is at the intersection of the gate line and the data line (100 per panel).
If it occurs on the order of ten thousand, an electrical short will occur there, causing line defect failure. For this reason, various measures have been devised as described in the above literature.
The countermeasures are shown in FIGS. FIG. 3 shows an aluminum or aluminum alloy wiring provided with a high melting point material underlayer such as Cr or Mo. The causes of hillocks are the difference in the coefficient of thermal expansion between aluminum or aluminum alloy and the glass of the substrate,
This is a compressive stress generated in the aluminum or aluminum alloy film due to the thermal history in the manufacturing process. In order to release the compressive stress, atom migration occurs, and a projection called a hillock is generated. In the method of FIG. 3, a buffer layer is inserted between an aluminum or aluminum alloy film and a glass substrate to reduce generated thermal stress. But,
With this method, it was difficult to completely prevent the occurrence of hillocks. Also, if this wiring is to be manufactured by one photolithography, when the base layer is etched after etching the aluminum or aluminum alloy film, an overhang of the aluminum or aluminum alloy film is formed as shown in FIG. The coverage of an insulating film to be formed is deteriorated. Therefore, an electrical short is generated with the data line thereon. Further, in order to form an electrical contact between the wiring and the ITO film of the connection terminal, since the contact resistance between the aluminum or aluminum alloy film and the ITO is extremely high, the aluminum or aluminum alloy film is etched again or the aluminum or aluminum alloy film is etched. It is also problematic to require additional processing, such as depositing another contact metal film on the alloy film. FIG.
Is obtained by laminating a high melting point material layer such as Cr or Mo on an aluminum or aluminum alloy film. Since an attempt is made to form by one photolithography, the end of the aluminum or aluminum alloy film cannot be covered. Therefore, there is a problem that hillocks (side hillocks) are generated from this end face. Unless strict measures such as appropriately selecting a material to be formed thereon and optimizing etching conditions are taken, an overhang is formed in an upper layer, or a taper is formed in an end surface of an aluminum or aluminum alloy film. (There may be a reverse taper), which deteriorates the coverage of the insulating film thereon. Fig. 5 shows aluminum or aluminum alloy wiring (core wiring)
Is coated with a high melting point material such as Cr or Mo. The problem with this method is that if a taper (even a part) cannot be formed at the end of the aluminum or aluminum alloy film, the coverage of the outer wiring deteriorates and side hillocks generated from the end surface of the aluminum or aluminum alloy film cannot be suppressed. And it is difficult to form a taper at the end of the wiring to be covered. In this method, the number of times of photolithography is two. FIG. 6 shows a method of coating an aluminum or aluminum alloy film wiring with an alumina film by anodization. The problem with this method is that it is necessary to draw out the electrode terminal for anodic oxidation to the edge of the substrate, and to prevent the alumina film from being deposited on the terminal part, that is, use a photoresist mask so that the chemical solution does not adhere. In order to form it, another photolithography step is required in addition to the wiring. Also, as described with reference to FIG.
It is difficult to make contact with the O terminal.

An object of the present invention is to realize a liquid crystal display device to which a large screen and aluminum wiring effective for high definition are applied. More specifically, it is an object of the present invention to provide a structure and a manufacturing method of an active matrix type liquid crystal display device which prevents a defect caused by aluminum wiring and has a high manufacturing yield.

[0006]

In order to achieve the above object, the present invention provides a plurality of gate lines, a plurality of data lines formed so as to intersect the plurality of gate lines, A substrate having a thin film transistor formed near an intersection of data lines, a pixel electrode connected to the thin film transistor, a substrate facing the substrate, and a liquid crystal layer sandwiched between the substrate and the substrate facing the substrate A liquid crystal display device comprising:
At least one of the gate line and the data line is made of aluminum or a core wiring material containing aluminum as a main component, and a lower surface, a side surface, and an upper surface of the core wiring material different from the core wiring material. And a wiring end face formed of the outer wiring material is processed into an integral shape, and a side of the wiring end face portion and the substrate that includes wiring is formed. The angle between them is smaller than 90 degrees.

The present invention further comprises a first outer wiring material thin film forming a part of the gate line of the thin film transistor on the substrate, and a core wiring material thin film forming a part of the gate line. A first deposition means for depositing;
First processing means for processing only the core wiring material thin film into a gate line pattern by photolithography and etching, and the first outer wiring material thin film, and the core wiring material thin film formed thereon. Second depositing means for depositing a second outer wiring material thin film forming a part of the gate line on a gate line pattern, the first outer wiring material thin film and the second outer wiring material thin film And, by photolithography and etching,
And a second forming means for completing the laminated gate line pattern by processing the gate wiring pattern slightly wider than the gate line pattern of the core wiring material thin film.

[0008]

(Embodiment 1) FIG. 7 is a perspective view of a part of a manufactured liquid crystal display device. FIG. 8 shows FIG.
3 is a diagram showing a plane pattern of each layer constituting the TFT substrate in FIG. FIG. 1 is a sectional view taken along the line AA 'of FIG.

As shown in FIG. 7, a liquid crystal display device has a thin film transistor 303 and a transparent conductive film ITO1 (indium-tin-oxide; abbreviation for indium-tin-oxide) 105 on one surface of a transparent glass substrate (SUB1) 101, A transparent conductive film (IT) is formed on one surface of a TFT substrate on which various wirings and the like are formed and another transparent glass substrate (SUB2) 102.
O2) 106, a color film (FIL) 305, and the like are formed on a counter substrate, and a liquid crystal layer (LC) 304 is filled in the gap between the two substrates. In addition,
FIG. 1 shows only the glass substrate 101 for simplicity.

An image signal voltage is applied between the transparent conductive film (ITO 1) 105 and the transparent conductive film (ITO 2) 106 to control the electro-optical state of the liquid crystal layer (LC) 304 between the two electrodes and to transmit light. The state is changed and a predetermined image is displayed.

A backlight is provided on the counter substrate side or the TFT substrate side of the liquid crystal panel, and light transmitted through the pixel portion of the liquid crystal panel is observed from the side opposite to the backlight. << TFT Substrate >> Next, referring to FIG. 1, FIG. 7 and FIG.
The structure of the substrate will be described in detail. On the surface of the TFT substrate, a plurality of parallel gate lines (scanning signal lines or horizontal signal lines) GL103 and a plurality of parallel data lines (video signal lines or vertical signal lines) formed so as to intersect with the gate lines 103 are formed. Line) DL112 is provided. A region surrounded by two adjacent gate lines (GL) 103 and two adjacent data lines (DL) 112 is a pixel region, and a transparent conductive film (ITO1) 105 is formed almost entirely on this region. ing. This region is also called a (transparent) pixel electrode. Thin film transistor 303 as a switching element (region indicated by broken line in FIG. 8)
Are formed on the convex portion of the gate line 103 corresponding to each pixel electrode (in FIG. 8, the upward convex portion), and the source electrode (SD1) 109 is connected to the pixel electrode. The scanning voltage applied to the gate line (GL) 103 is applied to the gate electrode of the TFT constituted by a part of the gate line 103 to turn on the TFT, and the image supplied to the data line (DL) 112 at this time. A signal is transmitted through the transparent conductive film (ITO1) 10 through the source electrode (SD1) 109.
5 is written.

{Thin Film Transistor TFT} FIGS. 1 and 8
As shown in FIG. 1, a gate line (GL) 103 made of a conductive film g1 is formed on a transparent glass substrate (SUB1) 101, and an insulating film, a semiconductor layer and the like are formed thereon as described later, and a thin film transistor (TFT) is formed. ) 303 is constituted. The thin film transistor 303 has a gate line (G
L) When a bias voltage is applied to the channel 103, the channel resistance between the source and the drain (data line DL) is reduced, and when the bias voltage is set to zero, the channel resistance is increased. A gate insulating film (GI) 104 made of silicon nitride is provided on a gate electrode which is a part of the gate line (GL) 103, and an i-type semiconductor made of amorphous silicon to which an impurity is not intentionally added is provided thereon. A layer (AS) 111 and an N-type semiconductor layer (d0) 110 made of amorphous silicon doped with impurities are formed. This i
The semiconductor layer (AS) 111 forms an active layer of the thin film transistor 303. Further, a source electrode (SD
1) 109, drain electrode (data line D in the embodiment)
Part of L forms a drain electrode. Hereinafter, the drain electrode is referred to as a data line DL unless otherwise specified. ) To form a thin film transistor 303.

As the gate insulating film (GI) 104, for example, a silicon nitride film formed by plasma CVD is selected, and has a thickness of 200 to 500 nm (in this embodiment, 3
(About 50 nm).

The i-type semiconductor layer (AS) 111 has a thickness of 50 to 2
It is formed with a thickness of 50 nm (about 200 nm in this embodiment). The N-type semiconductor layer (d0) 110 is formed to be thin with a thickness of 50 nm or less, and the i-type semiconductor layer (AS) 111
It is provided for forming ohmic contacts between the gate electrode and the source and drain electrodes, and is formed of an amorphous silicon semiconductor doped with phosphorus (P).

The names of the source electrode and the drain electrode are originally determined by the polarity of the bias between them. In the liquid crystal display device of the present invention, the source electrode and the drain electrode are switched because their polarities are inverted during operation. However, in the following description, one is fixedly called the source electrode and the other is fixedly called the drain electrode for convenience.

{Source Electrode} As shown in FIG. 1, the source electrode (SD1) 109 is formed on the N-type semiconductor layer (d0) 110 and is constituted by the first conductive film d1. The first conductive film d1 has a thickness of 60 to 300 nm (in this embodiment,
(About 200 nm).

As shown in FIGS. 1 and 8, the source electrode (SD1) 109 includes an i-type semiconductor layer (AS) 111 and an N-type semiconductor layer (d0) 110 formed inside one pixel region.
Formed on top. Further, the transparent conductive layer (ITO1) 105 formed of the second conductive film d2 on the upper side thereof is
Source electrode (SD1) 1 through contact hole (CN) 107 opened in protective insulating film (PSV1) 108
09 and is formed on the protective insulating film (PSV1) 108.

{Pixel Electrode} The pixel electrode is a transparent conductive film (ITO1) 105 such as indium tin oxide which is the second conductive film d2.
Respectively. This is the thin film transistor 30
3 is connected to the source electrode (SD1) 109. The transparent conductive film (ITO1) 105 is formed by a sputtering method and has a thickness of 30 to 300 nm (1 in this embodiment).
About 40 nm).

{Gate Line GL} As shown in FIGS. 1 and 2, the gate line (GL) 103 is made of aluminum or a core wiring material 201 containing aluminum as a main component.
And outer wiring materials 202 and 203 formed so as to surround the lower surface, side surfaces, and upper surface of the core wiring material with a material different from the core wiring material. The end face of the formed wiring is processed into an integral shape, and the angle between the end face of the wiring and the substrate on the side including the wiring is smaller than 90 degrees. In this embodiment, Ti (titanium) and Ta (tantalum) are added to Al (aluminum) as the core wiring material 201, respectively.
wt%, Cr as the outer wiring material 202
(Chromium), and a material in which Mo (molybdenum) was added to Cr at 50 wt% was used as Cr. The thicknesses of the core wiring material 201 and the outer wiring materials 202 and 203 were 300 nm, 100 nm and 30 nm, respectively. With such a configuration, since the taper of the Al end portion 204 and the Cr end portion 205 is formed, the coverage of the gate insulating film GI formed thereon is improved, and the data line (DL) crossing over the gate insulating film GI is improved. ) 112 can be prevented from breaking.

{Data Line DL} As shown in FIGS. 1 and 8, the data line (DL) 112 is formed of a gate insulating film (GI) 104 on a transparent glass substrate (SUB1) 101.
And on the i-type semiconductor layer (AS) 111 and the N-type semiconductor layer (d0) 110 thereabove. In the present embodiment, the same laminated film of Cr and CrMo alloy as used for the outer wiring material of the gate line (GL) 103 was used. The film thickness is 200 nm in total, and the lower Cr 170 nm,
The upper CrMo alloy was 30 nm. Data line 11
As the second structure, the same configuration as the gate line 112 was examined separately, but it was confirmed that no disconnection occurred.

{Storage capacitance Cadd, parasitic capacitance Cgs} Storage capacitance (Cadd) 401 is a gate line (G
L) A gate line (GL) 10 in the preceding stage different from 103
3 and a gate insulating film (GI) 104 and a protective insulating film (PS)
V1) Transparent conductive film (ITO1) sandwiching 108 laminated film
It is composed of the capacity of the crossing area with 105. The storage capacitor (Cadd) 401 is used to reduce the capacitance of the liquid crystal layer (LC) 304 or to reduce Tc.
It has a function of preventing a voltage drop when the FT is off.

The parasitic capacitance (Cgs) 403 is a lamination of a gate line (GL) 103 of a self-stage which is a gate line (GL) 103 on which a TFT is formed, a gate insulating film (GI) 104 and a protective insulating film (PSV1) 108. It is composed of the capacitance of the intersecting region with the transparent conductive film (ITO1) 105 across the film. The (Cadd) 401 and (Cgs) 403 are set so that the second conductive film d2 is at a predetermined interval on the gate line (GL) 103 as shown in FIG.

As described above, by providing the parasitic capacitance (Cgs) 403, the gate line (Ggs) is compared with a structure in which the gate line (GL) 103 of the own stage and the second conductive film d2 are not overlapped.
L) It is not necessary to cover the gap between the transparent conductive film (ITO1) 105 and the black conductive film (ITO1) 105 with the black matrix BM formed on the opposing substrate OPSUB, and the aperture ratio is improved.

{Light shielding electrode SKD} Light shielding electrode (SKD) 4
02 is a transparent glass substrate (SUB1) 101 of the TFT substrate
A conductive film g1 forming a gate line (GL) 103 thereon
Is formed. The light-shielding electrode (SKD) 402 has a data line (DL) 112 and a transparent conductive film (ITO) along a data line (DL) 112 as shown in FIG.
1) It is formed so as to overlap with 105.
On the other hand, in terms of the cross-sectional structure, the light-shielding electrode (SKD) 402 is connected to the data line (DL) 112 and the gate insulating film (GI) 10.
4 for insulation. In addition, the transparent conductive film (I
The TO1) 105 and the light-shielding electrode (SKD) 402 are a gate insulating film (GI) 104 and a protective insulating film (PSV1) 108
Is insulated and separated.

In this embodiment, in order to improve the aperture ratio, the transparent conductive film 105, the light shielding electrode 402, and the transparent conductive film 10
5 and the gate line 103 are provided in an overlapping manner. However, since these overlappings increase the wiring capacity, it is needless to say that the driving ability, that is, the image quality is affected. When the image quality is prioritized, the aperture ratio may be slightly reduced.

<< Process for Fabrication >> First, the process for fabricating the wiring structure of the liquid crystal display device of the present invention will be described with reference to FIG. On the cleaned glass substrate 101, a substrate temperature of 120 was applied using a single-wafer DC magnetron sputtering apparatus.
Cr film 502 having a thickness of 100 nm at a temperature of 0.3 ° C. and a pressure of 0.3 Pa.
After being deposited, it was transferred to another chamber and an Al-Ti-Ta film 501 having a thickness of 300 nm was deposited under the same conditions as Cr. The addition amounts of Ti and Ta are each about 0.5 wt%. Next, a wiring pattern was formed with a photoresist (PRES1) 503 by ordinary photolithography, and then the Al—Ti—Ta film was etched by a wet etching method. For the etching, a mixed aqueous solution of phosphoric acid, acetic acid and nitric acid kept at 40 ° C. was used. Although simplified in the figure, the end face of the Al—Ti—Ta film 501 has a taper of about 50 degrees at this time. Next, the photoresist (PRES1) 503 is peeled off, and the single-wafer DC is again formed.
Substrate temperature 12 using magnetron sputtering equipment
Cr-50w having a thickness of 30 nm at 0 ° C. and a pressure of 0.3 Pa
A t% Mo alloy film 505 was deposited. Subsequently, a wiring pattern (a little wider than the photoresist PRES1) was formed with a photoresist (PRES2) 504, and subsequently, a multilayer film of a Cr-50 wt% Mo alloy and Cr was collectively etched by a wet etching method. For the etching, a 15 wt% ceric ammonium nitrate aqueous solution maintained at 30 ° C. was used. As a result, a taper of about 45 degrees was formed on the end face of the Cr film. Cr-50wt%
The end face of the Mo alloy is almost perpendicular to the substrate,
Since the thickness is as thin as nm, there is no adverse effect on the coverage of the film formed thereon. Thereafter, the photoresist (PRES2) 504 is peeled off and the gate line (GL) 1 is removed.
03 was completed. Although not shown in the figure, FIG.
The light-shielding electrode (SKD) 402 is manufactured by the same process as the gate line (GL) 103 described above, but it is not necessary to have a low resistance.
All of the a film 501 was removed by etching.

Next, a method for manufacturing a TFT substrate will be described with reference to FIGS. First, a gate line (GL) 103 was formed by the method described with reference to FIG. 9 (FIG. 10A).
In the following, the description of photoresist removal after etching is omitted. Next, the SiN film as the gate insulating film (GI) 104, a-
A three-layer film of the Si film AS and the n ⁺ .a-Si film d0 was continuously deposited by sequentially moving the three chambers. The film thickness was 350 nm, 200 nm, and 30 nm in order from the bottom. Further, using a single-wafer DC magnetron sputtering apparatus, a Cr film having a thickness of 170 nm and a Cr-50w film having a thickness of 30 nm thereon were formed at a substrate temperature of 120 ° C. and a pressure of 0.3 Pa.
A laminated film composed of a t% Mo alloy film was deposited (FIG. 10).
(B)). A photoresist pattern is formed thereon, and the data line (DL) 112 is first processed by wet etching. Then, the n ⁺ .a-Si films d0 and a-Si are formed by dry etching using a mixed gas of SF ₆ and HCl. Membrane AS
Was partially processed (FIG. 10 (C)). For wet etching, the same ceric ammonium nitrate aqueous solution as described above was used. Thereby, the data line (DL) 112
A good tapered shape was obtained on the end face of the. In addition, the channel portion of the TFT is formed by the dry etching. Next, TF is applied by another photoresist pattern.
The island pattern of the i-type semiconductor layer AS of the a-Si film serving as T was processed by a dry etching method using SF ₆ gas (FIG. 10D). An SiN film, which is a protective insulating film (PSV) 108, was formed thereon by single-wafer plasma CVD. The film thickness was 400 nm. A photoresist pattern was formed on this protective film, and the contact holes CN were processed by a dry etching method using SF ₆ gas (FIG. 10).
(E)). Next, a transparent conductive film (ITO) 105 was deposited to a thickness of 140 nm using a single-wafer DC magnetron sputtering apparatus at a substrate temperature of 210 ° C. and a pressure of 0.5 Pa of argon gas to which 5% oxygen was added. A photoresist pattern was formed thereon, and the transparent conductive film pattern was processed by wet etching (FIG. 10F). An HBr solution kept at 40 ° C. was used for wet etching. Thus, a TFT substrate was completed.

(Embodiment 2) In the previous embodiment, FIG.
As shown in FIG. 5, a metal film to be the data line (DL) 112 was directly deposited on the three CVD films, but before depositing the metal film, the i-type semiconductor layer AS of a-Si film, n ⁺ .a- The laminated film of the N-type semiconductor layer d0 of the Si film is dry etched to
The island pattern of the T part is prepared, and then the data line (D
L) A TFT substrate was produced by a method of forming 112. In the former, three CVD films exist in all regions below the data line (DL) 112 in the former, whereas in the latter, the data lines (DL) 11 in regions other than the TFT portion exist in the latter.
2 can be a gate insulating film (GI) 104. In the former case, the n ⁺ .a-Si film d0 does not come into contact with the photoresist or the stripping solution, so that there is a feature that the contact characteristics of the TFT hardly deteriorate.

(Example 3) TF produced by the method described above
When the disconnection inspection of the T substrate was performed, the gate lines 103,
It was found that no disconnection occurred in any of the data lines 112. In the case of a TFT substrate having a gate line cross-sectional shape shown in FIG. 5 manufactured as a comparison, about 10% of data line disconnection occurred.

As described above, according to the present invention, the gate line 103 can be provided with a taper having a good shape, so that disconnection failure can be prevented, and the cost of the liquid crystal display device can be reduced. In addition, since the gate line has a three-layer structure, the gate line 103 itself is hard to be disconnected. Although the gate line structure has excellent characteristics as described above, it can be manufactured by two photolithography operations, and the additional effect that the process cost is not increased is also provided. Of course, since aluminum is used for the wiring, the resistance is low, the distortion of the electric signal is small, and the image quality is not deteriorated even on a large screen display.

In the above embodiment, C is used as the second shell material.
An alloy in which Mo was added to r was applied. As a result of examining the material added to Cr, it was confirmed that even if W was added instead of Mo, a good taper could be formed on the wiring end face. Furthermore, during the search for this material, the following was clarified. That is, as a result of measuring the immersion potential (electrode potential) in an aqueous ceric ammonium nitrate solution as an etching solution, it is found that the lower immersion potential of the second outer material is lower than the immersion potential of Cr to achieve a favorable tapered shape. I found that it was a condition. Here, the standard electrode at the time of measuring the immersion potential is Ag-AgCl (saturated KCl).

In the embodiment, A is used as a core wiring material.
Although an l-Ti-Ta alloy was used, Al was Ta, Ti, C
A material containing at least one of u, Si, B, Y, Zr, Pd, Hf, La, and a lanthanoid element having atomic numbers 58 to 71 can be used. It is also possible to use Al to which nothing is added. In this case, the specific resistance is 3μΩ
Since it can be reduced to about cm, there is a feature that the film thickness can be reduced to achieve the same wiring resistance.

[0033]

According to the present invention, it is possible to prevent the occurrence of defects due to aluminum wiring,
An active matrix liquid crystal display device having a high production yield can be provided.

Further, a large-screen and high-definition liquid crystal display device can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a cross section of a TFT of a liquid crystal display device according to the present invention.

FIG. 2 is a diagram showing a wiring cross section of the liquid crystal display device according to the present invention.

FIG. 3 is a diagram showing one embodiment of a wiring cross-sectional structure of a conventional liquid crystal display device.

FIG. 4 is a diagram showing another embodiment of a wiring cross-sectional structure of a conventional liquid crystal display device.

FIG. 5 is a view showing another embodiment of a wiring cross-sectional structure of a conventional liquid crystal display device.

FIG. 6 is a diagram showing another embodiment of a wiring cross-sectional structure of a conventional liquid crystal display device.

FIG. 7 is a diagram showing one embodiment of a liquid crystal display device according to the present invention.

FIG. 8 is a diagram showing a plane example of a pixel portion of the liquid crystal display device according to the present invention.

FIG. 9 is a diagram illustrating a process for manufacturing a wiring structure of a liquid crystal display device according to the present invention.

FIG. 10 is a diagram showing a process for manufacturing a TFT substrate of a liquid crystal display device according to the present invention.

[Explanation of symbols]

101, 102... Glass substrates (SUB1, SUB2),
103: gate line (GL), 104: gate insulating film (GI), 105, 106: transparent conductive film (ITO1, I
TO2), 107 ... contact hole (CN), 108
... Protective insulating film (PSV1), 109 ... Source electrode (SD
(D1)), 110... N-type semiconductor layer (d0), 111.
Type semiconductor layer (AS), 112 ... data line (DL),
201: wiring material, 202, 203: outer wiring material, 2
04: Al end, 205: Cr end, 206: Cr-M
o Edges, 301, 302 ... Polarizing plates (POL1, POL
2), 303 ... Thin film transistor (TFT), 304 ...
Liquid crystal layer (LC), 305 ... color filter (FIL),
401: storage capacitance (Cadd), 402: light shielding electrode (SK)
D), 403: parasitic capacitance (Cgs), 501: Al-Ti
-Ta film, 502 ... Cr film, 503,504 ... Photoresist (PRES1, PRES2), 505 ... Cr-Mo
Alloy film.

Continued on the front page (72) Inventor Yuichi Harano 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratory Co., Ltd. Within the Electronic Devices Division (72) Inventor Kazumi Fujii 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term (reference) 2H092 JA26 JA29 JA33 JA35 JA38 JA39 JA40 JA42 JA43 JA44 JA46 JB13 JB23 JB27 JB32 JB33 JB36 JB38 JB52 JB57 JB63 JB69 KA05 KA07 KA12 KA16 KA18 KA22 KB14 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA35 MA37 MA41 NA15 NA16 NA25 NA28 NA29 PA06

Claims (5)

[Claims] A plurality of gate lines; a plurality of data lines formed to intersect the plurality of gate lines; a thin film transistor formed near an intersection of the gate line and the data line; A liquid crystal display device comprising: a substrate having a pixel electrode connected thereto; a substrate facing the substrate; and a liquid crystal layer sandwiched between the substrate and the facing substrate. At least one of the data lines is formed so that aluminum or a core wiring material containing aluminum as a main component and a lower surface, a side surface, and an upper surface of the core wiring material are surrounded by a material different from the core wiring material. And a wiring end surface formed of the outer wiring material is processed into an integral shape, and the wiring end surface is formed. The liquid crystal display device comprising a and the substrate, the angle sandwiching the side including the wiring smaller than 90 degrees. 2. The liquid crystal display device according to claim 1, wherein the outer wiring material is a first outer wiring material located below the core wiring material, and side and upper surfaces of the core wiring material. The liquid crystal display device comprises two layers of a second outer wiring material located at the same position, and these two layers are formed of different materials. 3. The liquid crystal display device according to claim 2, wherein the first outer wiring material is Cr, and the second outer wiring material contains at least one selected from Mo and W in Cr. A liquid crystal display device characterized by the above-mentioned. 4. The liquid crystal display device according to claim 2, wherein said first outer wiring material is Cr, and said second outer wiring material contains a second element in Cr and is ceric nitrate. A liquid crystal display device wherein the electrode potential of the second outer wiring material in an aqueous ammonium solution is lower than the electrode potential of Cr. 5. A plurality of gate lines, a plurality of data lines formed to intersect the plurality of gate lines, a thin film transistor formed near an intersection of the gate line and the data line, and A method for manufacturing a liquid crystal display device, comprising: a substrate having a pixel electrode connected thereto; a substrate facing the substrate; and a liquid crystal layer sandwiched between the substrate and the facing substrate. A first outer wiring material thin film forming a part of the gate line of the thin film transistor, and a first wiring means for depositing a core wiring material thin film forming a part of the gate line; A first processing means for processing only a wiring material thin film into a gate line pattern by photolithography and etching; Material thin film, and on the gate line pattern of a wiring material film of the core which is formed thereon,
Second deposition means for depositing a second outer wiring material thin film forming a part of the gate line; and photolithography and etching the first outer wiring material thin film and the second outer wiring material thin film. And a second forming means for completing the laminated gate line pattern by processing the gate line pattern slightly wider than the gate line pattern of the core wiring material thin film.