JP2000098002A - Semiconductor integrated circuit and test method therefor - Google Patents

Abstract

(57) [Summary] [PROBLEMS] It is not necessary to create complicated expected value data for a functional test, and it is possible to easily and quickly perform a test. Tests can be easily performed with a small number of probe needles. An output section of an inverter circuit is provided with a switch circuit T, a test terminal _Vtest for applying an arbitrary voltage and monitoring a current flowing therethrough, and an output terminal. By controlling an input signal to the inverter circuit, an output signal output from a transistor of the inverter circuit is controlled. The switch circuit T is controlled by a test circuit (not shown in FIG. 2) in synchronization with the output signal, the test terminal V _test is connected to the output terminal OUT, and the current flowing through the _test terminal V _test at that time is output. Measure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for testing whether a semiconductor integrated circuit is operating normally or not.

[0002]

2. Description of the Related Art In a conventional function test of a semiconductor integrated circuit, first, an input signal generated by an inspection device (test system) is applied to an input terminal of the semiconductor integrated circuit. In a semiconductor integrated circuit, an internal circuit operates based on a given input signal,
The result is output from the output terminal. This output signal is input to the inspection apparatus, and is compared with an expected value signal prepared in advance to perform a functional test on whether the semiconductor integrated circuit is operating normally.

Next, a function test of a conventional semiconductor integrated circuit will be described in detail. FIG. 10 is a block diagram of an integrated circuit including an inverter circuit. This inverter circuit has a structure in which Pch and Nch CMOS FETs are connected in series. The integrated circuit has n inverter circuits. The source of the Pch transistor is VD
The source of the D and Nch transistors is set to GRD and output from the drains of both transistors. The function test of this integrated circuit is performed. FIG. 11 shows a test block diagram of one inverter circuit. The input signal of the inspection device 54 is input to the input terminal 52 of the inverter circuit 51. The output taken from the output terminal 53 of the inverter circuit 51 is compared with the expected value by the comparator 55 of the inspection device 54.

FIG. 12 is a time chart showing a function test on the inverter circuit of the inspection apparatus. In the period A of FIG. 12, the input signal is at the HIGH level, the Pch transistor of the inverter circuit 51 is OFF, and Nc
When the h transistor is turned on, the inverter circuit 51
Output terminal 53 via an Nch transistor
An ND level, that is, a LOW level is output.

The output signal is input to a comparator 55 of the inspection device 54, and is compared with expected value data set in advance by programming. The judgment is made from the signal. In the period B, contrary to the period A, the input signal is at the LOW level and the Pch
When the transistor is turned on and the Nch transistor is turned off, the VDD terminal, that is, the HIGH level is output to the output terminal of the inverter circuit 51 via the Pch transistor.

Periods C and D are examples of defective products in which the source and drain of the Nch transistor of the inverter circuit are short-circuited. In the period D, the Pch transistor of the inverter circuit is turned on and the Nch transistor is turned off, so that the non-defective product outputs the VDD level. In this case, the output state becomes the GND level, and a mismatch with the expected value data occurs. It is determined to be defective. Thus, the function test is performed by inputting the output signal to the comparator 55 of the inspection device 54, comparing it with expected value data set in advance by programming, and making a determination.

Japanese Patent Application Laid-Open No. 7-260857 describes a test in a drive circuit of a liquid crystal display device. FIG. 13 is a block diagram showing a driving circuit of the liquid crystal display device. The drive circuit of the liquid crystal display device has a configuration including an output short circuit including a switching element SW controlled by an eighth test mode signal Tm8 between channels of the output unit 5. The switching element short-circuits all channels in the output section,
If the eighth test mode is a test mode in which the individual channels are sequentially output one by one, the output waveform of each channel can be sequentially observed with the monitor pad MP on the TCP.

Japanese Patent Application Laid-Open No. 8-184646 discloses a semiconductor integrated circuit capable of measuring characteristics. FIG. 14 is a block diagram showing the semiconductor integrated circuit. In the test mode, the output signals from the output circuits 2a to 2d correspond to the corresponding switching signals 5a to 5d, respectively.
Is controlled by Output signals from the switching circuits 6a to 6d are sequentially transmitted as test input / output signals to an external inspection device via the test pads 4a, and are output to the switching circuits 6e to 6d.
The output signal of h is sequentially transmitted to an external inspection device as a test input / output signal via the test pad 4b.

[0009]

In the conventional function test shown in FIG. 11, a supply of an input signal and an expected value for comparison of an output signal corresponding thereto are supplied to a semiconductor integrated circuit to be tested. It is necessary to incorporate it in the inspection device 54 in advance. Generally, in a functional test of a semiconductor integrated circuit, execution of all instructions and various combinations of data are input, and an output expected value corresponding to the input is created (or automatically generated using simulation). As the scale of the circuit increases and the functions become more advanced, expected value data for comparing input signals and output signals given to the semiconductor integrated circuit becomes complicated and bloated, and its development requires a lot of time.

Further, an increase in the number of output terminals of a semiconductor integrated circuit leads to miniaturization between input / output terminals and a reduction in terminal area, and as a result, probing becomes extremely difficult. Further, the amount of investment in a test apparatus and a test jig for performing a functional test of the semiconductor integrated circuit is increasing in proportion to the increase in the number of terminals of the semiconductor integrated circuit.

The technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-260857 is intended to facilitate the operation analysis at the time of mounting a liquid crystal panel, and is not for performing a functional test. In addition, in this technique, it is impossible to perform a function test because each output terminal is always short-circuited. Further, the conventional technique disclosed in Japanese Patent Application Laid-Open No. 8-184646 is intended to improve the measurement accuracy of the characteristic evaluation, and is not for performing a functional test.

According to the present invention, there is no need to create complicated expected value data for a function test, a simple and quick test can be performed, and the number of test terminals is reduced.
It is an object of the present invention to provide a semiconductor integrated circuit that can easily perform a test with a small number of probe stitches even if the number of outputs is large, and a test method therefor.

[0013]

According to the present invention, a plurality of output terminals for outputting a signal, a test terminal for applying a predetermined voltage and measuring a current value flowing from the output terminal are provided. At least at the time of measurement, a semiconductor integrated circuit having switching means for connecting the output terminal for outputting a measurement output signal and the test terminal.

According to a second aspect of the present invention, in the method for testing a semiconductor integrated circuit having the configuration according to the first aspect, a measurement output signal is output from the output terminal by controlling an input signal to the semiconductor integrated circuit, and The switching means connects the output terminal for outputting a measurement output signal to the test terminal, measures a current value at the test terminal at a predetermined timing, and determines the state of the output signal.

According to a third aspect of the present invention, in the method for testing a semiconductor integrated circuit according to the second aspect, at the measurement timing at the test terminal, input is performed such that the number of output terminals for outputting a measurement output signal is the same. A signal is controlled, and the switching means connects the test terminal to an output terminal for outputting the measurement output signal for a measurement signal output period.

According to a fourth aspect of the present invention, there is provided the semiconductor integrated circuit test method according to the second aspect, wherein at the measurement timing at the test terminals, the number of the output terminals for outputting the measurement output signals is the same. A signal is controlled, and the switching means connects the test terminal to an output terminal for outputting the measurement output signal from the time when the measurement output signal is output until the end of the entire test cycle.

According to a fifth aspect of the present invention, in the method for testing a semiconductor integrated circuit according to the second aspect, the switching means is configured such that all output terminals are used as the test terminals, and one of the output terminals is used for the measurement first. It is characterized in that connection is made from the time when an output signal is output until the end of all test cycles.

According to a sixth aspect of the present invention, there is provided the method of testing a semiconductor integrated circuit according to the third, fourth or fifth aspect, wherein a plurality of expected values for the current flowing through the test terminal at the measurement timing are set, and The current flowing through the test terminal is compared with the expected value.

According to a seventh aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit according to any one of the second to sixth aspects, wherein the semiconductor integrated circuit is an LCD driver.

According to the present invention, the development period can be shortened by eliminating the need to create expected value data required for the function test of the semiconductor integrated circuit, and the probing to the output terminal of the semiconductor integrated circuit is not required. Ease of probing, and reduction of the investment amount due to the elimination of the comparator circuit of the test apparatus and the reduction in the number of probe needles of the probe card, which were necessary for performing the functional test, can be achieved.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a semiconductor integrated circuit according to the present invention. This semiconductor integrated circuit has substantially the same configuration as that of the integrated circuit shown in FIG. 12 except for a test circuit 10, a switch circuit T provided in each output unit and controlled by the test circuit 10, and a current This is a point that a _test terminal V _test for measurement is provided.

Here, the measurement principle will be described with reference to FIG. 2 in which one inverter circuit is extracted. The output part of the inverter circuit is provided with a switch circuit T, a test terminal V _test for applying an arbitrary voltage and monitoring a current flowing therethrough, and an output terminal. By controlling an input signal to the inverter circuit, an output signal output from a transistor of the inverter circuit is controlled.
The switch circuit T is controlled by a test circuit (not shown in FIG. 2) in synchronization with this output signal.
_{The test} is connected to the output terminal OUT, and the current flowing through the _test terminal V _test at that time is measured. Thus, a defect of the inverter circuit can be determined from the current value.

As shown in FIG. 2A, the test circuit 10
Turns on the switch circuit T, and the test terminal V _test
To a GND level, turning on the Pch transistor and turning off the Nch transistor. Then, as shown by the arrow in the figure, the current changes from VDD to the test terminal.
_Flow to _test . Further, as shown in FIG. 2B, the switch circuit T is turned on by the test circuit 10, a voltage is applied to the _test terminal V _test to bring the voltage to the VDD level, the Pch transistor is turned off, and the Nch transistor is turned on.
Then, as indicated by arrows in the figure, a current flows through the test terminal V _test from GND.

Next, a functional test of the semiconductor integrated circuit shown in FIG. 1 will be described. FIG. 3 is a time chart showing a first test method of the semiconductor integrated circuit, and FIG. 4 shows a second test method. It is a time chart. In the test method in FIGS. 3 and 4, the HIGH level signal at the output terminal is the measurement output signal.

First, as shown in FIG. 3 (a), output terminals (output 1 to output n) are set to HIGH for a certain period for each terminal.
(VDD) A pattern of an input signal to be output at a level is prepared. In FIG. 3A, each output terminal (output 1 to output n)
Are set so as not to overlap, but they may overlap as described later. When the pattern of the input signal is input to the semiconductor integrated circuit shown in FIG. 1, if the semiconductor integrated circuit is normal, a signal should be output to the output terminal as described above. At this time, if the test circuit 10 is normally high,
The corresponding switch circuits (T1 to Tn) are turned on one terminal at a time for a certain period in synchronization with an output signal for (VDD) level output (FIG. 3B). Switch circuit (T1-T
n) is turned on / off at an output terminal (output 1).
ON / O of HIGH (VDD) level output of output n)
Same as the FF timing. As shown in FIG. 2A, if the Pch transistor is turned on and the Nch transistor is turned off and the test terminal V _test is set to the GND level, the current flowing into the _test terminal _test is as shown in FIG.
(C).

As shown in FIG. 4A, all output terminals (output 1 to output n) are set to HIGH for a certain period of time.
An input pattern for (VDD) level output is prepared.
In FIG. 4A, the output periods of the output terminals (output 1 to output n) are set so as not to overlap with each other.
It does not matter if they overlap. At this time, the test circuit 10 built in the semiconductor integrated circuit also sequentially turns on the switch circuits (T1 to Tn) in synchronization with the measurement output signal in the normal case, and holds that state. Then, when the last output n changes from the HIGH level to the LOW level (when the test cycle ends), all the switch circuits (T1 to Tn) are turned off (FIG. 4B). At this time, as shown in FIG. 2A, if the Pch transistor is turned on and the Nch transistor is turned off, and the test terminal V _test is set to the GND level, the current flowing into the _test terminal _test is as shown in FIG. (C).

The current at the _test terminal V _test shown in FIGS. 3C and 4C is measured at a predetermined timing. At this timing, as shown in the figure, the output signal is HIGH.
The timing is immediately before the level changes from the LOW level to the LOW level. Thus, by measuring the current value, it is possible to inspect the internal inverter circuit for a defect.

Next, a description will be given of the detection status at the _test terminal _test when a defect is desired to occur in the output. FIG. 5 is an explanatory diagram illustrating a failure detection situation when the failure model 1 occurs. As shown in FIG. 5A, in the failure model 1, a measurement output signal (HIGH level) is not output from the output 1,
Instead, the measured output signal is output from the output 2 during the output period of the output 1. FIGS. 5 (b) and 5 (c) show the case where the signal is detected by the first test method of FIG. 3, and FIGS. 5 (d) and 5 (e) show the case where the signal is detected by the second test method of FIG.

In the first test method, the switch circuits T1 to Tn are turned on / off sequentially in synchronization with the outputs 1 to n. Therefore, if the output 1 is not output at the HIGH level, the HIGH level signal of the output 1 is output. At this time, no current flows to the _test terminal _Vtest , and a defect can be detected. On the other hand, in the second test method, the switch circuits T1 to T
Since n keeps the ON state, the current flows through the _test terminal V _test as in the non-defective product, and the failure cannot be detected.

FIG. 6 is an explanatory diagram showing a failure detection situation when the failure model 2 occurs. As shown in FIG. 6A, the failure model 2 is a failure in which the HIGH-level measurement output signal of the output 1 is output for a period longer than the period during which the output signal is originally output, and is output until the output period of the output 2. First of FIG.
FIGS. 6B and 6C show the case where the detection is performed by the test method, and FIG. 6D shows the case where the detection is performed by the second test method in FIG.
(E).

In the first test method, the switch circuits T1 to Tn are sequentially turned ON / OFF in a certain period. Therefore, even if the output period of the output 1 is long, the switch circuit T1 is turned OFF, and the test terminal V _test is Only the current of output 2 flows,
Defects are undetectable. On the other hand, in the second test method,
Since the switch circuits T1 to Tn maintain the ON state, when the output 2 is at the HIGH level, the currents of the output 1 and the output 2 flow to the test terminal V _test, and twice the normal current flows. Therefore, defect detection is possible.

FIG. 7 is a time chart showing the third test method. The measurement output signal in this case is a LOW level signal. First, as shown in FIG. 7A, all the output terminals (output 1 to output n) are switched one by one for a certain period of time LOW.
An input pattern to be output to the (GND) level is prepared. In FIG. 7A, the output periods of the output terminals (output 1 to output n) are set so that they do not overlap, but they may overlap as described later. When this input signal pattern is input to the semiconductor integrated circuit shown in FIG. 1, a signal is output to the output terminal as described above. At this time, the test circuit 10 built in the semiconductor integrated circuit turns on the switch circuits (T1 to Tn) one terminal at a time for a certain period in synchronization with the output terminal (FIG. 7B). Switch circuit (T1-T
n) is turned on / off at an output terminal (output 1).
ON / OF of LOW (GND) level output of output n)
Same as F timing. As shown in FIG.
Pch transistor OFF, Nch transistor O
N, and if the test terminal V _test is set to the VDD level, the current flowing into the _test terminal V _test is as shown in FIG.
(C).

Next, the fourth test method will be described.
When there is an output as in (a), the test circuit 10 built in the semiconductor integrated circuit also turns on the switch circuits (T1 to Tn) sequentially in synchronization with all the output terminals, and holds that state. To go. Then, when the last output n changes from the LOW level to the HIGH level, all the switch circuits (T1 to Tn) are turned off. At this time, FIG.
As shown in (b), the Pch transistor is turned on and Nc
If the h transistor is turned off and the test terminal V _test is set to the GND level, the current flowing into the _test terminal _test becomes as shown in FIG.

When the third and fourth test methods are used to detect the defects shown in FIGS. 5 and 6, the detection results are similar to those of the first and second test methods. However, only the HIGH and LOW of the current waveform of the _test terminal _test are reversed.

As described above, if the first and second test methods or the third and fourth test methods are used in combination,
If a fault can be detected reliably and the optimum current measurement point is set, the measured current value is always constant, and a comparator circuit for comparison and determination that greatly affects the cost of the test equipment, and is used for determination. A memory circuit for retaining the expected value is not required, and the cost for capital investment can be significantly reduced.

FIG. 8 shows that the output terminals are set to HI every two terminals.
9 shows a first test method in a case where GH level output periods overlap. An input pattern of an input signal is prepared so as to obtain the output pattern shown in FIG. FIG.
As shown in (b), the corresponding switch circuits (T1 to Tn) are turned on one terminal at a time for a certain period in synchronization with the output signal.
Let it. In the test terminal V _test , the portion where the output period overlaps is such that the current only flows twice as much as normal (when output from one output terminal), and if the current measurement timing is set appropriately at regular intervals, No expectations for complex test patterns are required. As described above, it is not necessary to change the state setting of the output terminal so that the output periods do not overlap one by one. If an input pattern suitable for the operation of the semiconductor integrated circuit to be tested is created, the problem is raised. Absent. Although the first test method has been described here, the same applies to the second, third, and fourth test methods. Here, when the output periods overlap, the number of output terminals is two, but this is not a limitation, and it is sufficient if the number of output terminals is always the same.

FIG. 9 shows a case in which an expected value corresponding to the current value measured at the _test terminal _Vtest is prepared and a defect is detected. The input pattern of the input signal is prepared so that the output pattern shown in FIG. 9A is obtained. When an input signal is input to the semiconductor integrated circuit and an output signal is output, the test circuit 10 obtains the last output from the time when the first measurement output signal (signal when the integrated circuit is normal) is obtained. Until the test cycle is completed.
Are all turned on (FIG. 9B). As shown in FIG. 9C, three types of expected values (H,
Z, L) are provided, and an input pattern of an input signal is prepared so that the output pattern of FIG. 9A is obtained. By setting in this way, it is necessary to prepare an output pattern, but one terminal that requires the expected value is one terminal,
In addition, since the expected value signal to be created is simple (regular), the time and labor required for the creation are greatly reduced. Furthermore, when the first to fourth test methods are used, the variation of the input signal increases, and a more effective function test can be performed.

Particularly, in recent liquid crystal drivers, the number of output terminals per chip tends to increase in order to cope with a large screen and reduce the number of used terminals per panel. At the same time, the pad pitch of output terminals has been narrowed. Probing is becoming more difficult. Further, the cost per pin of the probing jig changes according to the pad pitch (the higher the finer the jig, the higher the cost), and the overall number is determined by multiplying this by the number of terminals. That is, in the example of the liquid crystal driver, the probing jig is very expensive (there is no need to reduce the pad pitch because the number of input terminals is small and the degree of freedom in arrangement on the chip is high). Therefore, by using the present invention for testing the liquid crystal driver, probing to the output terminal becomes unnecessary, so that probing can be facilitated and the cost of the probing jig can be reduced, and a better effect can be obtained.

[0039]

As described above, according to the present invention, the quality of a semiconductor integrated circuit is determined by measuring the power supply current, so that the comparator circuit for comparison and determination which greatly affects the cost of the test apparatus is used. A memory circuit for retaining the expected value is not required, and the cost for capital investment can be significantly reduced. Further, conventionally, probing is performed on the output terminal in order to extract a signal from the output terminal. However, according to the present invention, probing to the output terminal becomes unnecessary,
It is also possible to improve the ease of probing and reduce the cost of a measuring jig such as a probe card. Further, since it is unnecessary to create an expected value pattern which is conventionally required for performing a functional test, it is possible to shorten a test development period for the functional test. By using the present invention for testing a liquid crystal driver, probing to an output terminal becomes unnecessary, so that probing can be facilitated and the cost of a probing jig can be reduced, and a better effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a diagram illustrating a measurement principle of an inverter circuit.

FIG. 3 is a time chart illustrating a first test method of the semiconductor integrated circuit.

FIG. 4 is a time chart illustrating a second test method of the semiconductor integrated circuit.

FIG. 5 is an explanatory diagram showing a failure detection situation when a failure model 1 occurs.

FIG. 6 is an explanatory diagram showing a failure detection situation when a failure model 2 occurs.

FIG. 7 is a time chart illustrating a third test method of the semiconductor integrated circuit.

FIG. 8 is a time chart illustrating a first test method in a case where HIGH-level output periods of two output terminals overlap each other.

FIG. 9 is an explanatory diagram for preparing an expected value corresponding to a current value measured at a _test terminal V _test and performing defect detection.

FIG. 10 is a block diagram of an integrated circuit including a conventional inverter circuit.

FIG. 11 is a test block diagram of one inverter circuit.

FIG. 12 is a time chart showing a function test on the inverter circuit of the inspection device.

FIG. 13 is a block diagram showing a driving circuit of a liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. 7-260857.

FIG. 14 is a block diagram showing a semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 8-184646.

[Explanation of symbols]

10 Test circuit Pch1-Pchn P-channel transistor Nch1-Nchn N-channel transistor T1-Tn Switch circuit V _test test terminal Output 1-Output n Output terminal

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2G032 AA01 AB01 AC03 AD01 AD05 AE08 AE12 AF02 AF03 AG04 AG07 AG10 AK01 AK11 AK14 AK15 AL03 AL05 2G035 AA01 AC02 AC16 AD24 2H088 FA11 HA05 MA20 5F038 BE05 DT01 DT02 DT02 DT02 DT02

Claims (7)

[Claims] 1. A plurality of output terminals for outputting a signal, a test terminal for applying a predetermined voltage and measuring a current value flowing from the output terminal, and outputting a measurement output signal at least at the time of measurement. A semiconductor integrated circuit having switching means for connecting an output terminal and the test terminal. 2. A test method for a semiconductor integrated circuit having a configuration according to claim 1, wherein a control circuit controls an input signal to the semiconductor integrated circuit to output a measurement output signal from the output terminal, and A test method for a semiconductor integrated circuit, comprising: connecting the output terminal for outputting a measurement output signal to the test terminal; measuring a current value with the test terminal at a predetermined timing; and determining a state of the output signal. . 3. At the measurement timing at the test terminal, an input signal is controlled such that the number of the output terminals for outputting a measurement output signal is the same, and the switching means is connected to an output terminal for outputting the measurement output signal. 3. The test terminal is connected for a measurement signal output period.
The test method of the semiconductor integrated circuit described in the above. 4. At the measurement timing at the test terminal, an input signal is controlled such that the number of the output terminals for outputting a measurement output signal is the same, and the switching means is connected to an output terminal for outputting the measurement output signal. 3. The method for testing a semiconductor integrated circuit according to claim 2, wherein the test terminals are connected from a point in time when the measurement output signal is output until all test cycles are completed. 5. The switching means connects all output terminals to the test terminal from the time when any of the output terminals first outputs the measurement output signal until the end of the entire test cycle. 3. The test method for a semiconductor integrated circuit according to claim 2, wherein 6. The method according to claim 3, wherein a plurality of expected values for a current flowing through the test terminal at the measurement timing are set, and a current flowing through the test terminal at the measurement timing is compared with the expected value. 6. The test method for a semiconductor integrated circuit according to claim 5. 7. The test method for a semiconductor integrated circuit according to claim 2, wherein said semiconductor integrated circuit is an LCD driver.