JP2000090693A - Memory test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory test device for testing setup time Tds and hold time Tdh of a semiconductor memory. SOLUTION: A 2-pattern data generator 22 for generating a couple of pattern data within one operation period is provided in a pattern generator 2, a 2-timing clock generator 33 for generating a couple of timing clocks within one operation period is provided in a timing generator and a 2NRZ wave generator 44 which generates two NRZ waveforms with two timing clocks supplied from the timing generator and then supplies these waveforms to MUT 9 is provided in a waveform shaper 4. Two NRZ waveforms are alternately supplied to an MUT, readout response signal and expectation value pattern signal are logically compared to alternately measure the setup time and hold time of the MUT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus for testing a memory (IC memory) constituted by, for example, a semiconductor integrated circuit (IC) and other various semiconductor memories. Setup time (hereinafter referred to as “Td
s) and hold time (hereinafter “Td
h) as well as a memory test apparatus capable of accurately measuring the setup time and the hold time of a high-speed semiconductor memory.

[0002]

2. Description of the Related Art First, a basic configuration of a conventional memory test apparatus for testing various semiconductor memories is shown in FIG.
This will be described with reference to FIG. As shown, the memory test apparatus basically includes a tester processor 1, a pattern generator 2, a timing generator 3, a waveform shaper 4, a driver 5, an analog level comparator 6, It comprises a pattern comparator 7 and a failure analysis memory 8.

[0005] The tester processor 1 is constituted by a computer system, and controls the entire test apparatus according to a test program created by a user (programmer). For example, a control signal (command) is given to each unit (apparatus or circuit) of the test apparatus via the tester bus BUS. The pattern generator 2 starts generating a pattern in response to a control signal (in this case, a test start command) provided from the tester processor 1 and should apply the pattern to a semiconductor memory under test (generally called a DUT or MUT) 9. Test signal (test pattern data) PT of predetermined pattern
ND, address signal and control signal, pattern comparator 7
To generate an expected value signal (expected value pattern signal) EXP or the like of a predetermined pattern. The pattern generator 2 generally includes an ALPG (Algorithmic Pattern Generator).
r) is used. The ALPG is a pattern generator that generates a test pattern to be applied to a semiconductor memory (for example, an IC memory) by an operation using an internal register having an operation function.

The timing generator 3 generates a timing signal (pulse) based on timing information given from the pattern generator 2 to obtain a test timing of the entire test apparatus, and performs a waveform shaper 4 and a level comparator. 6,
This is given to the pattern comparator 7 and the like. The waveform shaper 4 receives the test pattern data PTN provided from the pattern generator 2.
A test pattern signal PTN having an actual waveform is generated based on D and a timing signal provided from the timing generator 3, and the test pattern signal PTN is transmitted to a semiconductor memory under test (hereinafter referred to as an MUT) 9 through a driver 5.
Is applied.

FIG. 8 shows a test pattern signal PT
The state in which N is applied (test pattern write cycle) is shown. As shown in the figure, when writing a test pattern signal to the MUT 9, the write / read (R / W) terminal of the MUT 9 is set to the write state (W),
The driver 5 is set in an output enable (output enabled) state (an output enable signal "/ OE" is applied), a switch SW1 inserted at the output side is turned on, and the input side of the level comparator 6 is turned on. Switch SW2
Turn off. In this state, a test pattern signal is written to the MUT 9 through the driver 5. In this specification, a signal whose polarity is inverted is indicated with a slash code "/" at the beginning. For example, the output enable signal “/ OE” indicates a signal obtained by inverting the polarity of the signal “OE”.

When the test pattern signal written in the MUT 9 is read after the writing of the test pattern signal to the memory cells in the predetermined test range is completed (in a test pattern read cycle), the driver 5
The switch SW1 on the output side is turned off (output disable state), the R / W terminal of the MUT 9 is set to the read state (R), and the level comparator 6 is set to the input enable (input enabled) state (input The enable signal “/ IE” is applied) The switch SW2 on the input side
Turn on. In this state, the test pattern signal written in the MUT 9 is read.

A test pattern signal (hereinafter referred to as a response signal) read from the MUT 9 has its signal level (usually a voltage level) given from a comparison reference voltage source (not shown) in an analog level comparator 6. The reference voltage is compared with the reference voltage to determine whether or not the reference voltage has a predetermined voltage level. As the reference voltage, the reference voltage V0H (H) used when the response signal from the MUT 9 is logic “1”.
Logic reference voltage) and a reference voltage V0L (L logic reference voltage) used when the response signal from the MUT 9 is logic "0". In the illustrated circuit example, in each case, The level comparator 6 outputs a logical "1" signal at the time of pass, and outputs a logical "0" signal at the time of fail.

[0008] The logic signal output from level comparator 6 determined to have a predetermined voltage level is applied to pattern comparator 7. The pattern comparator 7 performs a logical comparison between the logic signal from the level comparator 6 and the expected value pattern signal EXP given from the pattern generator 2, and detects whether or not both signals match. If the two signals do not match, the pattern comparator 7 determines that the memory cell at the address of the MUT 9 from which the logical signal (response signal) has been read is defective, and outputs a fail (FAIL) signal indicating that. appear. Usually, this fail signal is represented by a logical "1" signal, and is stored in the failure analysis memory 8. Generally, the fail signal is stored at the same address of the failure analysis memory 8 as the address of the failure memory cell of the MUT 9.

On the other hand, when the logic signal matches the expected value pattern signal, the pattern comparator 7 determines that the memory cell at the address of the MUT 9 from which the logic signal has been read is normal, and that fact is determined. A pass signal (PASS) is generated. This pass signal is represented by a logical “0” signal and is not normally stored in the failure analysis memory 8. At the end of the test, the fail signal stored in the failure analysis memory 8 is read, and it is determined whether or not a defective memory cell of the tested semiconductor memory can be rescued, for example.

In the example shown, the pattern generator 2, the timing generator 3, and the waveform shaper 4 are called table memories in this technical field in order to generate various control signals for performing the above-mentioned operations. The memory includes memories (hereinafter, referred to as tables) 2A, 3A, and 4A, and the tables 2A, 3A, and 4A store necessary data from the tester processor 1 in advance.

A user (programmer) considers a test pattern based on performance characteristics of a semiconductor memory to be tested.
You are creating a test program. At this time, in this example, the user has described in this test program data to be stored in advance in the tables 2A, 3A and 4A of the pattern generator 2, the timing generator 3, and the waveform shaper 4, and these data are Before you start testing your memory,
From the tester processor 1, these tables 2A, 3A, 4
A is preloaded.

The table 3A of the timing generator 3 includes a rate (RATE) setting table memory and a clock setting table memory, and a test cycle (test rate or test cycling) is stored in the rate setting table memory.
e) is stored, and the driver setting waveform (the waveform of the test pattern signal PTN given from the waveform shaper 4 to the driver 5) is stored in the clock setting table memory.
Various timing data relating to the above are stored. A plurality of timing data groups, for example, a TS1 group, a TS2 group,..., A TSn group are prepared by combining these timing data, and necessary groups are read to generate timing pulses of set signals and reset signals.

The pattern generator 2 also has an ALPG
The table 2A stores test pattern data to be applied to each of pins 1 to n (n is a positive integer) of the MUT 9. Waveform shaper 4
The table 4A stores data relating to waveform settings such as the waveform mode. The test pattern data PTND generated from the pattern generator 2 and the set and reset timing pulses generated from the timing generator 3 are stored in the table 4A. The test pattern signal PTN having a predetermined waveform and timing is generated by using the signal and supplied to the driver 5.

Next, the setup of the semiconductor memory, for example, the IC memory is performed by the memory test apparatus having the above-described configuration.
A method for measuring time and hold time and checking whether the values are appropriate values will be described. For example, one of IC memories, a static RAM (Static Random Ac)
The various timing signals used when testing a cess memory (hereinafter referred to as an SRAM) are determined with respect to a reference clock, as shown in FIG. FIG. 5A shows S
1 shows a write cycle (1 write cycle) time Twc for the RAM, and the write cycle time Twc
The timing of the start time and the end time is determined by the reference clock, and an address signal (ADR) is sent to the SRAM under test at the start of the write cycle. At a predetermined timing during the write cycle time Twc,
The chip select signal (/ CS) shown in FIG.
The write enable signal (/ WE) shown in FIG. 5C is supplied to the SRAM at a predetermined timing after the chip select signal is transmitted. After the transmission of the write enable signal, the input data Din is written into the SRAM under test at a predetermined timing as shown in FIG. 5D.

The SR under test of the input data Din is actually
Valid data portion Dv written to AM
The time duration d is the sum of the setup time Tds of the input data and the hold time Tdh of the input data, and their timing is defined for the write enable signal. In the development stage of the IC memory, it is inspected whether or not the Tds and Tdh have been developed according to the design standard. In the production stage, it is inspected whether or not they have been produced according to the specification.

Conventionally, when measuring Tds or Tdh, as shown in FIG. 6, an XOR waveform (Exclusive) generated using three timing clocks A, B, and C is used.
OR waveform). The XOR waveform is a waveform in which the waveforms on both sides of logic "1" are always logic "0" or the waveforms on both sides of logic "0" are always logic "1" in one test cycle (one operation cycle). .

This will be described more specifically with reference to FIG. FIG. 6A shows an operation cycle (some operation cycles in a write cycle in this example) when measuring Tds and Tdh, and one operation cycle is represented by RATE. The test pattern data PTND (P1, P2, P3,...) Shown in FIG. 6B is output from the pattern generator 2 in synchronization with (in synchronization with) this operation cycle. 6C, 6D, and 6E show the three timing clocks A, B, and C, respectively, described above. The timing clock A in FIG. 6C is generated by a time Ta after the start of each operation cycle RATE,
The timing clock B of FIG. 6D is generated with a delay of time Tb from the start of each operation cycle, and the timing clock C of FIG. 6E is generated with a delay of time Tc from the start of each operation cycle. Here, the relationship between these delay times is Ta <Tb <Tc, and Tc <RATE.
In this example, Tb−Ta = Tc−Tb = Ta + (R
ATE) -Tc = (RATE) / 3.

These three timing clocks A,
Test pattern data P1, P2, P3,... In each operation cycle in FIG. 6B to be applied to the MUT 9 by B and C.
6F, a test pattern signal PTN in which an inverted signal of the signal of the effective data portion Dvd exists immediately before and immediately after the signal of the effective data portion Dvd actually written in the MUT 9 as shown in FIG. Generate FIG. 6G shows the test pattern shown in FIG. 6B.
When data P1 = 0, P2 = 1, and P3 = 1, the waveform PTNWF of the test pattern signal PTN generated as described above is shown. As can be easily understood from FIG. 6G, the effective data portion Dv actually written in the MUT 9
A logical "1" signal is generated before and after the signal P1 = 0 of d, and a logical "0" signal is generated before and after the signal P2 = 1.
A signal is generated, and a logic "0" signal is generated before and after the signal P3 = 1. That is, XO
An R waveform has been generated. Using this XOR waveform, DU
The Tds and Tdh of T9 are measured. The XO generated by these three timing clocks A, B, and C
The R waveform will be referred to as an XORABC waveform in this specification.

The setup time Tds is measured by delaying the timing of the generation of the timing clock B in FIG. 6D, that is, by increasing the delay time Tb and narrowing the time width (Tds + Tdh) of the effective data portion Dvd. The effective data portion Dvd having the narrowed time width is stored in the MUT 9
Write to. Next, it is read from the MUT 9 and logically compared with the expected value pattern signal EXP, and a boundary between a fail (a mismatch state of both signals) and a path (a coincidence state of both signals) (for example, a boundary where a logical comparison result changes from fail to pass). ) Is measured from the value of the delay time Tb.

On the other hand, the measurement of the hold time Tdh is as follows.
The timing of the generation of the timing clock C in FIG. 6E is advanced, that is, the delay time Tc is shortened, the time width of the effective data portion Dvd is also narrowed, and the effective data portion Dvd whose time width is narrowed is reduced. Write to MUT9. Next, it is read from the MUT 9 and logically compared with the expected value pattern signal EXP, and Tdh is measured from the value of the delay time Tc at the boundary between the pass and the fail (for example, at the boundary where the logical comparison result changes from the pass to the fail). .

[0021]

In recent years, the development of semiconductor memories has been remarkable, and the speed has been further increased. For this reason,
The write cycle time Twc becomes short, that is, becomes short, and depending on the performance of the memory test apparatus, there may be cases where the XORABC waveform cannot be used. The reason will be described.

The logic signal P of the effective data portion Dvd in the test pattern signal applied to the MUT 9 shown in FIG.
i or / Pi (i is an integer, in this example i = 1, 2, 3,
...), That is, the minimum pulse width that can be generated by the memory test apparatus is Tp.
The write cycle time Twc for generating the ORACAC waveform requires about 3 Tp. That is, the relational expression between the write cycle time Twc and the minimum pulse width Tp is Twc
> 3 Tp. Therefore, Twc <3Tp
In this case, the XORBC waveform cannot be used.

For example, if each operation cycle RATE in FIG.
In the case of a memory test apparatus of ns (about 1/111 MHz), the minimum pulse width Tp is about 3 ns.
If the sum of the time and the hold time (Tds + Tdh) (equal to the time width of the signal Pi of the valid data portion Dvd) is not about 3 ns or more, the setup time and the hold time of the SRAM are measured using the XORABC waveform. It is not possible.

Incidentally, the timing clock A of FIG. 6C used for generating the XORABC waveform is omitted, and FIG.
6D to be applied to the MUT 9 by the two timing clocks B and C of FIGS. 6D and 6E for the test pattern data PTND of FIG. 6B, as shown in FIG. 7E, Immediately after the logical signal Pi (P1, P2, P3 in this example) of the valid data portion Dvd actually written in the MUT 9, an inverted signal / Pi of the logical signal Pi of the valid data portion Dvd is provided.
Is used, the hold time of the IC memory can be measured even when Twc <3Tp. In this specification, this waveform is referred to as an XORBC waveform because the timing clock A is not used.

The method of generating the XORBC waveform is shown in FIG. 7 and includes two timing clocks B and C of FIGS. 7C and 7D (substantially different from the two timing clocks B and C of FIGS. 6D and 6E). MUT9 by
7B to be applied to the test pattern data (FIG. 6B
7E), a change point is made in PTND, and immediately after the signal Pi of the effective data portion Dvd actually written in the MUT 9, the signal Pi of the effective data portion Dvd is made as shown in FIG. 7E. Inverted signal of /
Pi is generated.

FIG. 7F shows the waveform PT of the test pattern signal PTN generated as described above when the test pattern data P1 = 0, P2 = 1, and P3 = 1 in FIG. 7B.
Shows NWF. As can be easily understood from FIG. 7F, after the signal P1 = 0 of the effective data portion Dvd actually applied to the MUT 9, a logic “1” signal is generated and the signal P2 is generated.
= 1, a logical "0" signal is generated, and the signal P3 = 1
Is followed by a logic "0" signal.

As described above, when the hold time of the MUT 9 is measured using the XORBC waveform, the measurement can be performed until the relationship between the write cycle time Twc and the minimum pulse width Tp becomes Twc ≧ 2Tp. That is, the sum (Tds + Td) of the setup time and the hold time of the IC memory shown in the specification, for example, the SRAM.
h) is S which is about 1/2 or more of the write cycle time Twc.
Up to the RAM, the hold time of the SRAM can be measured using the XORBC waveform.

However, the measurement using the XORBC waveform is performed immediately before the logic signal Pi of the valid data portion Dvd by inverting the signal Pi of the valid data portion Dvd.
Since Pi cannot be generated, there is a serious drawback that the hold time of the IC memory can be measured, but the setup time Tds of the IC memory cannot be measured. In other words, the logic signal Pi of the valid data portion Dvd
Is the logical signal P of the valid data portion Dvd
As long as it does not exist immediately before i, even if the timing of generation of the timing clock B is shifted (even if the delay time Tb is changed), the starting point of the logic signal Pi of the valid data portion Dvd is not determined (the logic is inverted). Therefore, the pattern comparator 7 cannot accurately judge the coincidence / mismatch of the logic.

One object of the present invention is that the relationship between the write cycle time Twc and the minimum pulse width Tp is Twc ≧ 2.
An object of the present invention is to provide a memory test apparatus capable of measuring both the setup time and the hold time of various semiconductor memories up to Tp. Another object of the present invention is to provide a memory test apparatus capable of accurately measuring both the setup time and the hold time of a high-speed semiconductor memory using an NRZ (non-return to zero) waveform. That is.

[0030]

In order to achieve the above object, according to the present invention, a predetermined test pattern signal is applied to a semiconductor memory under test, and a response read out from the semiconductor memory under test is applied. A memory test apparatus for logically comparing a signal with an expected value pattern signal to test a setup time and a hold time of the semiconductor memory under test generates at least two test signal data of a predetermined pattern within one operation cycle. Pattern generating means, at least two timings within one operation cycle;
A clock generating means for generating a clock, at least two test signal data provided from the pattern generating means, and at least two timing clocks provided from the timing generating means generate two N.
A memory generating apparatus for generating an RZ waveform and applying the generated RZ waveform to the semiconductor memory under test.

The pattern generation means outputs two test signal data whose logics are inverted with each other in each operation cycle. In one preferred embodiment,
When testing the setup time of the semiconductor memory under test, the pattern generation means outputs first and second two test signal data whose logics are inverted with each other in each operation cycle, When the hold time of the semiconductor memory under test is tested, third and fourth two test signal data obtained by inverting the logic states of the first and second two test signal data are output.

The waveform generating means makes a change point in one of the two test signal data supplied from the pattern generating means by one of the two timing clocks supplied from the timing generating means, and uses the other timing clock to generate a changing point. A change point is created in the other test signal data to generate one NRZ waveform. In a preferred embodiment, the waveform generating means sets a change point in each of the first and fourth test signal data provided from the pattern generating means by one of two timing clocks provided from the timing generating means. Then, the second and third test signal data are changed at different timing clocks to generate two NRZ waveforms.

In a modified example, the waveform generating means, when testing the setup time of the semiconductor memory under test, receives a signal from the timing generating means.
One of two timing clocks makes a change point in one of the two test signal data provided from the pattern generating means, and the other timing clock makes a change point in the other test signal data to form one NRZ
When generating a waveform and testing the hold time of the semiconductor memory under test, a change point is created in the other test signal data by the one timing clock, and the one test clock is generated by the other timing clock. A change point is made in the signal data to generate one more NRZ waveform.

The generation timing of at least two timing clocks generated by the timing generation means is variable. According to the present invention, a pattern generating means for outputting test signal data of a predetermined pattern, a timing generating means for generating a required timing signal, a timing signal given from the timing generating means, Waveform generating means for generating a test pattern signal having an actual waveform from test signal data supplied from the generating means, a driver for applying the test pattern signal output from the waveform generating means to the semiconductor memory under test, A memory test device for logically comparing a response signal read from the semiconductor memory with an expected value pattern signal given from the pattern generating means, and determining whether the semiconductor memory under test is good or bad; 1 provided in the means
Pattern data generation means for generating at least two test signal data of a predetermined pattern within an operation cycle; and timing clock generation provided in the timing generation means for generating at least two timing clocks within one operation cycle Means, at least two test signal data provided from the pattern data generating means, provided in the waveform generating means, and at least two timing clocks provided from the timing clock generating means, to form two NRZ waveforms. N to generate
A memory test apparatus including an RZ waveform generation unit and capable of testing a setup time and a hold time of a semiconductor memory under test is also provided.

The pattern data generating means outputs two test signal data whose logics are inverted with each other in each operation cycle. In a preferred embodiment, when testing the setup time of the semiconductor memory under test, the pattern data generating means has a first logic whose logic is inverted in each operation cycle.
And when outputting the two test signal data and testing the hold time of the semiconductor memory under test, the third and the second inverted test signal data of the first and second test signal data are respectively inverted. The fourth two test signal data are output.

The NRZ waveform generating means generates a change point in one of the two test signal data supplied from the pattern data generating means by one of the two timing clocks supplied from the timing clock generating means, A change point is made in the other test signal data by the timing clock to generate one NRZ waveform.

In one preferred embodiment, the NRZ
The waveform generating means is configured to output the first and second clocks supplied from the pattern data generating means by one of the two timing clocks supplied from the timing clock generating means.
And a change point in each of the fourth test signal data,
The second and third timing clocks are used by the other timing clock.
Change points in the test signal data of
Generate an RZ waveform.

In one modification, when testing the setup time of the semiconductor memory under test, the NRZ waveform generation means uses the one of the two timing clocks provided by the timing clock generation means to test the pattern. A change point is created in one of the two test signal data provided from the data generation means, and a change point is created in the other test signal data by the other timing clock to generate one NRZ waveform, and hold the semiconductor memory under test. In testing the time, a change point is created in the other test signal data by the one timing clock, and a change point is created in the one test signal data by the other timing clock to further add one more point. Generate an NRZ waveform.

The timing of generating at least two timing clocks generated by the timing clock generating means is variable.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS.
In these drawings, parts corresponding to the parts, waveforms, and elements shown in FIGS. 6 to 8 are denoted by the same reference numerals, and description thereof will be omitted unless necessary.

FIG. 1 is a block diagram showing a basic configuration of an embodiment of a memory test apparatus according to the present invention, and FIG. 2 is a timing chart for explaining a method of generating an NRZBC waveform used in the present invention. is there. NRZ (non-re
The “turn to zero” waveform refers to a waveform that does not return to the original state within one operation cycle RATE once the state changes within that cycle.

Like the conventional memory test apparatus shown in FIG. 8, the memory test apparatus shown in FIG. 1 basically includes a tester processor (not shown), a pattern generator 2, and a timing generator. 3, a waveform shaper 4, a driver 5,
It comprises an analog level comparator 6, a pattern comparator 7, and a failure analysis memory (not shown).

In the present invention, the pattern generator 2 outputs two test pattern data PTND1 and PTND2 to the waveform shaper 4 within one operation cycle RATE.
A pattern data generator 22 is provided, and the timing generator 3 includes two timing generators within one operation cycle RATE.
A two-timing clock generator 33 that outputs clocks B and C to the waveform shaper 4 is provided. Further, the waveform shaper 4 includes a 2NRZ waveform generator 44 that generates two NRZ waveforms.

The waveform shaper 4 has two test pattern data PTND1 and PND provided from the pattern generator 2.
By using TND2 and two timing clocks B and C provided from the timing generator 3, its 2NR
Two NRZ waveforms can be generated by the Z waveform generation unit 44. The process of generating two NRZ waveforms in the 2NRZ waveform generation unit 44 of the waveform shaper 4 will be described with reference to FIG.

FIG. 2A shows an operation cycle RATE when measuring Tds and Tdh. In accordance with (in synchronization with) this operation cycle, the test pattern data PTND1 (P1b, P2b, P3b, P3b, ..) And PTND2 (P1c, P2c, P3c,...) Are output from the pattern generator 2. 2D and 2E show NRZ
FIG. 2D shows two timing clocks B and C for generating a waveform, respectively.
Is generated with a delay of time Tb from the start of each operation cycle, and the timing clock C of FIG. 2E is generated with a delay of time Tc from the start of each operation cycle. Here, the relationship between these delay times is Tb <Tc, and Tc <R
ATE.

These two timing clocks B and C
2B and 2C in each operation cycle RATE
Test pattern data P1b, P2b, P3b,.
., And P1c, P2c, P3c,..., And change points, and as shown in FIG. 2F, test pattern data P1b, P2b, P3b,.
A test pattern signal PTN to be applied to the MUT 9 in which data P1c, P2c, P3c,.
Generate FIG. 2G shows that the test pattern data PTND1 shown in FIG. 2B has P1b = 0, P2b = 1, P3b.
= 1 and the test pattern data P shown in FIG. 2C
When TND2 is P1c = 1, P2c = 0, and P3c = 0, the waveform PTNWF of the test pattern signal PTN generated as described above is shown.

As can be easily understood from FIG. 2, in this example, the test pattern data PTND1 is set by the timing clock B and the test pattern data PTND2 is reset at the same time in each operation cycle RATE. At the same time as resetting the test pattern data PTND1, the test pattern data PTND2 is set, and a test pattern signal PTN to be applied to the MUT 9 is generated. As a result, the test pattern signal PTN is, as shown in FIG. 2F, the test pattern data PTN in the same operation cycle after the data having a time width corresponding to a half cycle of the test pattern data PTND1 in one operation cycle.
This is a signal followed by data having a time width corresponding to a half cycle of D2. That is, the test pattern data PTND1 having a time width corresponding to a 周期 cycle and the test pattern data PTND2 having a time width corresponding to a 周期 cycle are signals arranged alternately at the same operation cycle. From the above results,
The test pattern data is generated by the two pattern data generation unit 22 of the pattern generator 2 so that the logic of the test pattern data PTND1 and the logic of the test pattern data PTND2 are in an inverted state with each other in each operation cycle RATE. When supplied to the waveform shaper 4, as is clear from FIG. 2G, one test pattern data PTN
Data P1b, P2b, P3 in each operation cycle of D1
Data immediately after b,... are data P1c, P in each operation cycle of the other test pattern data PTND2.
2c, P3c,...
Two data are always data whose logic is inverted. Therefore, the test pattern data P in the two pattern data generation unit 22 of the pattern generator 2 are in an inverted state with respect to each other.
By inverting the logic of TND1 and the logic of test pattern data PTND2 (test pattern data P
By generating two test pattern data in which the logics of TND1 and test pattern data PTND2 are respectively inverted), two NRZs in each operation cycle
Waveforms can be generated. For example, in the example of FIG. 2, test pattern data P1b = 0, P1c = 1, P2b
= 1, P2c = 0, P3b = 1, P3c = 0, the test pattern signal waveform PTNWF changes from “0” to “1”.
→ “1” → “0” → “1” → “0”, and the first NRZ waveform is generated. Next, the logic is reversed and P1b = 1, P
1c = 0, P2b = 0, P2c = 1, P3b = 0, P3
If c = 1, the test pattern signal waveform PTNWF changes from “1” → “0” → “0” → “1” → “0” → “1”, and the second NRZ waveform is generated. Thus, two NRZ waveforms can be generated in each operation cycle.

In this specification, one operation cycle RATE is performed by using two test pattern data PTND1 and PTND2 and two timing clocks B and C.
The two NRZ waveforms generated within are referred to as NRZBC waveforms. Although the timing clock A is not used, the timing clocks are described as timing clocks B and C as in the case of FIG. 7, but the timing clocks A and B are also named timing clocks D and E. Alternatively, the name of the test pattern data may be arbitrary. In short, the same operation can be performed by using two timing clocks and two test pattern data. In addition, the actual MU
Either test pattern data may be used as the signal of the valid data portion Dvd to be written in T9. Next, an operation of measuring the setup time Tds and the hold time Tdh of a semiconductor memory (for example, an SRAM) using the NRZBC waveform will be specifically described.

FIG. 3 is a timing chart for explaining the operation when measuring the setup time of the SRAM. FIG. 3A shows an operation cycle (in this example, several operation cycles in a write cycle), and shows one operation. The cycle is represented by RATE. When measuring Tds, as described above, the effective data portion D actually written into the MUT 9 is used.
A signal obtained by inverting the logic of the Dvd signal must exist immediately before the logic signal of vd. Therefore, in this case, the two-pattern data generator 22 of the pattern generator 2
B and two test pattern data PTND1 and PTND2 whose logic is inverted with respect to each other as shown in FIG. 3C.

Specifically, the test pattern data applied to the MUT 9 is the test pattern data PT shown in FIG.
If it is ND2 (P1, P2, P3), data (/ P1, / P2, / P3) that is the logic inverted of test pattern data PTND2 in FIG. 3C is generated as test pattern data PTND1 in FIG. 3B, These test pattern data PTND1 and PTND2 are stored in an operation cycle R
The signal is output from the pattern generator 2 in synchronization with (synchronized with) the ATE and supplied to the waveform shaper 4. The 2NRZ waveform generation unit 44 of the waveform shaper 4 sets the test pattern data PTND1 by the timing clock B of FIG. 3D which is generated with a delay of the time Tb from the start of each operation cycle, and tests each operation cycle. Pattern data P1, P
2 and P3, and the test pattern data PTND2 is generated by the timing clock C of FIG. 3E which is generated with a delay of time Tc from the start of each operation cycle.
To set the test pattern data / P for each operation cycle
1. Create a change point at / P2, / P3. As a result, FIG.
As shown in the figure, the data having a time width of 1/2 cycle is / P1,
A test pattern signal PTN composed of signals arranged in the order of P1, / P2, P2, / P3, P3 is generated, and the MU is generated.
It will be applied to T9. That is, data (Data / P1, with a 1/2 cycle time width) obtained by logically inverting the data immediately before the valid data portion Dvd (1/2 cycle time width data P1, P2, P3) actually written into the MUT 9. /
P2, / P3) is generated. The waveform of the test pattern signal PTN is shown in FIG.
As shown in G, two NRZ waveforms (NRZBC waveforms)
Is one of the waveforms. In this example, the delay time T
The time width obtained by subtracting the delay time Tb from c is one operation cycle RA
It is set to a time corresponding to 1/2 of TE.

The measurement of the setup time Tds is performed in the same manner as in the conventional example.
Is delayed, that is, the delay time Tb
And the time width of the valid data portion Dvd (Tds
+ Tdh) is narrowed, and the effective data portion Dvd having the narrowed time width is written into the MUT 9. Next, it is read out from the MUT 9 and logically compared with an expected value pattern signal EXP given from the pattern generator 2, and a boundary between a fail (a mismatch state of both signals) and a path (a match state of both signals) (for example, a logical comparison result) The value of the delay time Tb at the boundary where the signal changes from fail to pass) is measured, and Td is calculated from the measured value.
Measure s.

On the other hand, when measuring the hold time Tdh of the SRAM, the signal obtained by inverting the logic of the Dvd signal immediately after the signal of the valid data portion Dvd to be actually written into the MUT 9 is used as described above. Must be present. FIG. 4 is a timing chart for explaining the operation when measuring the Tdh of the SRAM.
Indicates an operation cycle (some operation cycles in the write cycle in this example) RATE, and FIGS. 4B and 4C show 2
Test pattern data PTND1 and PTND2 whose logics are inverted with respect to each other are shown.

At the time of measuring Tds, the MUT is actually
9, the valid data portion Dvd is P1, P2, P
.., The effective data portion Dvd of the test pattern data actually written in the MUT 9 is the same data P1, P2, P3,.
Must. Therefore, in this case, the two-pattern data generation unit 22 of the pattern generator 2 is the same as that shown in FIGS.
C, two test pattern data PTND1 and PTND2 whose logics are inverted. That is, P1, P2, P3,... Are generated as the test pattern data PTND1 in FIG. 4B, and the data / P1, which is the inverted logic of the test pattern data PTND1 in FIG. 4B, is generated as the test pattern data PTND2 in FIG. 4C.
/ P2, / P3,... Are generated.

These test pattern data PTND1
And PTND2 are output from the pattern generator 2 in synchronization with (synchronized with) the operation cycle RATE, and are supplied to the waveform shaper 4. 2NRZ waveform generator 44 of this waveform shaper 4
Sets the test pattern data PTND1 by the timing clock B of FIG. 4D which is generated after the time Tb from the start of each operation cycle, and changes the test pattern data P1, P2, P3 of each operation cycle to The test pattern data PTND2 is set by the timing clock C of FIG. 4E which is generated with a delay of the time Tc from the start of each operation cycle, and the test pattern data / P1, / P2 of each operation cycle is set. , / P3. As a result, as shown in FIG.
The data of the time width of the cycle is P1, / P1, P2, / P2,
A test pattern signal PTN composed of signals arranged in the order of P3 and / P3 is generated and applied to the MUT 9. That is, the effective data portion Dvd (data P1, P2 having a time width of 1/2 cycle) actually written to the MUT 9
2, P3) is the logically inverted data (1/1/3)
A test pattern signal PTN which is data / P1, / P2, / P3) having a time width of two cycles is generated. As shown in FIG. 4G, the waveform of this test pattern signal PTN is 2
This is the other of the two NRZ waveforms (NRZBC waveform). Note that, in this example as well, the delay time Tb
Is set to a time corresponding to の of one operation cycle RATE.

The measurement of Tdh was performed in the same manner as in the conventional example, as shown in FIG.
The timing of the generation of the timing clock C is advanced, that is, the delay time Tc is shortened, the time width of the effective data portion Dvd is narrowed, and the narrowed effective data portion Dvd is written to the MUT 9. . Next, MU
It is read from T9, logically compared with the expected value pattern signal EXP, and the value of the delay time Tc at the boundary between the pass and the fail (for example, the boundary at which the logical comparison result changes from the pass to the fail) is measured, and Tdh is calculated from the measured value. Measure.

As described above, when the NRZBC waveform is used, the write cycle time Twc and the minimum pulse width Tp
Up to Twc ≧ 2Tp, the setup time and the hold time of the MUT 9 can be measured. That is, according to the present invention, the setup time of the semiconductor memory up to the semiconductor memory in which the sum (Tds + Tdh) of the setup time and the hold time of the semiconductor memory described in the specification is about 1/2 or more of the write cycle time Twc is obtained.
The time and the hold time can each be measured accurately. Therefore, Twc can be shortened to 2Tp, so that Tds and Tdh can be accurately measured up to a high-speed semiconductor memory in the range of 3Tp ≧ Twc ≧ 2Tp, which cannot be measured by the conventional memory test apparatus. .

In the above embodiment, the logic of the test pattern data PTND1 and the logic of the test pattern data PTND2, which are in an inverted state, are reversed in the two pattern data generator 22 of the pattern generator 2, so that the other NRZ waveform is obtained. Is generated, but the present invention is not limited to this method. For example, the test pattern data PTND1
Without reversing the logic of the test pattern data PTND2 and the test pattern data PTND1 by the timing clock C (Tc) in the 2NRZ waveform generator 44 of the waveform shaper 4, and the timing clock B (Tb ) By the test pattern data PT
Even if ND2 is set, the other NRZ waveform can be generated. Specifically, in FIG. 3, if the test pattern data PTND1 is set by the timing clock C and the test pattern data PTND2 is set by the timing clock B, the same result as in FIG. 4 can be obtained. Two NRZs in a cycle
Waveforms can be generated. In other words, two NRZ waveforms can be generated in each operation cycle by inverting test pattern data that is set / reset (gives a change point) by two timing clocks.

The memory test apparatus according to the present invention
Needless to say, the present invention can be similarly used for measuring the setup time and the hold time of various semiconductor memories other than the C memory (for example, SRAM). Although the present invention has been described with reference to preferred embodiments, it is understood by those skilled in the art that various modifications, changes, and improvements can be made to the embodiments described above without departing from the spirit and scope of the present invention. It will be clear to you. Accordingly, the invention is not limited to the illustrated embodiments, but encompasses all such variations, modifications, and improvements that fall within the scope of the invention as defined by the appended claims.

[0059]

As is apparent from the above description, the memory test apparatus according to the present invention can be used in each operation cycle immediately before the valid data portion actually written in the semiconductor memory under test.
Two types of NRZ waveforms can be generated: an NRZ waveform that generates an inverted signal of the valid data portion, and an NRZ waveform that generates an inverted signal of the valid data portion immediately after the valid data portion. Therefore, by using these two types of NRZ waveforms, the relationship between the write cycle time Twc and the minimum pulse width Tp becomes Twc ≧ 2Tp, and the setup time and hold time of various semiconductor memories.
Time can be measured accurately. Thus, T
Since wc can be shortened to 2Tp, 3Tp ≧ Twc ≧ which cannot be measured by the conventional memory test apparatus.
Up to a high speed semiconductor memory in the range of 2 Tp, a significant advantage is obtained in that its Tds and Tdh can be measured accurately.

In recent years, the speed of semiconductor memory has been remarkably increased, and the effect obtained by the present invention is extremely large for practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an embodiment of a memory test device according to the present invention.

FIG. 2 is a timing chart for explaining a method of generating an NRZBC waveform used in the present invention.

FIG. 3 is an NR used when measuring the setup time of an IC memory using the memory test apparatus shown in FIG. 1;
5 is a timing chart for explaining a method of generating a ZBC waveform.

FIG. 4 is an NRZBC used when measuring the hold time of an IC memory by the memory test apparatus shown in FIG. 1;
6 is a timing chart for explaining a waveform generation method.

FIG. 5 is a timing chart for explaining an operation of writing data to an IC memory under test in a conventional memory test apparatus.

FIG. 6 is a timing chart for explaining a method of generating an XORABC waveform used when measuring a setup time and a hold time of an IC memory using a conventional memory test apparatus.

FIG. 7 shows an XORBC used when measuring the hold time of a high-speed IC memory using a conventional memory test apparatus.
6 is a timing chart for explaining a waveform generation method.

FIG. 8 is a block diagram showing a basic configuration of an example of a conventional memory test device.

[Explanation of symbols]

 1: Tester processor 2: Pattern generator 3: Timing generator 4: Waveform shaper 7: Pattern comparator 8: Failure analysis memory 9: Memory under test 22: 2 pattern data generator 33: 2 timing clock generator 44: 2NRZ waveform generation unit Tds: setup time Tdh: hold time Dvd: valid data part

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01R 31/28 R

Claims (14)

[Claims] 1. A predetermined test pattern signal is applied to a semiconductor memory under test, a response signal read from the semiconductor memory under test is logically compared with an expected value pattern signal, and a setup time and hold of the semiconductor memory under test are performed. In a memory test apparatus for testing time, pattern generation means for generating at least two test signal data of a predetermined pattern within one operation cycle, and timing generation means for generating at least two timing clocks within one operation cycle Waveform generating means for generating two NRZ waveforms based on at least two test signal data provided from the pattern generating means and at least two timing clocks provided from the timing generating means, and applying the two NRZ waveforms to the semiconductor memory under test And a method characterized by having Moly test equipment. 2. The memory test apparatus according to claim 1, wherein said pattern generation means outputs two test signal data whose logics are inverted with each other in each operation cycle. 3. The test circuit according to claim 1, wherein the pattern generating means tests the setup time of the semiconductor memory under test in each operation cycle with two first and second test signals whose logics are inverted with respect to each other. When outputting the data and testing the hold time of the semiconductor memory under test, the third and fourth two test signal data obtained by inverting the logic states of the first and second two test signal data, respectively. 2. The memory test apparatus according to claim 1, wherein the memory test apparatus outputs 4. The waveform generating means generates a change point in one of two test signal data supplied from the pattern generating means by one of two timing clocks supplied from the timing generating means, 3. The memory test apparatus according to claim 2, wherein a transition point is generated in the other test signal data by a clock to generate one NRZ waveform. 5. The waveform generating means generates a change point in each of the first and fourth test signal data provided from the pattern generating means by one of two timing clocks provided from the timing generating means, 4. The memory test apparatus according to claim 3, wherein a transition point is formed in each of the second and third test signal data by the other timing clock to generate two NRZ waveforms. 6. When the setup time of the semiconductor memory under test is tested, the waveform generation means outputs two waveforms provided from the pattern generation means by one of two timing clocks supplied from the timing generation means. When a change point is made in one of the test signal data and a change point is made in the other test signal data by the other timing clock to generate one NRZ waveform, and the hold time of the semiconductor memory under test is tested, A change point is created in the other test signal data by the one timing clock, and the other
3. The memory test apparatus according to claim 2, wherein a change point is created in said one test signal data by a clock to generate one more NRZ waveform. 7. The memory test apparatus according to claim 1, wherein the generation timing of at least two timing clocks generated by said timing generation means is variable. 8. A pattern generating means for outputting test signal data of a predetermined pattern, a timing generating means for generating a required timing signal, a timing signal supplied from the timing generating means, and a timing signal supplied from the pattern generating means. Waveform generating means for generating a test pattern signal having an actual waveform from the test signal data, a driver for applying the test pattern signal output from the waveform generating means to the semiconductor memory under test, and reading from the semiconductor memory under test A pattern comparator for performing a logical comparison between the response signal obtained and an expected value pattern signal given from the pattern generating means, and determining whether the semiconductor memory under test is good or bad. At least two tests in a predetermined pattern within one operation cycle Pattern data generating means for generating signal data; timing clock generating means for generating at least two timing clocks within one operation cycle provided in the timing generating means; At least two test signal data provided from the pattern data generating means and at least two timing clocks provided from the timing clock generating means,
A memory test apparatus comprising: NRZ waveform generation means for generating two NRZ waveforms; and capable of testing a setup time and a hold time of a semiconductor memory under test. 9. The memory test apparatus according to claim 8, wherein said pattern data generating means outputs two test signal data whose logics are inverted with each other in each operation cycle. 10. The pattern data generating means, when testing a setup time of a semiconductor memory under test, includes a first test and a second test whose logics are inverted in each operation cycle. When outputting the signal data and testing the hold time of the semiconductor memory under test, the third and fourth test signals obtained by inverting the logical states of the first and second two test signal data, respectively. 9. The memory test apparatus according to claim 8, wherein the memory test apparatus outputs data. 11. The NRZ waveform generating means generates a change point in one of two test signal data supplied from the pattern data generating means by one of two timing clocks supplied from the timing clock generating means, 10. The memory test apparatus according to claim 9, wherein a change point is generated in the other test signal data by the other timing clock to generate one NRZ waveform. 12. The NRZ waveform generating means changes the first and fourth test signal data supplied from the pattern data generating means by one of two timing clocks supplied from the timing clock generating means. 11. The memory test apparatus according to claim 10, wherein a point is formed, and a transition point is formed in each of the second and third test signal data by the other timing clock to generate two NRZ waveforms. 13. The NRZ waveform generating means, when testing a setup time of a semiconductor memory under test,
One of the two timing clocks supplied from the timing clock generating means makes a change point in one of the two test signal data supplied from the pattern data generating means, and the other timing clock generates a change point in the other test signal data. Make a change point and get one N
When generating an RZ waveform and testing the hold time of the semiconductor memory under test, a change point is created in the other test signal data by the one timing clock, and the one timing clock is changed by the other timing clock. Create a change point in the test signal data and add one more NR
The memory test apparatus according to claim 9, wherein the memory test apparatus generates a Z waveform. 14. The generation timing of at least two timing clocks generated by said timing clock generation means is variable.
3. The memory test device according to claim 1.