JP2000068228A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: A fine contact hole connected to an impurity region of a substrate is easily formed while preventing damage to the substrate, and the contact resistance is reduced. An element isolation, a gate electrode, and an oxide film on an upper surface thereof are formed on a surface of a silicon substrate to form an impurity region. Next, a metal film 5 is formed on the entire surface. Next, a resist mask 6 is selectively formed on the metal film 5. Next, the metal film 5 is etched using the resist mask 6 as an etching mask so that the impurity region 8 is not exposed, thereby forming an electrode 53 including a metal floor 52 and a metal column 51 thereon. The metal floor 52 is formed to cover the entire surface of the impurity region 8. Next, an interlayer insulating film 7 is formed on the entire surface. Next, the interlayer insulating film 7 is etched to form the metal pillars 51.
To expose. Next, an on-metal wiring 54 connected to the metal pillar 51 is selectively formed on the interlayer insulating film 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS (Metal-Oxide-Semicond).
and a method of manufacturing the same.

[0002]

2. Description of the Related Art To manufacture a semiconductor device 200 having a MOS transistor, first, as shown in FIG. 2A, an impurity region 8 such as a gate electrode 3 and a diffusion layer is formed on a semiconductor substrate 1 such as silicon. After the formation, as shown in FIG. 2B, an interlayer insulating film 17 is formed on the substrate 1, and thereafter, as shown in FIG. 2C, an opening for forming a contact hole is formed by using a lithography technique. 161 is formed on the interlayer insulating film 17 and then the etching mask 16 shown in FIG.
As shown in (D), the interlayer insulating film 17 is etched using the etching mask 16 as a mask to form a contact hole 171 exposing the impurity region 8. Next, FIG.
As shown in (E), a wiring 150 connected to the impurity region 8 through the contact hole 171 is formed on the interlayer insulating film 17 by using a technique such as sputtering or CVD.

[0003]

The conventional manufacturing method and the semiconductor device 200 manufactured by the conventional manufacturing method have the following problems.

[0004] 1. Since the connection with the impurity region 8 of the substrate 1 is made only through the conductor in the contact hole 171, the contact resistance between the substrate 1 and the wiring 150 increases in the fine contact hole 171. 0.2
If it is less than μmφ, it becomes 100Ω or more.

[0005] 2. Although the interlayer insulating film 17 is over-etched to expose the impurity region 8 of the substrate 1 to the contact hole 171, the substrate 1 is etched while the interlayer insulating film 17 is over-etched. Damage is formed.

[0006] 3. When forming the resist mask 16 for forming the contact hole 171, an opening 161 for forming the contact hole is formed. However, since the opening 161 is a punched pattern, it is difficult to control the hole diameter.
Also, with the blanking pattern, it is not possible to form a fine wiring pattern exceeding the performance limit of the stepper.

[0007] 4. In the etching of the fine contact hole 171, a phenomenon called an etch stop occurs, and the fine contact hole 171 exposing the impurity region 8 cannot be formed.

[0008] 5. It is difficult to embed a conductor such as a metal in the fine contact hole 171.

Accordingly, it is an object of the present invention to easily form a fine contact hole for connecting an impurity region of a substrate, to prevent damage to the substrate at the time of forming a contact,
Moreover, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing contact resistance and a semiconductor device capable of reducing contact resistance even when impurity regions of a substrate are connected by fine contact holes.

[0010]

According to a first aspect of the present invention, an impurity region is formed on one main surface of a semiconductor substrate by exposing a part or all of the surface of the impurity region from the one main surface. A step of forming a conductive film on the one main surface of the substrate so as to cover at least a part or all of the exposed surface of the impurity region; and an etching mask, wherein the one main surface is formed from above the one main surface. A step of selectively forming, on the conductive film, an etching mask in which the projected area of the etching mask is smaller than the exposed area of the impurity region when looking at the surface, and using the etching mask as a mask; The conductive film is etched so that the first sub-electrode on the impurity region and the second sub-electrode on the first sub-electrode are viewed from above the one main surface toward the one main surface. If the second The method of manufacturing a semiconductor device characterized by comprising the steps of the projected area of the electrode to form an electrode and a first sub electrode sub-electrode smaller the second than the projected area of, is provided.

According to a second aspect of the present invention, the step of forming the conductive film includes the step of: forming the impurity region on the one main surface of the semiconductor substrate through the opening of an insulator formed on the one main surface. Forming the conductive film on the one main surface of the semiconductor substrate formed by exposing a part or all of the surface of the region so as to cover at least a part of the impurity region exposed to the opening; Wherein the step of forming the electrode includes etching the conductive film using the etching mask as a mask, covering the entire surface of the portion of the impurity region exposed to the opening, in the opening of the insulator. The first sub-electrode present and the second sub-electrode on the first sub-electrode, the second sub-electrode being viewed from above the one main surface toward the one main surface; The projected area of the electrode is the first sub-electrode The method of manufacturing a semiconductor device according to claim 1, characterized in that the step of forming the electrode and a smaller second sub electrode than the projected area is provided.

According to a third aspect of the present invention, the first sub-electrode and the second sub-electrode are made of the same conductive material. Is provided.

According to the fourth aspect, a step of forming a conductive film on the one main surface of the semiconductor substrate in which the impurity region is formed on one main surface of the semiconductor substrate, and selecting an etching mask on the conductive film And a step of etching the conductive film using the etching mask as a mask so that the impurity region is not exposed.

In the method of manufacturing a semiconductor device according to any one of the first to fourth aspects, preferably, the impurity region is a source region and / or a drain region.

Preferably, after forming the conductive film by etching as described in the above claims, an interlayer insulating film filling the conductive film is formed, and then the interlayer insulating film is processed by etching or the like. Is exposed, and thereafter, a predetermined wiring or the like is formed by a conductor connecting the exposed conductive film.

According to claim 5, the semiconductor substrate, an impurity region formed on one main surface of the semiconductor substrate, an electrode formed on the impurity region, a columnar electrode formed on the electrode, Wherein the projected area of the electrode is larger than the projected area of the columnar electrode when the one main surface is viewed from above the one main surface.

According to a sixth aspect of the present invention, the semiconductor device further comprises an insulator formed on one main surface of the semiconductor substrate, the insulator having an opening exposing the impurity region. 6. The semiconductor device according to claim 5, wherein the semiconductor device is provided in the opening of the insulator so as to entirely cover a portion of the region exposed to the opening.

In the semiconductor device according to the fifth or sixth aspect, preferably, the impurity region is a source region and / or a drain region.

According to a seventh aspect of the present invention, there is provided the semiconductor device according to the fifth or sixth aspect, wherein the electrode and the columnar electrode are made of the same conductive material.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Conventionally, instead of forming a contact hole in an interlayer insulating film and embedding a wiring in the contact hole, a pole connecting the substrate and a wiring running on the interlayer insulating film is first formed. The above problem of the technology can be solved. Before forming an interlayer insulating film, a metal film is formed, and thereafter, the metal film is etched to a position between the gate electrode or the device isolation film and the substrate. At this time, impurities such as a diffusion layer formed on the substrate are removed. By leaving the metal film so that the region is not exposed, the impurity region is covered with the metal, so that the contact resistance is greatly reduced. Further, since the substrate is not etched, damage due to plasma is not formed on the substrate. Thereafter, an interlayer insulating film is formed, the interlayer insulating film is processed by etching or the like to expose a pole made of a metal film, and then a predetermined wiring pattern connected to the pole is formed. This provides a semiconductor device that can be easily miniaturized, easily conducts, and can realize high reliability in which extra damage is not applied to the diffusion layer.

The present invention is based on such knowledge, and an embodiment of the present invention will be described next with reference to the drawings.

FIGS. 1A to 1G are schematic sectional views showing a semiconductor device and a method of manufacturing the same according to the present invention in the order of steps.

First, as shown in FIG. 1A, a LOCOS (Local Oxidation of Silico)
An element isolation 4 made of a field oxide film is formed by the n) process. Thereafter, a gate oxide film (not shown) is formed on the surface of the silicon substrate 1, then the gate electrode 3 is formed, and thereafter, the oxide film 2 is formed on the upper surface and side surfaces of the gate electrode 3. Then, impurities are introduced into the surface of the silicon substrate 1 to form impurity regions 8 serving as a source region and a drain region on the surface of the silicon substrate 1.

Next, as shown in FIG. 1B, a flattened metal film 5 is formed over the entire surface of the substrate 1.

Thereafter, as shown in FIG. 1C, a resist is formed on the metal film 5 over the entire surface of the substrate 1, and is exposed and developed to selectively form a resist mask 6.

Then, as shown in FIG. 1D, the metal film 5 is etched using the resist mask 6 as an etching mask so that the impurity region 8 is not exposed, and the metal floor 52 and the metal pillar 51 thereon are formed. Is formed. The metal floor 52 is formed to cover the entire exposed portion of the impurity region 8 exposed between the field oxide film of the element isolation 4 and the oxide film 2 on the side surface of the gate electrode 3. It exists only in a region surrounded by the oxide film and the oxide film 2 on the side surface of the gate electrode 3. The projected area of the metal floor 52 is larger than the projected area of the metal pillar 51 thereon.

Thereafter, as shown in FIG. 1E, an interlayer insulating film 7 is formed on the entire surface of the silicon substrate 1.

After that, as shown in FIG. 1F, the interlayer insulating film 7 is etched to expose the metal pillar 51.

Thereafter, as shown in FIG. 1G, an on-metal wiring 54 connected to the metal pillar 51 is selectively formed on the interlayer insulating film 7.

The present embodiment has the following operations and effects.

1. The entire impurity region 8 such as a diffusion layer is
Since the third metal floor 52 covers the contact resistance, the contact resistance can be made very small (about one tenth of the contact resistance formed by a normal method).

2. When etching the metal film 5, the substrate 1
Is not etched, so that plasma damage to the substrate 1 is small.

3. When the resist mask 6 for forming the metal pillars 51 is formed on the metal film 5, the resist mask 6 is left as a pattern, so that the minimum processing size can be reduced as compared with the punched pattern. Exposure becomes possible.

4. Resist mask 6 for forming metal pillar 51
Is slightly applied to the gate electrode 3, the gate electrode 3
Since the oxide film 2 which is an insulating film already exists between the gate electrode 3 and the metal film 5, the contact with the substrate 1 can be established without causing a short circuit between the pole 51 and the gate electrode 3. Therefore, the mask overlay accuracy may be lower than in a normal method. On the other hand, according to the conventional method described with reference to FIG. 2, if the overlay accuracy is low when forming the resist mask 16 for forming the contact hole 171, if the subsequent resist mask 16 is used as a mask, the interlayer insulating film 17
When the contact hole 171 is formed by etching the gate electrode 3, the oxide film 2 formed on the top and side surfaces of the gate electrode 3 is etched, and a short circuit may occur between the contact wiring and the gate electrode 3.

5. When the metal film 5 is etched, unlike a normal contact hole forming step, the area to be etched is large, so that no etch stop occurs.

6. Since the metal pillars 51 are formed in advance and the interlayer insulating film 7 is formed thereafter, the technique of embedding metal in fine holes is unnecessary.

[0037]

According to the method of manufacturing a semiconductor device of the present invention, fine contact holes for connecting impurity regions of a substrate can be easily formed, damage to the substrate can be prevented during contact formation, and contact resistance can be reduced. it can. Further, according to the semiconductor device of the present invention, the contact resistance can be reduced even if the impurity regions of the substrate are connected by fine contact holes.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view for explaining a semiconductor device of the present invention and a method for manufacturing the same.

FIG. 2 is a schematic cross-sectional view for explaining a conventional semiconductor device and a method for manufacturing the same.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Oxide film 3 ... Gate electrode 4 ... Element isolation 5 ... Metal film 8 ... Impurity region 50 ... Metal wiring 51 ... Metal pillar 52 ... Metal floor 53 ... Electrode 54 ... Wiring on metal 6 ... Resist mask 7 ... Interlayer insulating film 100 ... Semiconductor device

Claims (7)

[Claims] An impurity region is formed on one main surface of a semiconductor substrate by exposing a part or all of the surface of the impurity region from the one main surface. Forming a conductive film covering a part or all of the exposed surface of the impurity region; and forming an etching mask, wherein the etching is performed when the one main surface is viewed from above the one main surface. Selectively forming an etching mask having a projected area of a mask smaller than an area where the impurity region is exposed, on the conductive film; and etching the conductive film using the etching mask as a mask to form an etching mask on the impurity region. A first sub-electrode and a second sub-electrode on the first sub-electrode, wherein the projection of the second sub-electrode when the one main surface is viewed from above the one main surface The area is the first sub The method of manufacturing a semiconductor device comprising: the step of forming a small second electrode and a secondary electrode than the projected area, characterized in that it comprises a. 2. The method according to claim 1, wherein the step of forming the conductive film comprises: forming the impurity region on the one main surface of the semiconductor substrate through an opening in an insulator formed on the one main surface; Forming the conductive film on the one main surface of the semiconductor substrate formed by exposing a part or the whole of the semiconductor substrate so as to cover at least a part of the impurity region exposed to the opening. Forming the first conductive layer in the opening of the insulator covering the entire surface of the portion of the impurity region exposed to the opening by etching the conductive film using the etching mask as a mask. And the second sub-electrode on the first sub-electrode has a projected area of the second sub-electrode when viewed from above the one main surface toward the one main surface. Than the projected area of the first sub-electrode The method of manufacturing a semiconductor device according to claim 1, characterized in that the step of forming the electrode and a again the second sub-electrode. 3. The first sub-electrode and the second sub-electrode are made of the same conductive material.
3. A method for manufacturing a semiconductor device according to item 2. 4. A step of forming a conductive film on the one main surface of the semiconductor substrate having an impurity region formed on one main surface of the semiconductor substrate, and a step of selectively forming an etching mask on the conductive film. And a step of etching the conductive film using the etching mask as a mask so that the impurity regions are not exposed. 5. A semiconductor substrate, comprising: an impurity region formed on one main surface of the semiconductor substrate; an electrode formed on the impurity region; and a columnar electrode formed on the electrode. A semiconductor device, wherein the projected area of the electrode is larger than the projected area of the columnar electrode when the one main surface is viewed from above the main surface. 6. An insulator formed on one main surface of said semiconductor substrate, said insulator having an opening exposing said impurity region, wherein said electrode is said opening in said impurity region. 7. The semiconductor device according to claim 6, wherein the semiconductor device is provided in the opening of the insulator so as to entirely cover a portion exposed to the semiconductor device. 7. The semiconductor device according to claim 5, wherein said electrode and said columnar electrode are made of the same conductive material.