JP2000058780A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To prevent deterioration of device characteristics as much as possible. SOLUTION: The present invention is characterized in that a surface of a trench formed in a semiconductor substrate of one conductivity type is subjected to hydrogen heat treatment. Further, the invention of the present application is characterized in that the impurity concentration of the one conductivity type semiconductor substrate is set lower than usual. Also,
The present invention is characterized in that an impurity of the opposite conductivity type is diffused from the trench to the semiconductor substrate of one conductivity type. Further, the present invention is characterized in that one-conductivity-type impurity is outwardly diffused from the vicinity of the trench by hydrogen heat treatment. Further, the present invention provides an insulating film 1 on a p-type silicon substrate 101.
03, 105, a step of forming the trench 109 by etching the insulating film and the silicon substrate, and a step of annealing in a predetermined reducing atmosphere.
It is characterized by having.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a trench and a method for manufacturing the same.

[0002]

2. Description of the Related Art A method of manufacturing a conventional semiconductor device having a trench, for example, a DRAM will be described. The trench here is used as a part of a trench capacitor in a DRAM.

[0003] First, as shown in FIG.
For example, a silicon oxide film 2 is formed to a thickness of about 8 nm on the upper surface of the p-type silicon substrate 1 by using a thermal oxidation method. Then, a silicon nitride film 3 having a thickness of 22 is formed on the upper surface of the silicon oxide film 2 by using a CVD (Chemical Vapor Deposition) method.
It is formed to about 0 nm. Further, a TEOS film 4 having a thickness of about 200 nm is formed on the upper surface of the silicon nitride film 3 by using the CVD method. Next, the TEOS film 4 is formed using a spin coating method.
(Not shown) is applied to the upper surface of the substrate. Next, this resist is patterned into a predetermined shape using a photolithography method. Using a resist (not shown) patterned in this predetermined shape as a mask, an anisotropic etching method such as RI
The TEOS film 4, the silicon nitride film 3, and the silicon oxide film 2 are etched into a predetermined shape by the E method. Thereby, a part of the upper surface of the p-type silicon substrate 1 is exposed. Further, using the TEOS film 4 as a mask, the p-type silicon substrate 1 is etched using an anisotropic etching method, for example, an RIE method. Thereby, a trench 5 is formed. Note that an n-type diffusion layer 6 is formed at a predetermined position on the p-type silicon substrate 1 in advance. The depth of the trench 5 is about 7 μm.

Next, as shown in FIG. 2, a film containing impurities, for example, an AsSG film 7 is formed on the entire surface to a thickness of about 30 nm by the CVD method. Further, a resist 8 is formed on the entire surface to a thickness of about several thousand nm using a spin coating method. Then, the resist 8 is removed to a predetermined depth of the trench 5 by using an exposure development method or a downflow etching method. Thereby, a part of the AsSG film 7 is exposed.

Next, as shown in FIG. 3, the exposed AsSG film 7 is removed by using a hydrofluoric acid-based wet etching method. Next, as shown in FIG. 4, the resist 8 is removed by an ashing method or a wet etching method. Then, a TEOS film 9 is formed on the entire surface by using the CVD method. The AsSG film 7 is covered with the TEOS film 9.

Next, as shown in FIG. 5, As contained in the AsSG film 7 is diffused from the side surface of the trench 5 into the p-type silicon substrate 1 by using a thermal diffusion method. As a result, an embedded plate 10 serving as a plate electrode is formed.
Here, the TEOS film 9 is formed by depositing As from the side of the trench 5 by p.
When diffusing into the silicon substrate 1, As
This is for preventing diffusion into the p-type silicon substrate 1 from a portion of the side surface of the trench 5 where the AsSG film 7 is not formed. Further, the TEOS film 9 and the AsSG film 7 are respectively removed by using a wet etching method.

Next, as shown in FIG. 6, an insulating film 11 is formed on the entire surface to a thickness of about several tens nm by using the CVD method. Here, the insulating film 11 is, for example, an NO film which is a composite film of a nitride film and an oxide film. Further, a dielectric film may be used instead of the insulating film 11. Further, the conductive film 12 is formed on the entire surface by using the CVD method.
As the conductive film 12, for example, a polysilicon film doped with an impurity is used.

Next, as shown in FIG. 7, a predetermined flattening process such as a CMP method or a predetermined etching process is performed.
The conductive film 12 is removed to a predetermined depth in the trench 5.
Thereby, a part of the insulating film 11 is exposed. On this occasion,
The TEOS film 4 will be removed.

Next, as shown in FIG. 8, the exposed insulating film 1 is etched using, for example, a phosphoric acid-based wet etching method.
Remove one. Next, as shown in FIG. 9, an insulating film, for example, a TEOS film 13 having a thickness of 3
It is formed to about 5 nm. The TEOS film 13 is for preventing the occurrence of a parasitic transistor, and needs to have a sufficient thickness. Then, the insulating film 13 is left only on the side surfaces of the trench 5 by using an anisotropic etching method, for example, an RIE method.

[0010] Next, as shown in FIG. 10, a conductive film 14 made of, for example, an arsenic-doped polycrystalline silicon film is used to fill the trench 5 with a thickness of several hundreds by using the CVD method. It is formed to a thickness of about nm. Then, the upper surface of the silicon nitride film 3 is flattened by a flattening process such as a CMP method. Then, the conductive film 14 is etched to a predetermined depth by using, for example, a downflow etching method.

Next, as shown in FIG. 11, the TEOS film 13 is etched to a predetermined depth using, for example, a wet etching method. Then, a conductive film 15 made of, for example, an arsenic-doped polycrystalline silicon film is formed on the entire surface to a thickness of about several hundred nm using the CVD method. And
The conductive film 15 is etched to a predetermined depth in the trench 5 by a predetermined planarization process such as a CMP method or a predetermined etching process.

Next, as shown in FIG. 12, the upper portion of the p-type silicon substrate 1 is etched into a predetermined shape by a predetermined etching process. Next, as shown in FIG.
An insulating film, for example, a TEOS film 16
Is formed to a thickness of about several hundred nm. Thereafter, the upper surface of the p-type silicon substrate 1 is planarized by using a predetermined etching process or a planarization process such as a CMP method. As a result, an element isolation region composed of the TEOS film 16 is formed.

Next, as shown in FIG. 14, a silicon oxide film 17 is formed to a thickness of 8 nm on the entire surface by using, for example, a thermal oxidation method.
Formed to the extent. This silicon oxide film 17 becomes a gate insulating film. Next, a polysilicon film 18 is formed to a thickness of about 100 nm on the entire surface by using the CVD method. Then, a tungsten silicide film 19 is formed to a thickness of about 55 nm on the upper surface of the polysilicon film 18 by using, for example, a sputtering method. Further, a silicon nitride film 20 is formed to a thickness of about 150 nm on the upper surface of the tungsten silicide film 19 by using, for example, a CVD method. Further, the silicon nitride film 2
An anisotropic etching method, for example, using an unillustrated resist patterned in a predetermined shape on the upper surface of
The silicon nitride film 20, the tungsten silicide film 19, and the polysilicon film 18 are etched by using the IE method. The silicon nitride film 20, the tungsten silicide film 19, and the polysilicon film 18 serve as gate electrodes.

Next, as shown in FIG. 15, a predetermined diffusion layer 21 is formed. Then, a silicon nitride film 22 is formed to a thickness of about 30 nm on the entire surface by using the CVD method. Further, an insulating film, for example, a BPSG film 23 is formed to a thickness of about 700 nm on the entire surface by using the CVD method. The BPSG film 23 is planarized by removing it to a thickness of about 100 nm above the silicon nitride film 20 by using a flattening process, for example, a CMP method. Then, an insulating film, for example, a TEOS film 24 is formed with a thickness of about 200 nm to 400 nm on the entire surface by using the CVD method. Further, the TEOS film 24 and the BPSG film 23 are etched into a predetermined shape to form a conductive film, for example, a polysilicon film 25 and a tungsten film 26 into a predetermined shape. Here, the polysilicon film 25 becomes a contact, and the tungsten film 26 becomes a first wiring layer.

As described above, the basic structure of the cell capacitor portion of the trench DRAM is formed. Here, a method in which the steps shown in FIGS. 2 to 5 are omitted and the buried plate 10 is not formed is also considered. In this case, the basic structure of the cell capacitor portion of the trench DRAM is as shown in FIG. This trench capacitor 27
Will be described. When a positive voltage is applied to the conductive film 12, the position of the p-type silicon substrate 1 opposing the conductive film 12 across the insulating film 11 becomes n-type. The n-type portion (not shown) becomes a plate electrode.

Next, FIG. 17 shows a plan view of a conventional semiconductor device having STI (Shallow Trench Isolation) used in, for example, a peripheral circuit portion of a DRAM, and FIG.
FIG. 18 shows a cross-sectional view taken along a line A ′, and a section line BB ′.
FIG. 19 shows a cross-sectional view taken along the line in FIG. This conventional semiconductor device has a MOS transistor structure, and has a gate electrode 33 formed on a semiconductor substrate 31 with a gate insulating film 32 interposed therebetween, and a diffusion region (source / source) formed so as to sandwich the gate electrode 33. Drain region) 34. The MOS transistor is electrically insulated from other elements by the STI 35. The STI 35 is formed by forming a trench in the semiconductor substrate 31 and filling the trench with an insulating film.

[0017]

First, FIG. 1 to FIG.
A problem in the manufacturing process of the DRAM as shown in FIG. FIG. 20 shows an enlarged view of a case where the buried plate 10 is formed and used as a plate electrode (see FIG. 15). This trench capacitor is formed by sandwiching an insulating film 11 between a conductive film 12 and a buried plate 10. Usually, the power supply voltage Vc is applied to the conductive film 12. Then, 埋 め 込 み of the power supply voltage, that is, Vc / 2 is applied to the embedded plate 10. Thereby, there is an advantage that the voltage applied to the insulating film 11 is reduced to の of the power supply voltage. However, the embedding plate 10
Is complicated, and there is a problem that it is difficult to control the structure. In addition, when a voltage is applied to the conductive film 14, there is a problem of occurrence of a parasitic transistor in which the diffusion layer 21 adjacent to the TEOS film 16 and the n-type diffusion layer 6 are electrically connected. This parasitic transistor is more likely to occur as the interface state density on the surface of the trench 5 increases. Since the interface state density is increased by etching damage generated on the surface of the trench when the trench 5 is formed, the occurrence of the parasitic transistor is promoted.

FIG. 21 is an enlarged view of the trench capacitor when the step of forming the buried plate 10 is omitted. In this trench capacitor, when a positive voltage is applied to the conductive film 12, the insulating film 11 of the p-type silicon substrate 1
The position opposing the conductive film 12 with n is sandwiched between the n-type. The n-type portion (not shown) becomes a plate electrode. In this case, there is an advantage that a complicated process for forming the embedded plate can be avoided. However, in order to prevent the occurrence of a parasitic diode leakage current between the n-type diffusion layer 6 and the silicon substrate 1 in a region adjacent to the insulating film 11, the potential of the n-type diffusion layer 6 and the potential of the silicon substrate 1 The substrate potential needs to be equal. That is, the potential of the n-type diffusion layer 6 is set to the ground potential. Normally, the power supply voltage Vc is applied to the conductive film 12. At this time, the potential of the plate electrode (not shown) generated at a position opposite to the conductive film 12 with the insulating film 11 interposed therebetween becomes the potential of the n-type diffusion layer 6, that is, the ground potential. Thus, the power supply voltage is applied to the insulating film 11 which is the capacitor insulating film of the trench capacitor as it is. Therefore, as compared with the case where the embedded plate 10 is formed as shown in FIG.
There is a problem that a double voltage is applied to the insulating film 11. In addition, when a voltage is applied to the conductive film 14,
A diffusion layer 21 adjacent to the TEOS film 16;
This causes a problem of generation of a parasitic transistor that is electrically connected. This parasitic transistor is more likely to occur as the interface state density on the surface of the trench 5 increases. Then, the interface state density increases due to etching damage generated on the trench surface when the trench 5 is formed. Therefore, the generation of the parasitic transistor is promoted. Also, the higher the interface state density, the more easily the parasitic diode leakage current between the n-type diffusion layer 6 and the silicon substrate 1 in the region adjacent to the insulating film 11 increases. These problems become more serious since the potential difference between the diffusion layer 21 and the n-type diffusion layer 6 is doubled as compared with the case where the buried plate 10 is formed. Then, with the miniaturization of the element, a more serious problem occurs. In addition, conductive film 1
If a positive voltage is not applied to 2, a depletion layer is generated between silicon substrate 1 and silicon substrate 1, which causes a problem of lowering the capacitance of the capacitor.

Next, as shown in FIGS.
For example, a problem in a manufacturing process of a conventional semiconductor device having an STI used in a peripheral circuit portion of a DRAM will be described.

In the conventional semiconductor device as shown in FIGS. 17 to 19, the STI
Corners 36a, 36b of the trench for forming
(See FIG. 18). As a result, a) the gate insulating film 32 of the MOSFET is thinned and the withstand voltage is deteriorated, and b) the MO due to the concentration of the electric field at the corner 36a is reduced.
There is a problem that the threshold value of the SFET is lowered and the cutoff characteristic is deteriorated.

Further, since the corners 36a and 36b of the trench for forming the STI 35 are sharp, when the insulating material is embedded in the trench to form the STI 35, the coverage of the insulating material is poor, as shown in FIG. Seam 4
There is a problem that 0 occurs. This seam 40 is
When forming an S transistor, the gate wiring is seam 4
This causes the problem of remaining at 0 and short-circuiting.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which prevent deterioration of element characteristics as much as possible.

[0023]

The present invention is characterized in that the surface of a trench formed in a semiconductor substrate of one conductivity type is subjected to a hydrogen heat treatment. Further, the invention of the present application is characterized in that the impurity concentration of the one conductivity type semiconductor substrate is set lower than usual.

Further, the present invention is characterized in that impurities of the opposite conductivity type are diffused from the trench to the semiconductor substrate of one conductivity type. In addition, the present invention, by hydrogen heat treatment,
The method is characterized in that one conductivity type impurity is diffused outward from the vicinity of the trench.

Further, according to the present invention, it is preferable that the one-conductivity-type impurity concentration from the bottom surface of the one-conductivity-type semiconductor substrate to a predetermined height is higher than the one-conductivity-type impurity concentration from the predetermined height to the top surface. Features.

Further, the present invention provides a step of forming a trench by forming an insulating film on a silicon substrate and then etching the insulating film and the silicon substrate.
Annealing in a predetermined reducing atmosphere.

Further, the present invention provides a method of forming a trench by forming an insulating film on a silicon substrate and then etching the insulating film and the silicon substrate.
Exposing the surface of the silicon substrate near the upper corner of the trench by etching a side portion of the insulating film remaining on the silicon substrate, and annealing in a predetermined reducing atmosphere; It is characterized by having.

Also, the present invention provides a method of forming a first substrate on a silicon substrate.
Forming a trench by etching the first insulating film and the silicon substrate, and depositing a second insulating film on the entire substrate so as to fill the trench. Etching the second insulating film until the surface of the first insulating film is exposed;
A step of removing the exposed first insulating film; and a step of annealing in a predetermined reducing atmosphere.

Further, according to the present invention, a step of forming a trench by etching a silicon substrate, and a step of depositing an insulating film over the entire surface of the substrate so as to fill the trench,
A step of etching the insulating film until the surface of the silicon substrate is exposed; and a step of annealing in a predetermined reducing atmosphere. Further, the reducing atmosphere has a pressure lower than the atmospheric pressure and a temperature of 900 ° C.
A temperature in the range of 1100 ° C. and a hydrogen concentration of 100%
The atmosphere is preferably

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings (FIGS. 22 to 37). Here, a DRAM will be described as an example of a semiconductor device having a trench. The trench here is used as a part of a trench capacitor in a DRAM.

First, as shown in FIG. 22, a silicon oxide film 52 is formed to a thickness of about 8 nm on the upper surface of a semiconductor substrate, for example, a p-type silicon substrate 51 by using a thermal oxidation method. Then, a silicon nitride film 5 is formed on the upper surface of the silicon oxide film 52 by using a CVD (Chemical Vapor Deposition) method.
3 is formed to a thickness of about 220 nm. Further, a TEOS film 54 is formed to a thickness of about 200 nm on the upper surface of the silicon nitride film 53 by using the CVD method. Next, a resist (not shown) is applied to the upper surface of the TEOS film 54 using a spin coating method. Next, this resist is patterned into a predetermined shape using a photolithography method. Using the resist (not shown) patterned in the predetermined shape as a mask, the TEOS film 54, the silicon nitride film 53, and the silicon oxide film 52 are etched into a predetermined shape by an anisotropic etching method, for example, an RIE method. Thereby, the p-type silicon substrate 51
A part of the upper surface of is exposed. Further, the p-type silicon substrate 51 is etched using an anisotropic etching method, for example, an RIE method using the TEOS film 54 as a mask. Thus, a trench 55 is formed. Note that an n-type diffusion layer 56 is formed at a predetermined position on the p-type silicon substrate 51 in advance. The depth of the trench 55 is, for example, 7
It is about μm.

Next, as shown in FIG. 23, a hydrogen heat treatment is performed. The conditions of the hydrogen heat treatment are, for example, 800 ° C.
At about 1000 ° C., the pressure is several Torr to several hundred Torr, and the processing time is several seconds to several tens of minutes, but is not limited thereto. Thereby, as shown in the enlarged view of FIG. 23, the etching damage 78 on the side surface of the trench 55 is removed. Then, by removing the etching damage 78, the unevenness of the shape of the side wall of the trench 55 is removed, and the interface state density can be reduced. By stabilizing the side surface of the trench 55 in this way, it is possible to suppress the occurrence of a parasitic transistor. In addition, it is possible to improve various electrical characteristics such as withstand voltage and reliability of the trench capacitor.

Next, as shown in FIG. 24, a film containing impurities, for example, an AsSG film 57 is formed on the entire surface by CVD.
Is formed to a thickness of about 30 nm. Further, a resist 58 is formed on the entire surface to a thickness of about several thousand nm using a spin coating method. Then, the resist 58 is removed to a predetermined depth of the trench 55 by using an exposure development method or a downflow etching method. Thereby, a part of the AsSG film 57 is exposed.

Next, as shown in FIG. 25, the exposed AsSG is etched using a hydrofluoric acid-based wet etching method.
The film 57 is removed. Next, as shown in FIG. 26, the resist 58 is removed by an ashing method or a wet etching method. Then, a TEOS film 59 is formed on the entire surface by using the CVD method. As a result of this TEOS film 59, AsSG
The membrane 57 is coated.

Next, as shown in FIG. 27, As contained in the AsSG film 57 is formed in the trench 55 by using a thermal diffusion method.
Is diffused into the p-type silicon substrate 51 from the side surface. Thus, a buried plate 60 serving as a plate electrode is formed. Here, the TEOS film 59 is formed by forming As into the trench 55.
When diffusing from the side surface of the substrate into the p-type silicon substrate 51, A
This is for preventing s from diffusing into the trench 55 and diffusing into the p-type silicon substrate 51 from a portion of the side surface of the trench 55 where the AsSG film 57 is not formed. Further, the TEOS film 59 and the AsSG film 57 are respectively removed by using a wet etching method.

Next, as shown in FIG. 28, an insulating film 61 is formed on the entire surface to a thickness of about several tens nm by using the CVD method. Here, as the insulating film 61, for example, an NO film which is a composite film of a nitride film and an oxide film is exemplified. Further, a dielectric film may be used instead of the insulating film 61. Further, a conductive film 62 is formed on the entire surface by using the CVD method.
As the conductive film 62, for example, a polysilicon film doped with an impurity can be given.

Next, as shown in FIG. 29, the conductive film 62 is removed to a predetermined depth in the trench 55 by a predetermined planarization process such as a CMP method or a predetermined etching process. Thereby, a part of the insulating film 61 is exposed. At this time, the TEOS film 54 is removed.

Next, as shown in FIG. 30, the exposed insulating film 61 is removed using, for example, a phosphoric acid-based wet etching method. Next, as shown in FIG.
An insulating film, for example, a TEOS film 63 is formed to a thickness of about 35 nm on the entire surface by using a method. The TEOS film 63 is for preventing the occurrence of a parasitic transistor, and needs to have a sufficient thickness. Then, the insulating film 63 is formed in the trench 55 by anisotropic etching, for example, RIE.
Leave only on the sides.

Next, as shown in FIG. 32, a conductive film 64 made of, for example, an arsenic-doped polycrystalline silicon film having a thickness of several hundreds It is formed to a thickness of about nm. Then, the upper surface of the silicon nitride film 53 is flattened by a flattening process such as a CMP method. Then, the conductive film 64 is etched to a predetermined depth by using, for example, a downflow etching method.

Next, as shown in FIG. 33, the TEOS film 63 is etched to a predetermined depth by using, for example, a wet etching method. Then, a conductive film 65 made of, for example, a polycrystalline silicon film doped with arsenic is formed on the entire surface to a thickness of about several hundred nm using the CVD method. And
The conductive film 65 is etched to a predetermined depth in the trench 55 by a predetermined planarization process such as a CMP method or a predetermined etching process.

Next, as shown in FIG. 34, the upper portion of the p-type silicon substrate 51 is etched into a predetermined shape by a predetermined etching process. Next, as shown in FIG. 35, an insulating film, for example, a TEOS film 66 is formed on the entire surface to a thickness of about several hundred nm by using the CVD method. After that, the upper surface of the p-type silicon substrate 51 is planarized by using a predetermined etching process or a planarization process such as a CMP method. Thus, an element isolation region composed of the TEOS film 66 is formed.

Next, as shown in FIG. 36, a silicon oxide film 67 having a thickness of 8 nm is formed on the entire surface by, for example, a thermal oxidation method.
Formed to the extent. This silicon oxide film 67 becomes a gate insulating film. Next, a polysilicon film 68 is formed to a thickness of about 100 nm on the entire surface by using the CVD method. Then, a tungsten silicide film 69 having a thickness of about 55 nm is formed on the upper surface of the polysilicon film 68 by using, for example, a sputtering method. Further, a silicon nitride film 70 is formed to a thickness of about 150 nm on the upper surface of the tungsten silicide film 69 by using, for example, a CVD method. Further, the silicon nitride film 7
An anisotropic etching method, for example, using an unillustrated resist patterned in a predetermined shape on the upper surface of
The silicon nitride film 70, the tungsten silicide film 69, and the polysilicon film 68 are etched by using the IE method. The silicon nitride film 70, the tungsten silicide film 69, and the polysilicon film 68 serve as gate electrodes.

Next, as shown in FIG. 37, a predetermined diffusion layer 71 is formed. Then, a silicon nitride film 72 is formed to a thickness of about 30 nm on the entire surface by using the CVD method. Further, an insulating film, for example, a BPSG film 73 is formed to a thickness of about 700 nm on the entire surface by using the CVD method. The BPSG film 73 is planarized by removing it to a thickness of about 100 nm above the silicon nitride film 70 using a planarization process, for example, a CMP method. Then, an insulating film, for example, a TEOS film 74 is formed with a thickness of about 200 nm to 400 nm on the entire surface by using the CVD method. Further, the TEOS film 74 and the BPSG film 73 are etched into a predetermined shape to form a conductive film, for example, a polysilicon film 75 and a tungsten film 76 into a predetermined shape. Here, the polysilicon film 75 becomes a contact, and the tungsten film 76 becomes a first wiring layer.

As described above, the basic structure of the cell capacitor portion of the trench DRAM is formed. Note that, instead of the steps shown in FIGS. 24 to 26, an n-type impurity, for example, As, may be diffused into a p-type silicon substrate by using a vapor phase diffusion method.

As described above, according to the first embodiment of the present invention, it is possible to prevent the characteristics of the device from deteriorating as much as possible. Then, by removing the etching damage 78 on the side surface of the trench 55 (see FIG. 23), it is possible to reduce the interface state density and suppress the occurrence of the parasitic transistor. In addition, it is possible to improve various electrical characteristics such as withstand voltage and reliability of the trench capacitor.

Next, a second embodiment of the present invention will be described with reference to the drawings (FIGS. 38 to 49). First,
As shown in FIG. 38, a silicon oxide film 52 is formed to a thickness of about 8 nm on the upper surface of a semiconductor substrate, for example, a p-type silicon substrate 51 by using a thermal oxidation method. And CVD (Ch
A silicon nitride film 53 is formed on the upper surface of the silicon oxide film 52 to a thickness of about 220 nm by using an emical vapor deposition (EM) method. Further, a TEOS film 54 is formed to a thickness of about 200 nm on the upper surface of the silicon nitride film 53 by using the CVD method. Next, a resist (not shown) is applied to the upper surface of the TEOS film 54 using a spin coating method. Next, this resist is patterned into a predetermined shape using a photolithography method.
Using the resist (not shown) patterned in the predetermined shape as a mask, the TEOS film 54, the silicon nitride film 53, and the silicon oxide film 52 are etched into a predetermined shape by an anisotropic etching method, for example, an RIE method. Thereby, a part of the upper surface of the p-type silicon substrate 51 is exposed. Further, using the TEOS film 54 as a mask, the p-type silicon
1 is etched. Thus, a trench 55 is formed. Note that an n-type diffusion layer 56 is formed at a predetermined position on the p-type silicon substrate 51 in advance. The depth of the trench 55 is, for example, about 7 μm.

Next, as shown in FIG. 39, a hydrogen heat treatment is performed. The conditions of the hydrogen heat treatment are, for example, 800 ° C.
At about 1000 ° C., the pressure is several Torr to several hundred Torr, and the processing time is several seconds to several tens of minutes, but is not limited thereto. Thereby, as shown in the enlarged view of FIG. 39, the etching damage 78 on the side surface of the trench 55 is removed. Then, by removing the etching damage 78, the unevenness of the shape of the side wall of the trench 55 is removed, and the interface state density can be reduced. This makes it possible to suppress the occurrence of parasitic transistors and the leakage current of parasitic diodes. In addition, it is possible to improve various electrical characteristics such as withstand voltage and reliability of the trench capacitor.

Next, as shown in FIG. 40, an insulating film 61 is formed to a thickness of about several tens nm on the entire surface by using the CVD method. Here, as the insulating film 61, for example, an NO film which is a composite film of a nitride film and an oxide film is exemplified. Further, a dielectric film may be used instead of the insulating film 61. Further, a conductive film 62 is formed on the entire surface by using the CVD method.
As the conductive film 62, for example, a polysilicon film doped with an impurity can be given.

Next, as shown in FIG. 41, the conductive film 62 is removed to a predetermined depth in the trench 55 by a predetermined flattening process such as a CMP method or a predetermined etching process. Thereby, a part of the insulating film 61 is exposed. At this time, the TEOS film 54 is removed.

Next, as shown in FIG. 42, the exposed insulating film 61 is removed by using, for example, a phosphoric acid-based wet etching method. Next, as shown in FIG.
An insulating film, for example, a TEOS film 63 is formed to a thickness of about 35 nm on the entire surface by using a method. The TEOS film 63 is for preventing the occurrence of a parasitic transistor, and needs to have a sufficient thickness. Then, the insulating film 63 is formed in the trench 55 by anisotropic etching, for example, RIE.
Leave only on the sides.

Next, as shown in FIG. 44, a conductive film 64 made of, for example, an arsenic-doped polycrystalline silicon film having a thickness several hundreds It is formed to a thickness of about nm. Then, the upper surface of the silicon nitride film 53 is flattened by a flattening process such as a CMP method. Then, the conductive film 64 is etched to a predetermined depth by using, for example, a downflow etching method.

Next, as shown in FIG. 45, the TEOS film 63 is etched to a predetermined depth using, for example, a wet etching method. Then, a conductive film 65 made of, for example, a polycrystalline silicon film doped with arsenic is formed on the entire surface to a thickness of about several hundred nm using the CVD method. And
The conductive film 65 is etched to a predetermined depth in the trench 55 by a predetermined planarization process such as a CMP method or a predetermined etching process.

Next, as shown in FIG. 46, the upper portion of the p-type silicon substrate 51 is etched into a predetermined shape by a predetermined etching process. Next, as shown in FIG. 47, an insulating film, for example, a TEOS film 66 is formed on the entire surface to a thickness of about several hundred nm by using the CVD method. After that, the upper surface of the p-type silicon substrate 51 is planarized by using a predetermined etching process or a planarization process such as a CMP method. Thus, an element isolation region composed of the TEOS film 66 is formed.

Next, as shown in FIG. 48, a silicon oxide film 67 having a thickness of 8 nm is formed on the entire surface by using, for example, a thermal oxidation method.
Formed to the extent. This silicon oxide film 67 becomes a gate insulating film. Next, a polysilicon film 68 is formed to a thickness of about 100 nm on the entire surface by using the CVD method. Then, a tungsten silicide film 69 having a thickness of about 55 nm is formed on the upper surface of the polysilicon film 68 by using, for example, a sputtering method. Further, a silicon nitride film 70 is formed to a thickness of about 150 nm on the upper surface of the tungsten silicide film 69 by using, for example, a CVD method. Further, the silicon nitride film 7
An anisotropic etching method, for example, using an unillustrated resist patterned in a predetermined shape on the upper surface of
The silicon nitride film 70, the tungsten silicide film 69, and the polysilicon film 68 are etched by using the IE method. The silicon nitride film 70, the tungsten silicide film 69, and the polysilicon film 68 serve as gate electrodes.

Next, as shown in FIG. 49, a predetermined diffusion layer 71 is formed. Then, a silicon nitride film 72 is formed to a thickness of about 30 nm on the entire surface by using the CVD method. Further, an insulating film, for example, a BPSG film 73 is formed to a thickness of about 700 nm on the entire surface by using the CVD method. The BPSG film 73 is planarized by removing it to a thickness of about 100 nm above the silicon nitride film 70 using a planarization process, for example, a CMP method. Then, an insulating film, for example, a TEOS film 74 is formed with a thickness of about 200 nm to 400 nm on the entire surface by using the CVD method. Further, the TEOS film 74 and the BPSG film 73 are etched into a predetermined shape to form a conductive film, for example, a polysilicon film 75 and a tungsten film 76 into a predetermined shape. Here, the polysilicon film 75 becomes a contact, and the tungsten film 76 becomes a first wiring layer.

As described above, the basic structure of the cell capacitor portion of the trench DRAM is formed. The structure of the trench capacitor 77 will be described. Conductive film 62
When a positive voltage is applied to the p-type silicon substrate 51,
The position opposing the conductive film 62 with the insulating film 61 interposed therebetween becomes the n-type. The n-type portion (not shown) becomes a plate electrode. Except for the capacitor section, it is the same as the first embodiment of the present invention.

As described above, according to the second embodiment of the present invention, it is possible to prevent the characteristics of the device from deteriorating as much as possible. Further, since the buried plate is not formed, it is possible to avoid complicated steps for forming the buried plate and difficulties in controlling the structure. Further, etching damage 7 on the side surface of the trench 55
By removing 8 (see FIG. 39), the interface state density can be reduced, and the occurrence of parasitic transistors can be suppressed. In addition, it is possible to improve various electrical characteristics such as withstand voltage and reliability of the trench capacitor. Further, it is possible to reduce a parasitic diode leak current between the n-type diffusion layer 56 and the p-type silicon substrate 51, which is generated in a region adjacent to the insulating film 61. Therefore, it is possible to keep the potential of the n-type diffusion layer 56 at Vc / 2, which is 1/2 of the power supply voltage Vc. As a result, the voltage applied to the insulating film 61 is reduced to 1 of the power supply voltage.
/ 2 can be reduced. At the same time, the capacitor insulating film can be made thinner, which is advantageous for miniaturization of elements. In addition, since the voltage applied to the conductive film 64 is also の of the power supply voltage, it is possible to further suppress the occurrence of the parasitic transistor.

Next, a third embodiment of the present invention will be described with reference to the drawings (FIGS. 38 to 49). The third embodiment of the present invention is the same as the second embodiment,
The substrate concentration of the p-type silicon substrate 51 is made lower than usual. Normal impurity concentration is 1 × 10 ¹⁵ (atom
s / cm ³ ) to about 1 × 10 ¹⁶ (atoms / cm ³ ). On the other hand, for example, the impurity concentration is set to 1 × 10
¹⁴ (atoms / cm ³ ) to 1 × 10 ¹⁵ (atoms
/ Cm ³ ). As shown in FIG. 49, also in the third embodiment, when a positive voltage is applied to the conductive film 62, the position of the p-type silicon substrate 51 opposed to the conductive film 62 with the insulating film 61 interposed therebetween. Becomes n-type. The n-type portion (not shown) serves as a plate electrode. However, if the substrate concentration of the p-type silicon substrate 51 is reduced as in the third embodiment, strong inversion in which the plate electrode is formed may occur. The effect of lowering the threshold can be obtained. Thus, it is possible to suppress the occurrence of a depletion layer between the insulating film 61 and the p-type silicon substrate 51 and a decrease in the capacitance of the capacitor.

The hydrogen heat treatment step already shown in FIG. 39 can be omitted. As described above, according to the third embodiment of the present invention, it is possible to prevent the characteristics of the device from deteriorating as much as possible. Further, since the buried plate is not formed, it is possible to avoid complicated steps for forming the buried plate and difficulties in controlling the structure. Further, by removing the etching damage 78 on the side surface of the trench 55 (see FIG. 39), the interface state potential can be reduced, and the occurrence of a parasitic transistor can be suppressed. In addition, it is possible to improve various electrical characteristics such as withstand voltage and reliability of the trench capacitor. Further, it is possible to reduce a parasitic diode leak current between the n-type diffusion layer 56 and the p-type silicon substrate 51, which is generated in a region adjacent to the insulating film 11. Therefore, it is possible to keep the potential of the n-type diffusion layer 56 at Vc / 2, which is 1/2 of the power supply voltage Vc. As a result, the voltage applied to the insulating film 61 can be reduced to 電源 of the power supply voltage.
At the same time, the capacitor insulating film can be made thinner, which is advantageous for miniaturization of elements. In addition, since the voltage applied to the conductive film 64 is also の of the power supply voltage, it is possible to further suppress the occurrence of the parasitic transistor. further,
It is possible to suppress the occurrence of a depletion layer between the insulating film 61 and the p-type silicon substrate 51 to reduce the capacitance of the capacitor.

Next, a fourth embodiment of the present invention will be described with reference to the drawings (FIGS. 38 to 49). According to the fourth embodiment of the present invention, the p-type silicon substrate 51 is formed from the surface of the trench 55 between the step already shown in FIG. 39 and the step already shown in FIG. 40 in the second embodiment. It diffuses a thin n-type impurity toward it. As a method for diffusing the n-type impurity, for example, a gas phase diffusion method can be mentioned. Examples of the n-type impurity include P (phosphorus) and A
s (arsenic) is considered. Also, the p-type silicon substrate 51
Substrate concentration from 1 × 10 ¹⁵ (atoms / cm ³ ) to 1
When it is about × 10 ¹⁶ (atoms / cm ³ ),
The concentration of this n-type impurity is 1 × 10 ¹⁶ (atoms / c
m ³ ) to about 1 × 10 ¹⁷ (atoms / cm ³ ). Here, the concentration of a p-type well region (not shown) formed in a later step is usually 1 × 10 ¹⁷ (atoms / cm ³ ).
This is sufficiently higher than the concentration of the n-type impurity. Therefore, even if the n-type impurity is diffused, the electric characteristics of the p-type well region are not affected.

When the n-type impurity is diffused using the solid-phase diffusion method, a film containing the n-type impurity is formed on the surface of the trench 55 by using, for example, a CVD method, and the n-type impurity is removed by heat treatment. Diffusion into the p-type silicon substrate 51.
Thereafter, the film containing the n-type impurity is removed using, for example, a wet etching method. By such a process, the n-type impurity is diffused.

Here, also in the fourth embodiment, as shown in FIG. 49, when a positive voltage is applied to conductive film 62, conductive film is sandwiched between insulating films 61 of p-type silicon substrate 51. The position opposing the film 62 becomes the n-type. The n-type portion (not shown) serves as a plate electrode. If a thin n-type impurity is diffused from the surface of the trench 55 toward the p-type silicon substrate 51 as in the fourth embodiment, The silicon substrate near the trench 55 has a thin n-type. Thereby, an effect of lowering the strong inversion threshold at which the plate electrode is formed can be obtained. Thus, it is possible to suppress the occurrence of a depletion layer between the insulating film 61 and the p-type silicon substrate 51 and a decrease in the capacitance of the capacitor.

The hydrogen heat treatment step already shown in FIG. 39 can be omitted. As described above, according to the fourth embodiment of the present invention, it is possible to prevent deterioration of the characteristics of the element as much as possible. Further, since the buried plate is not formed, it is possible to avoid complicated steps for forming the buried plate and difficulties in controlling the structure. Further, by removing the etching damage 78 on the side surface of the trench 55 (see FIG. 39), the interface state density can be reduced, and the occurrence of a parasitic transistor can be suppressed. In addition, it is possible to improve various electrical characteristics such as withstand voltage and reliability of the trench capacitor. Further, it is possible to reduce a parasitic diode leak current between the n-type diffusion layer 56 and the p-type silicon substrate 51, which is generated in a region adjacent to the insulating film 11. Therefore, it is possible to keep the potential of the n-type diffusion layer 56 at Vc / 2, which is 1/2 of the power supply voltage Vc. As a result, the voltage applied to the insulating film 61 can be reduced to 電源 of the power supply voltage.
At the same time, the capacitor insulating film can be made thinner, which is advantageous for miniaturization of elements. In addition, since the voltage applied to the conductive film 64 is also の of the power supply voltage, it is possible to further suppress the occurrence of the parasitic transistor. further,
It is possible to suppress the occurrence of a depletion layer between the insulating film 61 and the p-type silicon substrate 51 to reduce the capacitance of the capacitor.

Next, a fifth embodiment of the present invention will be described with reference to the drawings (FIGS. 38 to 49). In the fifth embodiment of the present invention, the p-type impurity is outwardly diffused from the surface of the trench 55 between the step already shown in FIG. 39 and the step already shown in FIG. 40 in the second embodiment. This is a step of performing a hydrogen heat treatment to a degree that is sufficient. The condition of the hydrogen heat treatment is, for example, 800 ° C. to 1000 ° C.
The pressure is several Torr to several hundred Torr, and the processing time is several seconds to several tens of minutes, but is not limited thereto.

Here, also in the fifth embodiment, as shown in FIG. 49, when a positive voltage is applied to conductive film 62, conductive film sandwiches insulating film 61 in p-type silicon substrate 51. The position opposing the film 62 becomes the n-type. The n-type portion (not shown) serves as a plate electrode. However, if a p-type impurity is outwardly diffused from the surface of the trench 55 by performing a high-temperature heat treatment as in the fifth embodiment, the In the vicinity of 55, the concentration of the p-type impurity decreases. Thereby, an effect of lowering the strong inversion threshold at which the plate electrode is formed can be obtained. This allows
It is possible to suppress the occurrence of a depletion layer between the insulating film 61 and the p-type silicon substrate 51 to reduce the capacitance of the capacitor. Further, the amount of the p-type impurity in the vicinity of the trench 55 of the p-type silicon substrate 51 becomes lower due to the outward diffusion of the p-type impurity in the vicinity of the trench 55. The concentration increases. Therefore, the portion other than the vicinity of the trench 55 of the p-type silicon substrate 51 has low resistance. In the third embodiment, the p-type silicon substrate 51 has a low p-type impurity concentration, whereas in the present embodiment, the p-type silicon substrate 5
1 can be kept high.
This makes it possible to obtain a latch-up suppression effect that can prevent the parasitic thyristor from turning on.

As described above, according to the fifth embodiment of the present invention, it is possible to prevent the element characteristics from deteriorating as much as possible. Further, since the buried plate is not formed, it is possible to avoid complicated steps for forming the buried plate and difficulties in controlling the structure. Further, etching damage 7 on the side surface of the trench 55
By removing 8 (see FIG. 39), the interface state density can be reduced, and the occurrence of parasitic transistors can be suppressed. In addition, it is possible to improve various electrical characteristics such as withstand voltage and reliability of the trench capacitor. Further, it is possible to reduce a parasitic diode leak current between the n-type diffusion layer 56 and the p-type silicon substrate 51, which is generated in a region adjacent to the insulating film 11. Therefore, it is possible to keep the potential of the n-type diffusion layer 56 at Vc / 2, which is 1/2 of the power supply voltage Vc. As a result, the voltage applied to the insulating film 61 is reduced to 1 of the power supply voltage.
/ 2 can be reduced. At the same time, the capacitor insulating film can be made thinner, which is advantageous for miniaturization of elements. In addition, since the voltage applied to the conductive film 64 is also の of the power supply voltage, it is possible to further suppress the occurrence of the parasitic transistor. Further, it is possible to suppress the occurrence of a depletion layer between the insulating film 61 and the p-type silicon substrate 51 to reduce the capacitance of the capacitor. Also, it is possible to obtain a latch-up suppression effect that can prevent the parasitic thyristor from turning on.

Next, a sixth embodiment of the present invention will be described with reference to the drawings (FIGS. 38 to 49). The sixth embodiment of the present invention is the same as the first to fifth embodiments, except that the p-type impurity has a higher concentration than the normal concentration on the silicon. The formed silicon substrate is used.

First, the p-type impurity concentration is higher than usual, for example, when the impurity concentration is 1 × 10 ¹⁸ (atoms / atom /
A p-type silicon film of about cm ³ ) to 1 × 10 ¹⁹ (atoms / cm ³ ) is formed. Next, the impurity concentration is set to a normal concentration, for example, 1 by using an epitaxial method (vapor phase growth method).
× 10 ¹⁵ (atoms / cm ³ ) to 1 × 10 ¹⁶ (atom
A p-type silicon film of about ms / cm ³ ) is formed to a thickness of about 1 μm, for example. With such a method, a p-type silicon substrate is formed. Then, by using this p-type silicon substrate, the basic structure of the memory cell portion of the DRAM is formed by the same steps as those of the first to fifth embodiments.

When such a p-type silicon substrate is used,
The concentration of the p-type impurity in the lower layer of the p-type silicon substrate 51 is high. Therefore, the lower part of the p-type silicon substrate 51 has low resistance. This makes it possible to obtain a latch-up suppression effect that can prevent the parasitic thyristor from turning on.

As described above, according to the sixth embodiment of the present invention, the effect of each of the first to fifth embodiments can be obtained. Further, it is possible to obtain a latch-up suppression effect that can prevent the parasitic thyristor from turning on.

Next, a seventh embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. This embodiment relates to a method for manufacturing a MOSFET. First, as shown in FIG. 50A, a surface of a p-type silicon substrate 101 is thermally oxidized to form a thermal oxide film 103 on the p-type silicon substrate 101. Thereafter, silicon nitride film 105 is deposited on thermal oxide film 103 by using a CVD method.

Next, as shown in FIG. 50B, a photoresist pattern 107 is formed on the silicon nitride film 105, and using the photoresist pattern 107 as a mask, the silicon nitride film 105, the thermal oxide film 103, and the p-type Type silicon substrate 101 is anisotropically etched, for example, RIE
(Reactive Ion-Etching) to form a shallow trench (Shallow Trench) 109.

The method of forming the trench 109 is not limited to the above method, and the following method is conceivable, although not shown. First, an insulating film and a mask material are formed on the silicon substrate 101. Then, the insulating film and the mask material are patterned into a predetermined shape by a photoresist pattern. Thereafter, using a mask material patterned into a predetermined shape as a mask, an anisotropic etching method such as R
The silicon substrate 101 is etched using the IE method.
Thus, a trench 109 is formed. At this time,
As the insulating film, a silicon nitride film or a silicon oxide film can be considered. It is also conceivable to form a thin thermal oxide film between the silicon substrate 101 and the insulating film.

Next, as shown in FIG. 51A, after removing the photoresist pattern 107, the side surfaces of the thermal oxide film 3 and the silicon nitride film 105 are retracted toward the center thereof using an HF / glycerin solution (FIG. 51A). FIG. 51 (b)). This exposes the substrate surface near the upper corner 112 of the trench 109 (see FIG. 51B).

Next, when the pressure is 100 Torr and the temperature is 100
By performing annealing in a reducing atmosphere at 0 ° C. and a hydrogen concentration of 100%, migration occurs on the surface of the p-type silicon substrate 101, and as shown in FIG. Round 112 and the lower corner 111.

Next, as shown in FIG. 52B, after the exposed surface of the trench 109 is oxidized to form an oxide film 113, the SiO2 film 115 is formed on the substrate by CVD (Chemical Vapor Deposition). Deposited on the entire surface, the trench 109 is buried. At this time, since the lower corner 111 of the trench 109 is rounded, the apparent aspect ratio (ratio of depth to width) of the trench 109 is reduced, and the embedding property is improved. Thereby, generation of the seam 40 can be suppressed.

Next, as shown in FIG.
(Chemical Mechanical Polishing) method using SiO
The two films 115 are polished until the surface of the silicon nitride film 105 is exposed. Subsequently, the silicon nitride film 105 is removed using a hot H3PO4 solution as shown in FIG.

Next, using a diluted HF solution, the thermal oxide film 103 is removed as shown in FIG. Subsequently, after an oxide film 117 having a thickness of, for example, 100 angstroms is formed on the exposed silicon substrate surface, ion implantation for forming a MOSFET is performed (see FIG. 54B).

Next, as shown in FIG.
After removing 7, the gate oxide film 123 is formed on the element formation region of the p-type silicon substrate 101 by, for example, placing it in an HC1 atmosphere at 900 ° C. (see FIG. 55B).
Subsequently, a film of a gate electrode material is deposited on the entire surface of the substrate, and the film is patterned to form a gate electrode 127 (see FIG. 55B). And this gate electrode 12
5 is used as a mask to form a source / drain region (not shown) by ion implantation into the element formation region.
The OS transistor is completed.

Here, FIG. 56 illustrates the steps already shown in FIG. In this step, by performing annealing under a predetermined condition, migration occurs on the surface of the p-type silicon substrate 101, and the upper corner 112 and the lower corner 111 of the trench 109 are rounded. At this time, the rounded curvature of the upper corner 112 of the trench 109 is the silicon nitride film 105 as shown in FIG.
It can be controlled by the retreat amount 130 of the thermal oxide film 103. Here, FIG. 57 (a) and FIG.
(A) shows a case where the retreat amount 130 is different from each other.
FIG. 57 (a) has a larger retreat amount 130 than that shown in FIG. 58 (a). When annealing is performed on each of these, FIGS. 57B and 58
The state shown in FIG. That is, FIG.
As shown in (b), the retreat amount 130 is large and the rounding curvature 131 is large. On the other hand, as shown in FIG. 58B, when the retreat amount 130 is small, the rounding curvature 133 becomes small. Here, the trench 1 is formed by annealing.
The rounded corners 112 and 111 of 09 are caused by the transition of the surface energy of the silicon substrate 101 to a stable state. In other words, it is caused by the surface tension and the force for aligning the crystal surfaces. When the crystal orientation of the silicon substrate 101 is (100),
This is a phenomenon that occurs when the crystal orientations of the corners 112 and 111 of the trench 109 are about to become (111). In the upper corner 112 of the trench 109, when the corner 112 is about to be rounded, the thermal oxide film 10 is formed.
3, the surface of the silicon substrate 101 is fixed. As a result, the thermal oxide film 103 and the silicon nitride film 10
It is possible to control the rounding curvature of the corner 112 depending on how far the 5 is retracted.

As described above, according to the manufacturing method of the present embodiment, since the upper corner 112 of trench 109 is rounded, electric field concentration is reduced and MOSF
It is possible to prevent lowering of the threshold value of ET and deterioration of cutoff characteristics.

In this embodiment, the corner 112 of the element formation region before the gate oxide film 123 is formed is rounded, and the crystal orientation of the exposed surface of the element formation region is (111). , The corner 112
, The gate oxide film 123 can be suppressed from being thinned, and the deterioration of the breakdown voltage can be suppressed.

Next, an eighth embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. The manufacturing method according to the eighth embodiment uses a MOSFE
In the method of manufacturing T, the process until the trench 109 is formed is performed in the same manner as the manufacturing method of the seventh embodiment shown in FIGS. 50 (a) and 50 (b). Subsequently, after removing the photoresist pattern 107 (see FIG. 50 (b)), the pressure becomes 1
00 Torr, temperature 1000 ° C, hydrogen concentration 100%
The lower corner 111 of the trench 109 is rounded by annealing in a reducing atmosphere (see FIG. 59A).

Next, as shown in FIG. 59 (b), after oxidizing the exposed surface of the trench 109 to form an oxide film 113, a SiO2 film 115 is deposited on the entire surface of the substrate by using the CVD method. The trench 109 is buried. At this time, since the lower corner 111 of the trench 109 is rounded, the apparent aspect ratio (ratio of depth to width) of the trench 109 is reduced, and the embedding property is improved. Thereby, generation of the seam 40 can be suppressed.

Next, as shown in FIG.
The SiO2 film 115 is polished by using an mechanical mechanical polishing method until the surface of the silicon nitride film 105 is exposed. Subsequently, using hot H3PO4 solution, FIG.
The silicon nitride film 105 is removed as shown in FIG.

Next, as shown in FIG. 61A, the thermal oxide film 103 is removed using a dilute HF solution. Subsequently, after an oxide film 117 having a thickness of, for example, 100 Å is formed on the exposed silicon substrate surface, ion implantation is performed to form a MOSFET (see FIG. 61B).

Next, as shown in FIG.
After removing 7, a gate oxide film 123 is formed on the element formation region of the p-type silicon substrate 101 by, for example, placing the substrate in an HC1 atmosphere at 900 ° C. (see FIG. 62B).
Subsequently, a film of a gate electrode material is deposited on the entire surface of the substrate, and the film is patterned to form a gate electrode 127 (see FIG. 62B). And this gate electrode 12
5 is used as a mask to form a source / drain region (not shown) by ion implantation into the element formation region.
The OS transistor is completed.

As described above, according to the manufacturing method of this embodiment, since the lower corner 111 of the trench 109 is rounded, the apparent aspect ratio of the trench 109 is reduced, and the embedding property is improved. Thus, the generation of the seam 40 can be suppressed.

Next, a ninth embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. The ninth embodiment relates to a method for manufacturing a MOSFET, and FIG.
This is performed in the same manner as in the manufacturing steps of the seventh embodiment shown in FIGS. Subsequently, the photoresist pattern 107
After removing (see FIG. 50 (b)), as shown in FIG. 63 (b), the exposed surface of the trench 109 is oxidized to form an oxide film 113, and then CVD (Chemical Vapor).
An SiO2 film 115 is deposited on the entire surface of the substrate by using a deposition method, and the trench 109 is buried.

Next, as shown in FIG.
The SiO2 film 115 is polished by using an mechanical mechanical polishing method until the surface of the silicon nitride film 105 is exposed. Subsequently, using hot H3PO4 solution, FIG.
The silicon nitride film 105 is removed as shown in FIG.

Next, using a diluted HF solution, the thermal oxide film 103 is removed as shown in FIG. Next, when the pressure is 100
By performing annealing in a reducing atmosphere having a Torr temperature of 1000 ° C. and a hydrogen concentration of 100%, migration occurs on the surface of the p-type silicon substrate 101, and as shown in FIG. The upper corner 112 is rounded.

Next, after an oxide film 117 having a thickness of, for example, 100 angstroms is formed on the exposed surface of the silicon substrate, ion implantation for forming a MOSFET is performed (see FIG. 66A).

Next, as shown in FIG.
After removing 7, the gate oxide film 123 is formed on the element formation region of the p-type silicon substrate 101 by, for example, placing it in an HC1 atmosphere at 900 ° C. (see FIG. 67). Subsequently, a film of a gate electrode material is deposited on the entire surface of the substrate, and this film is patterned to form a gate electrode 127 (see FIG. 67). Then, ions are implanted into the element formation region using the gate electrode 125 as a mask, so that the source
A drain region (not shown) is formed to complete a MOS transistor.

As described above, according to the manufacturing method of the present embodiment, since the upper corner 112 of trench 109 is rounded, electric field concentration is reduced, and MOSF
It is possible to prevent the threshold of ET from being lowered and the cutoff characteristic from being deteriorated.

In this embodiment, the corner 112 of the element formation region before the gate oxide film 123 is formed is rounded, and the crystal orientation of the exposed surface of the element formation region is (111). , The corner 112
, The gate oxide film 123 can be suppressed from being thinned, and the deterioration of the breakdown voltage can be suppressed.

In the seventh to ninth embodiments, the reducing atmosphere conditions for rounding the corners of the trench 109 were a pressure of 100 Torr, a temperature of 1000 ° C., and a hydrogen concentration of 100%. If the pressure is lower than the atmospheric pressure, the corner can be similarly rounded. The temperature is 9
The same effect can be obtained if it is in the range of 00 ° C to 1100 ° C. At this time, it is desirable that the natural oxide film having a thickness of about several nm formed on the trench surface is removed.

In the seventh to ninth embodiments, the STI 115 is used as an element isolation insulating film of a MOSFET. However, the present invention is not limited to this.
Needless to say, it can be used for an STI of a bipolar transistor and an STI of a general semiconductor device.

Note that, in the ninth embodiment, the trench 10
Although the manufacturing method was a case where the upper corner of the trench 9 was rounded, the rounding of the upper corner of the trench may be performed as follows.

After forming a first insulating film on a silicon substrate, a trench is formed in the silicon substrate by etching the first insulating film and the silicon substrate. Subsequently, a second layer is formed on the entire surface of the substrate so as to fill the trench.
Is deposited. Then, the second insulating film is etched until the silicon substrate is exposed. At this time, the first insulating film is removed with the etching of the second insulating film. Thereafter, the upper corner portion of the trench is rounded by annealing in a predetermined reducing atmosphere. Note that the above-described method may be performed without forming the first insulating film over the silicon substrate.

[0100]

As described above, according to the present invention, it is possible to prevent the characteristics of the element from deteriorating as much as possible.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 2 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 4 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 6 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 9 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 10 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 13 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 14 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 15 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 16 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 17 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

18 is a cross-sectional view of the conventional semiconductor device when cut along a cutting line AA 'shown in FIG.

19 is a cross-sectional view of the conventional semiconductor device when cut along a cutting line BB 'shown in FIG.

FIG. 20 is a sectional view of a semiconductor device according to a conventional technique.

FIG. 21 is a sectional view of a semiconductor device according to a conventional technique.

FIG. 22 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 23 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 24 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 25 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 26 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 27 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 28 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 29 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 30 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 31 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 32 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 33 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 34 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 35 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 36 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 37 is a sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 38 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 39 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 40 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 41 is a sectional view of a semiconductor device according to a second embodiment of the present invention in the manufacturing process.

FIG. 42 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 43 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 44 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 45 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 46 is a manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the present invention;

FIG. 47 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 48 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention;

FIG. 49 is a manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the present invention;

FIG. 50 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 51 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 52 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 53 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 54 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 55 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 56 is a manufacturing process sectional view of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 57 is a sectional view showing the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 58 is a process cross-sectional view of the semiconductor device according to the seventh embodiment of the present invention;

FIG. 59 is a sectional view showing the manufacturing process of the semiconductor device according to the eighth embodiment of the present invention;

FIG. 60 is a sectional view showing the manufacturing process of the semiconductor device according to the eighth embodiment of the present invention;

FIG. 61 is a sectional view showing the manufacturing process of the semiconductor device according to the eighth embodiment of the present invention;

FIG. 62 is a sectional view showing the manufacturing process of the semiconductor device according to the eighth embodiment of the present invention;

FIG. 63 is a sectional view showing the manufacturing process of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 64 is a manufacturing process sectional view of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 65 is a sectional view of the manufacturing process of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 66 is a sectional view showing the manufacturing process of the semiconductor device according to the ninth embodiment of the present invention;

FIG. 67 is a sectional view showing the manufacturing process of the semiconductor device according to the ninth embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... silicon oxide film 3 ... silicon nitride film 4 ... TEOS film 5 ... trench 6 ... n-type diffusion layer 7 ... ··· AsSG film 8 ··· Resist 9 ··· TEOS film 10 ··· Buried plate 11 ··· Insulating film 12 ··· Conductive film 13 ··· TEOS film 14 ··· Conductive film 15 Conductive film 16 TEOS film 17 Silicon oxide film 18 Polysilicon film 19 Tungsten silicide film 20 Silicon nitride film 21 ... Diffusion layer 22 ... Silicon nitride film 23 ... BPSG film 24 ... TEOS film 25 ... Polysilicon film 26 ... Tungsten film 27 ... Trench capacitor 31 .... Semiconductor substrate 32 ... ..Gate insulating film 33 ... Gate electrode 34 ... Diffusion area 35 ... STI 36a ... Corner 36b ... Corner 40 ... Seam 51 ... p-type silicon substrate 52... silicon oxide film 53... silicon nitride film 54... TEOS film 55... trench 56... n-type diffusion layer 57... AsSG film 58 ··· Resist 59 ··· TEOS film 60 ··· Buried plate 61 ··· Insulating film 62 ··· Conductive film 63 ··· TEOS film 64 ··· Conductive film 65 ··· ··· Conductive film 66 ··· TEOS film 67 ··· Silicon oxide film 68 ··· Polysilicon film 69 ··· Tungsten silicide film 70 ··· Silicon nitride film 71 ··· Diffusion layer (N-type) 72 ... silicon nitride film 73 BPSG film 74 TEOS film 75 Polysilicon film 76 Tungsten film 77 Trench capacitor 78 Etching damage 101 Silicon substrate 103 ··· Thermal oxide film 105 ··· Silicon nitride film 107 ··· Photoresist pattern 109 ··· Trench 111 ··· Corner 112 ··· Corner 113 ··· Oxidation Film 115 ··· STI 123 ··· Gate oxide film 125 ··· Gate electrode 130 ··· Regression amount 131 ··· Rounding curvature 132 ··· Rounding curvature 133 ··· Rounding curvature

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Satoshi Matsuda 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Yoshitaka Tsunashima 8th Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa (72) Inventor Ichiro Mizushima, Kanagawa Prefecture, Yokohama, 8th, Shinsugita-cho, Isogo-ku, Kanagawa Prefecture Inside Toshiba Yokohama Office (72) Inventor Riki Sato, 8-8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa, Japan Toshiba Corporation Inside Yokohama Office (72) Inventor Koichi Kishi 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 5F040 DC01 EC02 EC07 EK05 EM04 EM06 FC10 FC12 FC21 FC22 5F083 AD15 AD17 GA21 JA03 JA35 JA53 NA01 PR03 PR05 PR06 PR12 PR40

Claims (22)

[Claims] An impurity concentration of one conductivity type is 1 × 10 ¹⁵ (at.
oms / cm ³ ) or less, a trench formed from a predetermined position on the upper surface of the one conductivity type semiconductor substrate to a predetermined depth, and a first formed on a surface extending from the bottom surface of the trench to a first height. An insulating film, a side surface of the trench, a second insulating film formed from an upper surface of the first insulating film to a second height, and formed at a predetermined position of the one conductivity type semiconductor substrate. An element isolation region, a first conductive film formed in the trench, a first opposite conductivity type diffusion layer electrically connected to the first conductive film, A gate electrode formed at a predetermined position on the upper surface; a second opposite conductivity type diffusion layer electrically connected to the first opposite conductivity type diffusion layer by the gate electrode; and the second opposite conductivity type Electrically connected to the diffusion layer and electrically connected to external circuits The semiconductor device characterized by comprising a second conductive film to be continued. 2. An impurity concentration of 1 × 10 ¹⁵ (atoms / atom /
cm ³ ) or less, a step of forming a trench having a predetermined depth in a semiconductor substrate of one conductivity type, a step of forming a first insulating film over the entire surface, and a step of forming a first conductive film over the entire surface. A step of removing the first conductive film to a predetermined depth of the trench; a step of removing the first insulating film to a predetermined depth of the trench; Forming a second insulating film from the upper surface of the film to a predetermined height; forming a second conductive film from the upper surface of the first conductive film in the trench to a predetermined height; Forming a device isolation region at a predetermined position on a semiconductor substrate; and forming an information transfer transistor on an upper surface of the one conductivity type semiconductor substrate. 3. An impurity concentration of one conductivity type is 1 × 10 ¹⁵ (at.
oms / cm ³ ) or less, a trench formed from a predetermined position on the upper surface of the one conductivity type semiconductor substrate to a predetermined depth and having a smoothed surface, and a surface from the bottom surface of the trench to a first height. A first insulating film formed on a side surface of the trench, a second insulating film formed from an upper surface of the first insulating film to a second height, and the one-conductivity-type semiconductor substrate. An element isolation region formed at a predetermined position, a first conductive film formed in the trench, a first opposite conductivity type diffusion layer electrically connected to the first conductive film, A gate electrode formed at a predetermined position on the upper surface of the one conductivity type semiconductor substrate; a second opposite conductivity type diffusion layer electrically connected to the first opposite conductivity type diffusion layer by the gate electrode; Electrically connected to the second opposite conductivity type diffusion layer It is a semiconductor device characterized by comprising a second conductive film electrically connected to an external circuit. 4. An impurity concentration of 1 × 10 ¹⁵ (atoms / atom /
cm.sup.3) or less, a step of forming a trench having a predetermined depth in a one-conductivity-type semiconductor substrate of not more than ³ cm. Forming a first conductive film, removing the first conductive film to a predetermined depth of the trench, removing the first insulating film to a predetermined depth of the trench, Forming a second insulating film from the upper surface of the first insulating film to a predetermined height from the side surface of the trench; and forming a second insulating film from the upper surface of the first conductive film to a predetermined height from the upper surface of the trench. Forming a conductive film, forming an element isolation region at a predetermined position on the one conductivity type semiconductor substrate, and forming an information transfer transistor on an upper surface of the one conductivity type semiconductor substrate. It is characterized by Method of manufacturing a semiconductor device that. 5. A trench formed from a predetermined position on the upper surface of the one-conductivity-type semiconductor substrate to a predetermined depth, and a concentration which diffuses into the one-conductivity-type semiconductor substrate and increases in distance from an interface with the trench. An impurity of the opposite conductivity type to be thinned; a first insulating film formed on a surface from a bottom surface of the trench to a substantially first height; and a side surface of the trench, and a second insulating film formed from a top surface of the first insulating film. A second insulating film formed up to a second height, an element isolation region formed at a predetermined position on the one conductivity type semiconductor substrate, a first conductive film formed in the trench, A first opposite conductivity type diffusion layer electrically connected to the one conductive film; a gate electrode formed at a predetermined position on an upper surface of the one conductivity type semiconductor substrate; Electrical contact with conductive diffusion layer A second conductive type diffusion layer, and a second conductive film electrically connected to the second conductive type diffusion layer and electrically connected to an external circuit. Semiconductor device. 6. A step of forming a trench having a predetermined depth in the one-conductivity-type semiconductor substrate, wherein the opposite-conductivity-type impurity concentration of the one-conductivity-type semiconductor substrate decreases as the distance from the interface with the trench decreases. Diffusing an impurity of the opposite conductivity type from the surface of the trench toward the one conductivity type semiconductor substrate; forming a first insulating film over the entire surface; forming a first conductive film over the entire surface; Removing the first conductive film to a predetermined depth of the trench; removing the first insulating film to a predetermined depth of the trench; and removing the first insulating film from the side surfaces of the trench. A step of forming a second insulating film from an upper surface to a predetermined height, a step of forming a second conductive film from the upper surface of the first conductive film in the trench to a predetermined height, and the one conductivity type semiconductor Base The method of manufacturing a step of forming an isolation region in a predetermined position, the semiconductor device characterized by comprising a step of forming a top surface in the information transfer transistors of the one conductivity type semiconductor substrate. 7. A trench formed from a predetermined position on an upper surface of the one-conductivity-type semiconductor substrate to a predetermined depth and having a smoothed surface; and a trench diffused into the one-conductivity-type semiconductor substrate; An impurity of the opposite conductivity type, the concentration of which decreases as the distance from the interface increases; a first insulating film formed on a surface from a bottom surface of the trench to a substantially first height; and a side surface of the trench, A second insulating film formed from the upper surface of the insulating film to a second height, an element isolation region formed at a predetermined position on the one conductivity type semiconductor substrate, and a first formed in the trench. A first conductive type diffusion layer electrically connected to the first conductive film; a gate electrode formed at a predetermined position on an upper surface of the one conductive type semiconductor substrate; The first opposite by the electrode A second opposite-conductivity-type diffusion layer electrically connected to the electric-type diffusion layer; and a second conductor electrically connected to the second opposite-conductivity-type diffusion layer and electrically connected to an external circuit. And a film. 8. A step of forming a trench having a predetermined depth in the one-conductivity-type semiconductor substrate, a step of performing a hydrogen heat treatment on a surface of the trench, and a step of setting the opposite-conductivity-type impurity concentration of the one-conductivity-type semiconductor substrate to the trench. Diffusing an impurity of the opposite conductivity type from the surface of the trench toward the semiconductor substrate of the one conductivity type so as to become thinner as the distance from the interface increases; forming a first insulating film on the entire surface; Forming one conductive film; removing the first conductive film to a predetermined depth of the trench; removing the first insulating film to a predetermined depth of the trench; Forming a second insulating film from the upper surface of the first insulating film to a predetermined height from the side surface of the second conductive film; and forming a second conductive film from the upper surface of the first conductive film to a predetermined height from the upper surface of the trench. Forming a film; forming an element isolation region at a predetermined position on the one conductivity type semiconductor substrate; and forming an information transfer transistor on an upper surface of the one conductivity type semiconductor substrate. A method for manufacturing a semiconductor device, comprising: 9. A trench formed from a predetermined position on an upper surface of the one conductivity type semiconductor substrate to a predetermined depth, a first insulating film formed on a surface from the bottom surface of the trench to a first height. A second insulating film formed on a side surface of the trench from the upper surface of the first insulating film to a second height, and an element isolation formed at a predetermined position of the one conductivity type semiconductor substrate A region, a first conductive film formed in the trench, a first opposite conductivity type diffusion layer electrically connected to the first conductive film, and a predetermined upper surface of the one conductivity type semiconductor substrate. And a second opposite conductivity type diffusion layer electrically connected to the first opposite conductivity type diffusion layer by the gate electrode, and the second opposite conductivity type diffusion layer. Second electrically connected to an external circuit Conductive films have provided a one conductivity type impurity concentration of the one conductivity type semiconductor substrate is a semiconductor device characterized by comprising darker away from the trench. 10. A step of forming a trench having a predetermined depth in a semiconductor substrate of one conductivity type, and performing a hydrogen heat treatment on a surface of the trench to remove impurities of one conductivity type contained in the semiconductor substrate of one conductivity type. Diffusing, forming a first insulating film on the entire surface, forming a first conductive film on the entire surface, removing the first conductive film to a predetermined depth of the trench, Removing the first insulating film to a predetermined depth of the trench; forming a second insulating film from the upper surface of the first insulating film to a predetermined height on a side surface of the trench; Forming a second conductive film from the upper surface of the first conductive film to a predetermined height in the trench; forming an element isolation region at a predetermined position on the one conductivity type semiconductor substrate; Information on the top of the Forming a data transfer transistor. 11. A trench formed from a predetermined position on an upper surface of the one conductivity type semiconductor substrate to a predetermined depth and having a smoothed surface, and a trench formed from a bottom surface of the trench to approximately a first height. A first insulating film, a second insulating film formed on a side surface of the trench, from an upper surface of the first insulating film to a second height, and a predetermined one of the one conductivity type semiconductor substrate. An element isolation region formed at a position; a first conductive film formed in the trench; a first opposite conductivity type diffusion layer electrically connected to the first conductive film; A gate electrode formed at a predetermined position on the upper surface of the type semiconductor substrate; a second opposite conductivity type diffusion layer electrically connected to the first opposite conductivity type diffusion layer by the gate electrode; Electrically connected to the diffusion layer of the opposite conductivity type And optionally comprising a second conductive film electrically connected, a semiconductor device in which one conductivity type impurity concentration of the one conductivity type semiconductor substrate is characterized in that it is low in the vicinity of the trench. 12. A trench formed from a predetermined position on the upper surface of the one conductivity type semiconductor substrate to a predetermined depth and having a smoothed surface, and a trench formed from a bottom surface of the trench to approximately a first height. A first insulating film, a buried plate formed in the one conductivity type semiconductor substrate at a position opposing the first insulating film, and a side surface of the trench, wherein the first insulating A second insulating film formed from the upper surface of the film to a second height, an element isolation region formed at a predetermined position of the one conductivity type semiconductor substrate, and a first conductive film formed in the trench. A film, a first opposite conductivity type diffusion layer electrically connected to the first conductive film, a gate electrode formed at a predetermined position on an upper surface of the one conductivity type semiconductor substrate, and the gate electrode The first opposite conductivity type diffusion layer and A second conductive layer that is electrically connected to the second conductive layer, and a second conductive film that is electrically connected to the second conductive layer and electrically connected to an external circuit. A semiconductor device characterized by the above-mentioned. 13. A step of forming a trench having a predetermined depth in a semiconductor substrate of one conductivity type, a step of performing a hydrogen heat treatment on a surface of the trench, and a step of forming the one conductivity type from a surface from a bottom surface of the trench to a predetermined height. Forming a buried plate by diffusing an impurity of the opposite conductivity type toward the type semiconductor substrate; forming a first insulating film over the entire surface; forming a first conductive film over the entire surface; Removing one conductive film to a predetermined depth of the trench; removing the first insulating film to a predetermined depth of the trench; and an upper surface of the first insulating film among side surfaces of the trench Forming a second insulating film from the upper surface of the first conductive film to a predetermined height in the trench; forming the second conductive film from the upper surface of the first conductive film to a predetermined height in the trench; of A method of manufacturing a semiconductor device, comprising: a step of forming an element isolation region at a predetermined position; and a step of forming an information transfer transistor on an upper surface of the one conductivity type semiconductor substrate. 14. A trench formed from a predetermined position on the upper surface of the one-conductivity-type semiconductor substrate to a predetermined depth and having a smoothed surface, and a trench formed from a bottom surface of the trench to approximately a first height. A first insulating film, a second insulating film formed on a side surface of the trench, from an upper surface of the first insulating film to a second height, and a predetermined one of the one conductivity type semiconductor substrate. An element isolation region formed at a position; a first conductive film formed in the trench; a first opposite conductivity type diffusion layer electrically connected to the first conductive film; A gate electrode formed at a predetermined position on the upper surface of the type semiconductor substrate; a second opposite conductivity type diffusion layer electrically connected to the first opposite conductivity type diffusion layer by the gate electrode; Electrically connected to the diffusion layer of the opposite conductivity type The semiconductor device characterized by comprising a second conductive film electrically connected with. 15. A step of forming a trench having a predetermined depth in a semiconductor substrate of one conductivity type; a step of performing a hydrogen heat treatment on a surface of the trench; a step of forming a first insulating film on the entire surface; Forming a first conductive film; removing the first conductive film to a predetermined depth of the trench; removing the first insulating film to a predetermined depth of the trench; Forming a second insulating film from the upper surface of the first insulating film on the side surface of the trench to a predetermined height, and forming a second conductive film from the upper surface of the first conductive film on the trench to a predetermined height. Forming a film; forming an element isolation region at a predetermined position on the one conductivity type semiconductor substrate; and forming an information transfer transistor on an upper surface of the one conductivity type semiconductor substrate. Characterized by A method for manufacturing a semiconductor device. 16. The one-conductivity-type impurity concentration from the bottom surface of the one-conductivity-type semiconductor substrate to a predetermined height is higher than the one-conductivity-type impurity concentration from the predetermined height to the top surface. Claims 1, 3, 5, 7, 9, 11, 1
16. The semiconductor device according to items 3 and 15. 17. The semiconductor device according to claim 17, wherein a concentration of the impurity of one conductivity type from the bottom surface of the one conductivity type semiconductor substrate to a predetermined height is higher than a concentration of the impurity of one conductivity type from the predetermined height to the top surface. Claims 2, 4, 6, 8, 10, 12, 1
5. The method for manufacturing a semiconductor device according to item 4. 18. A method comprising the steps of: forming an insulating film on a silicon substrate, forming a trench by etching the insulating film and the silicon substrate, and annealing in a predetermined reducing atmosphere. A method for manufacturing a semiconductor device. 19. forming a trench by forming an insulating film on a silicon substrate and then etching the insulating film and the silicon substrate; and forming a side portion of the insulating film remaining on the silicon substrate. A step of exposing a surface of the silicon substrate in the vicinity of an upper corner of the trench by etching the substrate, and a step of annealing in a predetermined reducing atmosphere. 20. A step of forming a trench by forming a first insulating film on a silicon substrate and then etching the first insulating film and the silicon substrate; and forming an entire surface of the substrate so as to fill the trench. Depositing a second insulating film on the first insulating film, etching the second insulating film until the surface of the first insulating film is exposed, and removing the exposed first insulating film. And a step of annealing in a predetermined reducing atmosphere. 21. A step of forming a trench by etching a silicon substrate, and depositing an insulating film on the entire surface of the substrate so as to fill the trench, and then etching the insulating film until the surface of the silicon substrate is exposed. And a step of annealing in a predetermined reducing atmosphere. 22. The reducing atmosphere, wherein the pressure is lower than the atmospheric pressure, the temperature is in the range of 900 ° C. to 1100 ° C., and the hydrogen concentration is 100%. The method for manufacturing a semiconductor device according to any one of the above.