JP2000049332A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which punch-through resistance is enhanced by suppressing short-channel effect and a fabrication method thereof. SOLUTION: A well region is formed by implanting impurity ions through a silicon oxide film formed on one major surface of a single-crystal silicon substrate 1 and then performing annealing. P-type impurity ions are then implanted at a part for forming an LOCOS film 2 using a resist mask. Subsequently, a silicon nitride film is formed on the silicon oxide film, and an LOCOS film 2 is formed using the silicon nitride film having an opening as a mask before removing the resist film, the silicon nitride film and the silicon oxide film. Thereafter, a tapered trench 4 is made in a part for forming an insulating gate 6 through photolithography and etching before forming the insulating gate 6 of polysilicon layer in the trench 4 through the silicon oxide film 5. Finally, a drain region 8 and a source region 9 having an impurity concentration gradient in the lateral direction are formed by conducting ion implantation and annealing, using the insulating gate 6 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art As the degree of integration of analog / digital ICs is increased, it is important to reduce the power consumption and speed of devices. For this reason, device miniaturization is rapidly progressing, but deterioration of device characteristics due to hot electrons has become a problem.

As a method of solving the above problem, a method of forming a concentration gradient near the drain to reduce the electric field intensity has been adopted.

FIG. 2 is a schematic sectional view showing a manufacturing process of a MOSFET according to a conventional example. First, a silicon oxide film (not shown) is formed on one main surface of a p-type single crystal silicon substrate 1, which is a semiconductor substrate, by thermal oxidation or the like, and a p-type material such as boron (B) is formed through the silicon oxide film. A p-type or n-type well region (not shown) is formed by performing ion implantation of a type impurity or an n-type impurity such as phosphorus (P) and annealing.

Subsequently, a silicon nitride film (not shown) is formed on the silicon oxide film by a CVD method or the like, and the silicon nitride film is etched using a resist mask (not shown) patterned in a predetermined shape. The LOCOS film 2 is formed by performing LOCOS (Local Oxidation of Silicon) using the silicon nitride film in which the opening is formed as a mask, thereby forming a resist mask,
The silicon nitride film and the silicon oxide film are removed.

Next, a silicon oxide film 5 is formed on one main surface of the single crystal silicon substrate 1, and a polysilicon layer is formed on the silicon oxide film 5. Then, the polysilicon layer is patterned into a predetermined shape to form an insulating gate 6 made of the polysilicon layer (FIG. 2A).

Next, ion implantation of an n-type impurity such as phosphorus (P) is performed using the insulating gate 6 as a mask, a silicon oxide film is formed by a low pressure CVD method (hereinafter referred to as LPCVD), and the entire surface is etched. Thereby, a sidewall 13 made of a silicon oxide film is formed on the sidewall of the insulating gate 6 (FIG. 2B).

Finally, an n-type impurity such as arsenic (As) is ion-implanted using the insulating gate 6 and the side wall 13 as a mask (FIG. 2C), and an LDD (Lightly Doped Drain) is performed by annealing. 2) A drain region 8 and a source region 9 having a structure are formed (FIG. 2D).

[0009]

The above-mentioned device structure (LDD structure) is a very useful technique. However, if the conditions are not optimized, the effective channel length is shortened due to lateral diffusion. There is a concern that the punch-through withstand voltage may be reduced.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device which suppresses a single channel effect and has a high punch-through breakdown voltage and a method of manufacturing the same. is there.

[0011]

According to the first aspect of the present invention,
A semiconductor substrate having a well region formed on one main surface thereof, a tapered groove formed on one main surface of the semiconductor substrate, a polysilicon layer formed via an oxide film in the groove, and the groove. A drain region and a source region are formed on one main surface of the semiconductor substrate with an impurity concentration gradient along the one main surface direction of the semiconductor substrate.

According to a second aspect of the invention, there is provided the method of manufacturing a semiconductor device according to the first aspect, wherein the tapered groove is formed on one main surface of the semiconductor substrate by anisotropic etching. A polysilicon layer is formed via the oxide film, and ion implantation is performed using the polysilicon layer as a mask. The ion implantation is performed along one main surface direction of the semiconductor substrate with the groove portion interposed therebetween. The drain region and the source region are formed with an impurity concentration gradient.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, the polysilicon layer is formed by epitaxial growth.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The case of an NMOS will be described below, but the present invention is also applicable to the case of a PMOS.
FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to one embodiment of the present invention. A silicon oxide film (not shown) is formed on one main surface of a p-type single crystal silicon substrate 1 which is a semiconductor substrate by thermal oxidation or the like, and a p-type impurity such as boron (B) is formed through the silicon oxide film. Alternatively, p-type or n-type well regions (not shown) are formed by performing ion implantation of n-type impurities such as phosphorus (P) and annealing. Then, using a resist mask (not shown) patterned in a predetermined shape or the like, a LOCOS (Local
A p-type impurity such as boron (B) is ion-implanted into a portion where the Oxidation of Silicon film 2 is to be formed through a silicon oxide film. This ion-implanted region is
S forms the p-type diffusion layer 3.

Subsequently, a silicon nitride film (not shown) is formed on the silicon oxide film by a CVD method or the like, and the silicon nitride film is etched using a resist mask (not shown) patterned in a predetermined shape. The LOCOS film 2 is formed by performing LOCOS using the silicon nitride film in which the opening is formed as a mask,
The resist mask, the silicon nitride film and the silicon oxide film are removed. At this time, a p-type diffusion layer 3 is formed below the LOCOS film 2 as a channel stopper.

Next, at a place where an insulated gate 6 described later is formed,
A trench 4 is formed by using a photolithography technique and an etching technique, and a thin silicon oxide film 5 is formed on one main surface of the single crystal silicon substrate 1 by thermal oxidation or the like (FIG. 1A). This silicon oxide film 5 becomes a gate oxide film. At this time, the etching for forming the groove 4 is
The tapered groove 4 is formed by anisotropic etching using an alkaline etchant such as a potassium hydroxide (KOH) solution.

Next, a polysilicon layer is formed on the silicon oxide film 5 by an LPCVD method or the like.
Thermal diffusion treatment of phosphorus (P) is performed in POCl ₃ atmosphere at ℃, and groove 4 is formed by photolithography technology and etching technology.
By leaving the polysilicon layer only at the formation location and removing the polysilicon layer at other locations, an insulating gate 6 made of the polysilicon layer is formed (FIG. 1B).

Next, an n-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted using a resist mask 7 patterned into a predetermined shape (FIG. 1C). At this time, since the groove 4 is formed in a tapered shape, the amount of impurities decreases from the opening end of the groove 4 toward the center on one main surface of the single crystal silicon substrate 1 during ion implantation. Then, by performing an annealing process, a drain region 8 and a source region 9 having an impurity concentration gradient are formed along the main surface direction (in the lateral direction) of the single-crystal silicon substrate 1 by gate self-alignment, and the resist mask 7 is formed. Is removed.

Next, an interlayer insulating film (BPSG) 10 is deposited on one main surface side of the single crystal silicon substrate 1 by a normal pressure CVD method,
In order to make contact with the insulating gate 6, the drain region 8 and the source region 9, the silicon oxide film 5 and the interlayer insulating film 10 at predetermined locations are etched to form contact holes 11.

Next, a metal layer such as an Al—Si—Cu layer is deposited so as to fill the contact hole 11 by sputtering or the like, and is patterned into a predetermined shape to form a metal electrode 1.
2 is formed (FIG. 1D).

Finally, a protective film (not shown) is formed by a normal pressure CVD method or the like, and a pad (not shown) for connection with the metal electrode 12 is formed by a photolithography technique and an etching technique.

Therefore, in the present embodiment, the tapered groove 4 is formed, the insulating gate 6 is formed so as to fill the groove 4, and ion implantation is performed using the insulating gate 6 as a mask, thereby forming a lateral direction. Since the impurity concentration gradient is provided, the electric field intensity in the vicinity of the drain can be reduced, and the effective channel length is not shortened by the formation of the groove portion 4, so that the reduction in punch-through breakdown voltage can be prevented.

Further, the LDD structure can be formed by one ion implantation, and the number of steps can be reduced as compared with the conventional example.

In the present embodiment, the single-crystal silicon substrate 1 has a p-type conductivity as the conductivity type.
A mold type may be used.

In this embodiment, if the polysilicon layer is formed by epitaxial growth, the steps can be simplified and the number of heat steps can be reduced.

[0026]

According to the first aspect of the present invention, there is provided a semiconductor substrate having a well region formed on one main surface, a tapered groove formed on one main surface of the semiconductor substrate, and an oxide film formed on the groove. And a drain region and a source region formed on one main surface of the semiconductor substrate with an impurity concentration gradient along one main surface direction of the semiconductor substrate with the groove portion interposed therebetween. Accordingly, the electric field intensity near the drain can be reduced, the short channel effect can be suppressed, and a semiconductor device with high punch-through breakdown voltage can be provided.

According to a second aspect of the present invention, there is provided the method of manufacturing a semiconductor device according to the first aspect, wherein the tapered groove is formed on one main surface of the semiconductor substrate by anisotropic etching. A polysilicon layer is formed via the oxide film, and ion implantation is performed using the polysilicon layer as a mask. The ion implantation is performed along one main surface direction of the semiconductor substrate with the groove portion interposed therebetween. Since the drain region and the source region are formed with an impurity concentration gradient, the electric field strength near the drain can be reduced, the short channel effect can be suppressed, and a method of manufacturing a semiconductor device with high punch-through breakdown voltage can be realized. Could be provided.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, since the polysilicon layer is formed by epitaxial growth, the process is simplified in addition to the effect of the second aspect. And the number of heating steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a manufacturing process of a semiconductor device according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 2 LOCOS film 3 P-type diffusion layer 4 Groove 5 Silicon oxide film 6 Insulating gate 7 Resist mask 8 Drain region 9 Source region 10 Interlayer insulating film 11 Contact hole 12 Metal electrode 13 Side wall

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisazu Miyajima 1048 Oaza Kadoma, Kadoma, Osaka Pref. Matsushita Electric Works Co., Ltd. F-term (reference) FC05 FC10 FC16 FC21

Claims (3)

[Claims] 1. A semiconductor substrate having a well region formed on one main surface, a tapered groove formed on one main surface of the semiconductor substrate, and a polysilicon layer formed on the groove with an oxide film interposed therebetween. And a drain region and a source region formed on one main surface of the semiconductor substrate with an impurity concentration gradient along one main surface direction of the semiconductor substrate with the groove interposed therebetween. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the tapered groove is formed on one main surface of the semiconductor substrate by anisotropic etching, and the groove is formed via the oxide film. By forming a polysilicon layer and performing ion implantation using the polysilicon layer as a mask, an impurity concentration gradient is provided on one main surface of the semiconductor substrate across the groove along the one main surface direction of the semiconductor substrate. Forming a drain region and a source region by performing the method. 3. The method according to claim 2, wherein said polysilicon layer is formed by epitaxial growth.