JP2001203348A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Problem] To determine the depth of a channel region regardless of the junction depth of a source / drain region.
It is an object of the present invention to provide a semiconductor device in which resistance of a drain region and prevention of a short channel effect can be controlled independently, and variation in characteristics can be suppressed. The semiconductor device includes a gate insulating film and a gate electrode formed on a semiconductor substrate, and a source / drain region buried in the semiconductor substrate. 14
A semiconductor device in which an insulating film 20 is formed between a source / drain region 21c and a semiconductor substrate 10 so as to contact the semiconductor substrate 10 at a depth smaller than that of the source / drain region 21c on the side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a MOS transistor having a fine structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years,
With the increase in the degree of integration of LSIs, the transistors used have been increasingly miniaturized. At present, transistors having a gate length of 0.2 to 0.3 μm have been required. Such a fine transistor is formed by, for example, a technique in which a source / drain region is formed shallow or a gate electrode is buried in a substrate to make the source / drain region apparently shallow.
No. 259).

However, when a transistor is miniaturized, problems such as a decrease in threshold voltage due to a short channel effect and a punch-through between source / drain regions occur. This is difficult to solve even when the source / drain regions are formed shallow, as long as the source / drain regions are in contact with the semiconductor substrate. In addition, the junction leakage between the source / drain region and the substrate and the junction capacitance increase due to the increase in the impurity concentration of the substrate due to the scaling law. From the viewpoint of the impurity concentration of the substrate, the short channel effect and the junction capacitance increase. Are in conflict with each other, and even if the power supply voltage is reduced, the problems of increased power consumption and reduced performance have not been solved.

[0004] A number of measures have been proposed for the above problem. For example, SOI (Silico) represented by SIMOX for maintaining low power consumption and high speed
n On Insulator) transistors formed on a substrate. However, the price of an SOI substrate is about ten times that of a bulk silicon substrate, and at present, it has not reached the mainstream technology due to cost issues.

Further, an SOI using a bulk silicon substrate
There are also attempts to obtain the same effect as the substrate. For example,
A structure in which a source / drain region is surrounded by a thin insulating film enough to allow a tunnel current to flow (Japanese Patent Laid-Open No. 6-97)
435). With such a structure, an ultrafine transistor can be realized while suppressing increase in junction leak and junction capacitance. As another example, FIG.
As shown in (e), there is a structure in which an oxide film 31 is provided below the source / drain region 37 (Japanese Unexamined Patent Application Publication No. 3-53-53).
No. 534). The transistor having such a structure has a small advantage in that the junction leakage and the junction capacitance can be suppressed to be small, and low power consumption and high speed can be obtained.

Hereinafter, a method of manufacturing this transistor will be described. First, as shown in FIG. 6A, the P-type silicon substrate 30 is oxidized to form an oxide film 31 on the entire surface of the silicon substrate 30. A P-type doped polysilicon film is deposited thereon. At this time, the thickness of the polysilicon film is made slightly smaller than the depth of the source / drain regions (0.2 μm).
m or less). The polysilicon film is monocrystallized by laser annealing to form a silicon film 32 (FIG. 6A).

Next, as shown in FIG. 6B, a resist pattern (not shown) having a desired opening is formed by a photolithography and etching process, and a silicon film is formed using this resist pattern as a mask. 3
2. An opening 33 is formed by etching the oxide film 31.
Next, after removing the resist pattern, as shown in FIG. 6C, a silicon 34 film is buried in the opening 33 by epitaxial growth. Subsequently, as shown in FIG. 6D, the silicon film 3 in a region corresponding to the element isolation region is formed.
2 is removed by etching, and an oxide film 38 is buried in the region.

Thereafter, as shown in FIG. 6E, a gate insulating film 35 and a gate electrode 36 are formed on the silicon substrate 30 by a known method, and arsenic or phosphorus is formed using the gate electrode 36 as a mask. To form source / drain regions 37, activate impurities by heat treatment, and form an interlayer insulating film (not shown), a contact hole (not shown), a wiring (not shown), and the like. Complete the semiconductor device.

Even in such a structure, since the short channel effect depends on the depth of the source / drain regions, the source / drain regions are made shallow (θ in FIG. 6 (e) is made shallow). If an attempt is made to prevent the short channel effect, the resistance of the source / drain regions increases, and the problem that high-speed operation is hindered still remains. In addition, if the source / drain regions are shallow, there is a problem that the silicon film is penetrated by overetching when forming the contact hole. Furthermore, since it is necessary to form a thin silicon film and heat-treat it, there is a problem that new facilities such as a laser annealing apparatus and an epitaxial growth apparatus which are not used in the conventional manufacturing of a MOS transistor are required. . Also,
Since the gate electrode is formed by patterning using the resist pattern as a mask after forming the element isolation region 38 and the oxide film 31, characteristic variations due to misalignment of the mask with the region where the silicon 34 film is embedded are reduced. There is also a problem that occurs.

The present invention has been made in view of the above problems, and can determine the depth of a channel region regardless of the junction depth of a source / drain region. And a semiconductor device capable of independently controlling the prevention and preventing a variation in characteristics due to a mask misalignment or the like because the insulating film surrounding the source / drain regions is formed in a self-aligned manner after the formation of the gate electrode. It is an object of the present invention to provide a manufacturing method thereof.

[0011]

According to the present invention, a gate insulating film and a gate electrode formed on a semiconductor substrate of a first conductivity type and a second insulating film and a gate electrode formed on the surface of the semiconductor substrate are embedded.
A source / drain region of a conductivity type, wherein the source / drain region is in contact with the semiconductor substrate at a depth smaller than the depth of the source / drain region on the gate electrode side. A semiconductor device in which an insulating film is formed between a region and a semiconductor substrate is provided.

According to the present invention, (a) a gate insulating film and a gate electrode are formed on a semiconductor substrate, and a sidewall spacer is formed on a side wall of the gate electrode. (B) The gate electrode and the sidewall are formed. The semiconductor substrate is etched by using the spacer as a mask to form a recess, (c) an oxidation-resistant film sidewall spacer is formed on the side wall of the recess, and (d) the oxidation-resistant film sidewall spacer. Using the as a mask, the obtained semiconductor substrate is oxidized to form an oxide film below the bottom surface and the side wall of the concave portion,
(E) There is provided a method of manufacturing a semiconductor device, comprising: removing a sidewall spacer of the oxidation-resistant film; and embedding a conductive film in the recess.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention mainly comprises a semiconductor substrate, a gate insulating film, a gate electrode, and source / drain regions. The semiconductor substrate used in the present invention is not particularly limited as long as it is generally used for a semiconductor device, and examples thereof include elemental semiconductors such as silicon and germanium, and compound semiconductors such as GaAs and InGaAs. Among them, a silicon substrate is preferable. This semiconductor substrate contains P-type or N-type impurities over the entire surface of the substrate, or partially
It is preferable that an impurity diffusion layer (well) is formed by introducing an N-type or N-type impurity. The impurity concentration in this case is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / c.
m ³ . Also, on other regions of the semiconductor substrate, circuits including transistors, capacitors, resistors,
A wiring layer, an insulating layer, another storage device, or the like may be formed alone or in combination.

The gate insulating film formed on the semiconductor substrate can be formed of a material and a film thickness usually formed as a gate insulating film of a MOS transistor. For example, a silicon oxide film, a silicon nitride film or a laminated film thereof,
The thickness is about 5 to 50 nm.

The gate electrode may be formed of any conductive film which is usually used as an electrode. For example, a polysilicon film; aluminum, copper, gold,
Metals such as silver and nickel; refractory metals such as tantalum, titanium and tungsten; silicides composed of refractory metals and polysilicon; polycides; The thickness of the gate electrode is, for example, about 0.1 to 0.3 μm. Note that an insulating film (silicon oxide film, silicon nitride film, a stacked film thereof, or the like) having the same planar shape as the gate electrode may be provided over the gate electrode, or may be insulated from the gate electrode side wall or the gate electrode. A sidewall spacer formed of an insulating film may be provided on a side wall of the film.

The source / drain regions buried in the surface of the semiconductor substrate are conductive regions formed on the surface of the semiconductor substrate on both sides of the gate electrode, and a conductive film is buried in the surface of the semiconductor substrate. Is formed.

The conductive film forming the source / drain regions is not particularly limited. For example, the conductive film is formed by doping a semiconductor material similar to the above-described semiconductor substrate with an impurity having a conductivity type different from that of the semiconductor substrate. And the like.
Among them, a silicon film, particularly a single crystal silicon film is preferable. The impurity concentration of the source / drain regions is, for example, about 5 × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ . The width and depth of the source / drain regions can be appropriately adjusted in consideration of the performance and the like of the obtained semiconductor device. For example, the width (w in FIG. 2C) can be adjusted.
About 0.2 to 0.5 μm, depth (β in FIG. 2C)
About 0.3 to 0.6 μm.

The source / drain region is in contact with the semiconductor substrate on the gate electrode side at a depth (α in FIG. 1) smaller than the depth of the source / drain region. An insulating film is formed between the source / drain region and the semiconductor substrate so as to make contact with the substrate. In other words, the source / drain region is surrounded by the insulating film on the surface of the semiconductor substrate so that the source / drain region is in contact with the semiconductor substrate only in the extreme surface region on the gate electrode side. For example, when the source / drain region has a depth within the above range, the source / drain region and the semiconductor substrate are in contact with each other at a depth of about 0.02 to 0.06 μm (α in FIG. 1). Is appropriate. And
On the gate electrode side, the entire periphery of the source / drain region is covered with an insulating film except for a region having such a depth from the surface.

Examples of the insulating film include a silicon oxide film, a silicon nitride film, and a laminated film of these.
The thickness of the insulating film is not particularly limited as long as the insulating property of the source / drain regions can be ensured when the operating voltage of the obtained semiconductor device is applied, but is about 10 to 50 nm. Note that the insulating film surrounding the source / drain regions only needs to insulate the source / drain regions from at least the semiconductor substrate, and does not need to cover the surfaces of the source / drain regions. The insulating film is
The film may be partially formed of a different material, or may have a different film thickness in a part of a region surrounding the source / drain region.

In the semiconductor device of the present invention, the semiconductor substrate in contact with the source / drain region may be of a conductivity type different from that of the source / drain region as described above. In part, the conductivity type and / or concentration of the impurity may be changed.

For example, a low-concentration region having the same conductivity type as that of the source / drain region and a low impurity concentration is formed on the semiconductor substrate in a region in contact with the source / drain region. The source / drain region may be in contact with the semiconductor substrate. It is generally appropriate that the low concentration region has a position, size, and impurity concentration similar to those of the LDD region in the source / drain region. Specifically, an impurity concentration of about 1 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ³ may be used.

In addition, the semiconductor substrate is located below the gate electrode and deeper than a region where the source / drain region and the semiconductor substrate are in contact with each other, that is, the surface of the semiconductor substrate,
A high-concentration region having the same conductivity type as the semiconductor substrate immediately below the gate electrode and having a high impurity concentration may be formed. The position, size, and impurity concentration of the high-concentration region can be appropriately adjusted depending on the characteristics of the obtained semiconductor device.For example, when the obtained semiconductor device is operated, a lower voltage and a higher speed can be obtained. It is preferable to set the position, size, and impurity concentration at which the operation can be performed more reliably. Specifically, the position and the size (width) in the range of about 0.02 to 0.06 μm from the surface of the semiconductor substrate include an impurity concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ .

In the method of manufacturing a semiconductor device according to the present invention, first, in step (a), a gate insulating film and a gate electrode are formed on a semiconductor substrate, and a sidewall spacer is formed on a side wall of the gate electrode. In the semiconductor substrate used here, an N-type or P-type impurity may be previously introduced into the entire surface, or a well in which an N-type or P-type impurity is partially introduced may be formed. . Further, it is preferable that an element isolation region is formed in a desired region by a LOCOS method, a trench element isolation method, or the like.

The gate insulating film is formed, for example, by a thermal oxidation method, CV
By the method D, it can be formed with a desired film thickness. The gate electrode can be formed by, for example, forming the conductive film over a semiconductor substrate by a sputtering method, a CVD method, an evaporation method, or the like, and patterning the conductive film into a desired shape by a photolithography and etching process. Note that when the gate electrode is formed of polysilicon, it is preferable to introduce a p-type or n-type impurity during, after, or after patterning the gate electrode. In the case where an insulating film is formed over the gate electrode, an insulating film such as a silicon oxide film or a silicon nitride film may be formed before patterning the conductive film, and patterning may be performed simultaneously with patterning the gate electrode. preferable.

As a method of forming a sidewall spacer on the side wall of the obtained gate electrode, for example, first, an insulating film is formed on the entire surface of the semiconductor substrate including the gate electrode,
There is a method of performing etch back by an anisotropic etching method such as an IE method. The thickness of the insulating film formed at this time is, for example, about 50 to 150 nm. In the case where an insulating film is formed over the gate electrode, it is preferable to form a sidewall spacer on a side wall between the gate electrode and the insulating film.

In the step (a), before forming the gate electrode, an impurity of the same conductivity type as that of the semiconductor substrate may be introduced into the semiconductor substrate. As described above, the impurity is introduced into the semiconductor substrate below the gate electrode at a position deeper than the region where the source / drain region and the semiconductor substrate are in contact with each other with the same conductivity type as the surface of the semiconductor substrate. A high-concentration region with a high concentration can be formed. In this case, the impurity is introduced, for example, at 10 to 30 k.
Energy of about eV, 1 × 10 ^{12 to} 5 × 10 ¹³ / cm
It is preferable to perform the ion implantation at a dose of about ² .

Further, in the step (a), after forming the gate electrode, an impurity of a conductivity type different from that of the semiconductor substrate may be introduced into the semiconductor substrate. By introducing the impurity, as described above, the source / drain region can be reliably brought into contact with the semiconductor substrate through the low-concentration region having the same conductivity type as the source / drain region and having a low impurity concentration. In this case, the introduction of the impurity is performed by, for example, 5
Energy of about 15 keV, 5 × 10 ¹¹ to 1 × 10
It is preferable to perform the ion implantation at a dose of about ¹³ / cm ² .

In the step (b), the semiconductor substrate is etched using the gate electrode and the sidewall spacer as a mask to form a concave portion. The etching in this case can be performed by, for example, anisotropic etching such as RIE. Note that this etching may be performed continuously with the etch back for forming the sidewall spacer by changing the etchant. The depth and width of the concave portion are not particularly limited, but the depth is particularly determined along with the thickness of the oxide film formed below the bottom surface and the side wall of the concave portion, which will be described later, and the depth of the source / drain region. Therefore, it is necessary to consider the characteristics, size, and the like of the obtained semiconductor device. For example, the depth is about 30 to 60 nm and the width is about 0.2 to 0.3 μm.

After the recess is formed in the semiconductor substrate and before the step (c), an oxide film may be formed on the entire inner surface of the recess, or the sidewall spacer of the oxide film may be formed only on the side wall of the recess. Alternatively, after forming an oxide film on the entire inner surface of the concave portion, a sidewall spacer of the oxide film may be formed again only on the side wall of the concave portion. In this case, the thickness of the oxide film formed on the entire inner surface is suitably about 2 to 10 nm. Further, the sidewall spacer formed only on the side wall of the concave portion has a width of 3 to 3 on the bottom surface of the concave portion.
Suitably, it is about 10 nm.

In step (c), sidewall spacers of an oxidation-resistant film are formed on the side walls of the recess. An example of the oxidation resistant film in this case is a silicon nitride film. The thickness of the oxidation resistant film is not particularly limited,
For example, the thickness is about 5 to 20 nm. The sidewall spacer can be formed substantially in the same manner as the sidewall spacer formed on the side wall of the gate electrode described above. When the oxide film and / or the sidewall spacer of the oxide film is formed only on the side wall of the recess in the previous step, the oxide film and / or the sidewall spacer is formed on the sidewall of the oxide film. Then, a sidewall spacer of an oxidation resistant film is formed.

In the step (d), the obtained semiconductor substrate is oxidized using the sidewall spacer of the oxidation-resistant film as a mask to form an oxide film on the bottom surface of the recess and below the side wall. The oxidation method here is not particularly limited, and for example, thermal oxidation in an oxidizing atmosphere is appropriate.
The oxidation conditions in this case include a temperature range of about 800 to 900 ° C. and a time of about 10 to 60 minutes. Thus, an oxide film can be formed on the surface of the semiconductor substrate other than the region covered with the oxidation resistant film, that is, on the bottom surface of the concave portion, and the oxide film can be formed below the side wall of the concave portion by wrapping around the oxide film. . The thickness of the oxide film can be appropriately adjusted depending on the depth of the concave portion and the like.
On the bottom surface of the concave portion, about 20 to 50 nm is exemplified.

In the step (e), first, the sidewall spacer of the oxidation resistant film is removed. In this case, examples of the removal method include various methods such as dry etching or wet etching using an etchant having a large selectivity to an oxide film or the like.

Next, a conductive film is embedded in the concave portion. As a method of embedding the conductive film, a method of depositing a conductive film on the entire surface of the obtained semiconductor substrate and etching back by an anisotropic etching method such as RIE method may be mentioned. Here, the conductive film deposited on the semiconductor substrate may be made of any material, but is preferably a silicon film. When a silicon film is used, the silicon film may be deposited while being doped with an N-type or P-type impurity so as to have an impurity concentration capable of functioning as a source / drain region. N-type or P-type impurities may be doped by ion implantation, thermal diffusion, or the like. Further, after a silicon film is deposited, a conductive film is buried in the concave portion, and then N-type or P-type impurities are implanted by ion implantation, thermal diffusion, or the like. Or P-type impurities may be doped. Also,
The silicon film may be deposited as a single crystal silicon film, or may be deposited as a polycrystalline silicon film and then recrystallized to form a single crystal silicon film. The thickness of the conductive film to be deposited is not particularly limited, but is preferably equal to or greater than the depth of the concave portion after the oxide film is formed on the bottom.
Specifically, about 400 to 800 nm is mentioned.

In the method of manufacturing a semiconductor device according to the present invention, before, during, after, etc., the steps usually performed for completing the semiconductor device, for example, heat treatment, formation of an interlayer insulating film, surface Flattening, forming contact holes,
By arbitrarily forming a wiring layer and the like, a semiconductor device can be completed. Further, in the method of manufacturing a semiconductor device according to the present invention, any one of N-type, P-type, N-type and P-type M
It can be used also when forming an OS transistor. Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same of the present invention will be described in detail with reference to the drawings.

Embodiment 1 As shown in FIG. 1, a MOS transistor, which is an example of a semiconductor device of the present invention, comprises a gate insulating film 13 and a gate electrode 14 formed on a P-type silicon substrate 10; 10 N-type source buried on the surface /
And a drain region 21c.

The source / drain region 21c is connected to the silicon substrate 10 at a depth (α in FIG. 1) smaller than the source / drain region 21c on the gate electrode 14 side. Silicon substrate 1
0 is formed between the insulating film 20 and the insulating film 20. The source / drain region 21c is N-type and is in contact with the silicon substrate 10 via a low concentration region 22 having a lower impurity concentration than the source / drain region 21c. Further, in the silicon substrate 10 below the gate electrode 14, at a position deeper than the region where the source / drain region 21 c and the silicon substrate 10 substrate are in contact with each other, the P-type silicon substrate 10 is located lower than the silicon substrate 10 directly below the gate electrode 14. A P-type diffusion region 23 having a high impurity concentration is formed.

With such a structure, the entrance and exit of electrons between the source / drain region 21c and the channel region formed immediately below the gate electrode 14 are formed by current paths (width in the depth direction, inversion (Layer width), and the short channel effect can be prevented. Further, by arranging the P-type diffusion region 23, the impurity concentration of the channel region can be reduced, so that a higher-speed MOS transistor can be obtained.

The above semiconductor device can be manufactured by the following manufacturing method. First, as shown in FIG. 2A, a boron ion 12 is formed on a surface of a P-type silicon substrate 10 having an element isolation region 11 formed of an oxide film having a thickness of about 100 to 200 nm by a LOCOS method.
V, ions were implanted at 1 to 5 × 10 ¹³ / cm ² .

Next, as shown in FIG. 2B, a gate insulating film 13 having a thickness of 4 to 6 nm and a phosphorus-doped polysilicon having a thickness of about 100 to 150 nm are formed on the silicon substrate 10 by thermal oxidation. A film is formed by sequentially depositing a CVD oxide film having a thickness of about 50 to 100 nm and patterning the same.
The gate electrode 14 covered with the oxide film 15 was formed. Next, as shown in FIG. 2C, a CVD oxide film having a thickness of about 90 to 120 nm is deposited on the obtained silicon substrate 10, and the gate electrode 14 is etched back using a CF-based gas. The sidewalls 16 are formed on the side walls of the silicon substrate 10, and the etching gas is changed to F-based, and the silicon substrate 10 is continuously etched, so that the width of the silicon substrate 10 (w in FIG. 6C) is 0.2-0. The concave portion 1 having a depth of about 3 μm and a depth (β in FIG. 6C) of about 0.3 to 0.6 μm.
7 was formed.

Subsequently, as shown in FIG. 2D, an oxide film 18 having a thickness of about 3 to 5 nm is formed on the surface of the concave portion 17, and a film thickness of 10 to 10 20
By depositing a silicon nitride film of about nm and performing etch back on the entire surface, a sidewall spacer 19 of a silicon nitride film was formed from the side wall of the concave portion 17 to the side wall of the sidewall spacer 16.
Thereafter, as shown in FIG. 3E, the obtained silicon substrate 10 is thermally oxidized, so that a thermal oxide film is formed on the bottom surface of the concave portion 17 and a part below the side surface of the concave portion 17 on the gate electrode 14 side. 20 were formed. The thickness of the thermal oxide film 20 was about 30 to 50 nm at the bottom of the recess 17.

Next, as shown in FIG. 3F, the side wall spacer 19 made of the silicon nitride film is removed,
Further, the oxide film 18 was etched and removed with hydrofluoric acid so that the silicon substrate 10 was exposed at a portion (α = about 30 nm) above the side surface of the recess 17 on the side of the gate electrode 14. On the obtained silicon substrate 10 by the CVD method,
A polysilicon film 21a having a thickness of about 400 to 800 nm was deposited.

Next, as shown in FIG. 3 (g), the polysilicon film 21a is etched back, the polysilicon film 21 is buried in the concave portion 17 of the silicon substrate 10, and the buried polysilicon film 21 is filled with arsenic. Or 10 to 10
Ion implantation was performed at ²⁰ keV and 1 to 5 × 10 ¹⁵ / cm ² .

Subsequently, as shown in FIG. 3 (h), the obtained silicon substrate 10 was heated at about 800 to 850 ° C.
By performing a heat treatment for about 60 minutes, the impurities in the polysilicon film 21 are activated, the polysilicon film 21 is made conductive, the source / drain regions 21c are formed, and the impurities in the polysilicon film 21 are moved in the channel direction. By diffusion, a low concentration region 22 was formed in the silicon substrate 10 immediately below the sidewall spacer 16. At the same time, the boron ions 12 implanted into the silicon substrate 10 were diffused in the vertical direction to form a P-type diffusion region 23. Thereafter, an MOS transistor is completed by forming an interlayer insulating film, a contact hole, a wiring, and the like.

Embodiment 2 In this embodiment, as shown in FIG. 4, after forming the gate electrode in Embodiment 1 (after FIG. 2B),
In order to form a low concentration impurity layer in the LDD structure,
Phosphorus ions 24 are converted to 5 to 10 keV, 5 × 10 ^{13 to} 5 ×
The step of ion implantation at 10 ¹⁴ is added. In the finally obtained MOS transistor, it is possible to prevent deterioration of transistor characteristics and the like, which are caused when diffusion of impurities from the polysilicon film 21 does not reach the gate electrode 14, and to stabilize characteristics. Also, the withstand voltage between the source and the drain can be improved. This is an effective technique especially when the heat treatment cannot be performed for a long time.

Embodiment 3 In this embodiment, as shown in FIG. 5 (a), after forming the recess 17 in the embodiment 1 and forming the oxide film 18 on the surface of the recess 17, the silicon nitride film is formed. Before depositing (FIG. 2D), a film thickness of 10 to 30
By depositing a silicon oxide film having a thickness of 10 nm and etching back, a portion above the side wall of the concave portion 17 (FIG. 5A,
The process of forming the side wall spacer 25 of the silicon oxide film is added except for α ′).

The MOS transistor finally obtained is
As shown in FIG. 5B, the sidewall spacer 1
6 can be made shallower, that is, the current path between the source / drain region 21c and the channel region can be made smaller. Note that the depth α ′ of the low concentration region 26 can be controlled by the height of the sidewall spacer 25 formed of the oxide film, that is, the amount of the oxide film etched back. This MOS transistor is particularly effective when it is close to the limit and further miniaturized.

[0047]

According to the present invention, the distance between the source / drain region and the semiconductor substrate is set so that the source / drain region contacts the semiconductor substrate at a depth smaller than the depth of the source / drain region on the gate electrode side. , Regardless of the junction depth of the source / drain regions
The depth of the channel region of the transistor can be determined. Therefore, it is possible to independently control the resistance of the source / drain regions and the prevention of the short channel effect represented by punch-through. Further, since the insulating film surrounding the source / drain regions is formed in a self-aligned manner after the formation of the gate electrode, it is possible to prevent the occurrence of characteristic variations due to misalignment of the mask and to surround the entire source / drain regions. Therefore, junction leakage can be prevented, and the junction capacitance can be reduced. Further, since it is not necessary to form the source / drain region particularly shallow, an etching margin for forming a contact can be increased, a finer and more stable structure can be realized, and a highly reliable semiconductor device can be realized. Can be provided.

Further, the source / drain region is
When the semiconductor substrate is in contact with the semiconductor substrate through a low-concentration region having the same conductivity type as the drain region and a low impurity concentration, a high source / drain withstand voltage can be obtained, so that hot carrier resistance increases and reliability increases. Semiconductor device with high reliability can be obtained. Further, a high concentration region having the same conductivity type and a high impurity concentration as the surface of the semiconductor substrate is formed in the semiconductor substrate below the gate electrode and at a position deeper than a region where the source / drain region and the semiconductor substrate are in contact with each other. In this case, the channel region can be set at a lower concentration, and a higher-speed semiconductor device can be realized.

According to the method of manufacturing a semiconductor device of the present invention, the semiconductor device having the above-described structure can be manufactured without using any new technology and equipment, as compared with the conventional method of manufacturing a semiconductor device. Becomes possible. Further, in the case where the sidewall spacer of the oxide film is formed on the side wall of the concave portion before the formation of the sidewall spacer of the oxidation-resistant film, the contact region between the source / drain region and the semiconductor substrate,
That is, since the depth of the current entrance / exit can be made smaller, a finer semiconductor device can be easily manufactured.

In the case where an impurity of the same conductivity type as that of the semiconductor substrate is introduced into the semiconductor substrate before forming the gate electrode, the source-drain withstand voltage can be further increased. It is possible to manufacture a semiconductor device with high reliability. Further, in the case where an impurity of a conductivity type different from that of the semiconductor substrate is introduced into the semiconductor substrate after the formation of the gate electrode, the surface of the channel region can be set to a lower impurity concentration; Can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a main part showing an embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional process drawing of a main part showing a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a schematic cross-sectional process drawing of a main part showing a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic cross-sectional process drawing of a main part showing another method of manufacturing a semiconductor device of the present invention.

FIG. 5 is a schematic cross-sectional process drawing of a main part showing a method for manufacturing still another semiconductor device of the present invention.

FIG. 6 is a schematic cross-sectional view of a main part showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Silicon substrate (semiconductor substrate) 11 Element isolation region 12 Boron ion 13 Gate insulating film 14 Gate electrode 15 CVD oxide film 16, 19, 25 Side wall spacer 17 Depression 18 Oxide film 20 Thermal oxide film 21, 21a Polysilicon film (Conductivity) 21c Source / drain region 22, 26 Low-concentration region 23 P-type diffusion region (high-concentration region) 24 Phosphorus ion

Claims (8)

[Claims] 1. A semiconductor device comprising: a gate insulating film and a gate electrode formed on a semiconductor substrate; and a source / drain region buried in the surface of the semiconductor substrate. A semiconductor device, wherein an insulating film is formed between the source / drain region and the semiconductor substrate so as to contact the semiconductor substrate at a depth smaller than the depth of the source / drain region. 2. The semiconductor device according to claim 1, wherein the source / drain region is in contact with the semiconductor substrate via a low-concentration region having the same conductivity type as the source / drain region and a low impurity concentration. 3. A high-concentration high-concentration region in the semiconductor substrate below the gate electrode and deeper than a region where the source / drain region and the semiconductor substrate are in contact with each other, having the same conductivity type as the surface of the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein a region is formed. 4. A gate insulating film and a gate electrode are formed on a semiconductor substrate, a sidewall spacer is formed on a side wall of the gate electrode, and (b) the gate electrode and the sidewall spacer are used as a mask. Forming a recess by etching the semiconductor substrate; (c) forming a sidewall spacer of an oxidation-resistant film on a side wall of the recess;
(D) using the sidewall spacer of the oxidation-resistant film as a mask, oxidizing the obtained semiconductor substrate to form an oxide film on the bottom surface and below the side wall of the concave portion; and (e) forming the sidewall spacer of the oxidation-resistant film. A method of manufacturing a semiconductor device, the method comprising: burying a conductive film in the recess after removing the semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step (e), the conductive film is a silicon film, and after the silicon film is buried in the recess, an impurity is introduced into the silicon film. 6. The method of manufacturing a semiconductor device according to claim 4, wherein before the step (c), a sidewall spacer of an oxide film is further formed on a side wall of the concave portion. 7. The semiconductor device according to claim 4, wherein in the step (a), before forming the gate electrode, an impurity of the same conductivity type as that of the semiconductor substrate is further introduced into the semiconductor substrate. Manufacturing method. 8. The semiconductor device according to claim 4, wherein in the step (a), after forming the gate electrode, an impurity of a conductivity type different from that of the semiconductor substrate is further introduced into the semiconductor substrate. Manufacturing method.