JP2000049286A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To provide a semiconductor device which is suitable for high integration, large scale, hybrid of analog circuit and digital circuit, and has high operation reliability in a noisy environment. A semiconductor substrate (2) including an element formation region (4) and an N-type guard ring (5) formed around the element formation region (4) in the semiconductor substrate (2), connected to a positive power supply terminal (VDD), and shielding the element formation region (4). And a P-type diffusion layer 6 formed inside the N-type guard ring 5 and connected to the negative power supply terminal VSS.
And Further, the N-type guard ring 5 and the P-type diffusion layer 6 are reversely biased to form a capacitor 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an improvement in a semiconductor device including a circuit that requires protection from noise or a circuit that is a source of noise.

[0002]

2. Description of the Related Art FIG. 6 is a perspective view showing an appearance when a conventional semiconductor device is mounted on a substrate. FIG. 7 is a cross-sectional view showing the internal configuration of the semiconductor device of FIG. As shown in FIG. 6, when the semiconductor device 1 is mounted on a substrate or the like, a bypass capacitor (hereinafter, referred to as a bypass capacitor) C is provided near the semiconductor device 1.
Is implemented. In many cases, a bypass capacitor is connected between the power supply terminal of the semiconductor device and the ground. One of the functions of this decap is to reduce adverse effects on circuit operation due to noise and the like outside the semiconductor device 1. In some cases, an electric capacitor having a large capacitance and a capacitor having a good high-frequency characteristic are connected in parallel as a decap.
Note that the wiring between the bypass capacitor and the semiconductor device generally needs to be shortened.

On the other hand, as shown in FIG. 4B, a guard ring 3 made of a ring-shaped diffusion layer is formed in the semiconductor substrate 2, and the element formation of the semiconductor substrate 2 located inside the guard ring 3 is performed. A circuit such as a transistor is formed in the region 4. This circuit is a circuit that needs protection from noise, such as an analog circuit. This guard ring 3
Is a stable power supply terminal V such as a ground terminal.
To form a low impedance circuit.
Therefore, the circuits in the area surrounded by the guard ring 3 are protected from noise generated in other peripheral circuits.

[0004]

However, in the above configuration, since the decap C is connected outside the semiconductor device 1, the noise generated inside the semiconductor device 1 is not sufficiently reduced. Therefore, there is a problem that the noise adversely affects other portions inside the semiconductor device 1. In particular, there is a problem that the adverse effect is large in the analog circuit, and the analog signal is deteriorated. In addition, there is a problem that noise in a circuit, which increases with a high degree of integration and a large scale, cannot be sufficiently reduced only by a guard ring. Further, when a capacitor is formed inside the semiconductor device 1 by a diffusion layer or the like, the area occupied by the capacitor prevents miniaturization and integration of the semiconductor chip 1. Furthermore, when handling signals in a high-frequency band with high-speed operation, the influence of the inductive component of the impedance of the external decap lead wire cannot be ignored, and the high-frequency characteristics of the external decap are not improved. I was

An object of the present invention is to achieve high integration, large scale,
An object of the present invention is to provide a semiconductor device which is suitable for hybrid of an analog circuit and a digital circuit and has high operation reliability in a noisy environment.

[0006]

In order to solve the above problems and achieve the object, the following means have been taken in the semiconductor device of the present invention. (1) A semiconductor device according to the present invention as set forth in claim 1, wherein the semiconductor device includes an element region, and is formed around the element formation region in the semiconductor substrate, and is connected to the first power supply terminal. The first of the first conductivity type that shields the formation region
A diffusion layer formed inside the first diffusion layer;
A second conductive type second diffusion layer connected to the power supply terminal. Further, the first diffusion layer and the second diffusion layer are reverse-biased to form a capacitor.

In the semiconductor device of the present invention, the first diffusion layer and the capacitor (the first diffusion layer and the second diffusion layer connected to the first power supply terminal and the second power supply terminal, respectively) Since the first diffusion layer (hereinafter, referred to as a decap) is formed integrally with the first diffusion layer (hereinafter, referred to as a shield effect) without providing a dedicated region for the decap.
A guard is formed in the guard ring). In other words, a bypass capacitor can be easily formed in the semiconductor device, and a circuit, for example, an analog circuit or the like, which is easily affected by noise that increases with higher integration and larger scale can be protected. Therefore, the configuration is suitable for an analog hybrid semiconductor device. Further, since the wiring of the decap is shortened and the high-frequency characteristics of the decap are improved, it is particularly effective when handling a signal in a high frequency band.

According to a second aspect of the present invention, at least a first insulating film formed on the second diffusion layer and a first insulating film formed on the first insulating film are connected to the first power supply terminal. And a first electrode connected to the second diffusion layer to form a capacitor with the second diffusion layer.

In the above-described semiconductor device of the present invention, the first diffusion layer, the second diffusion layer, the first insulating film,
Since the first electrode is formed, the first diffusion layer and the first electrode shield, and the first diffusion layer and the second diffusion layer connected to the first power supply terminal and the second power supply terminal. The influence of noise is further reduced by the decap formed of the diffusion layer and the decap formed of the second diffusion layer and the first electrode.

According to a third aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate including an element formation region, and a semiconductor substrate formed around the element formation region in the semiconductor substrate, connected to the second power supply terminal, A diffusion layer for shielding an element formation region, a first insulating film formed on the diffusion layer, and a diffusion layer formed on the first insulating film and connected to the first power supply terminal; And a first electrode forming a capacitor.

In the semiconductor device of the present invention, since the diffusion layer and the decap including the diffusion layer and the first electrode are integrated, a dedicated area for the decap is not required. That is, the structure is suitable for high integration and large scale. Further, a circuit which is easily affected by noise, such as an analog circuit, can be protected, so that a structure suitable for an analog hybrid semiconductor device can be obtained. Further, since the electrode of the decap is formed on the semiconductor substrate, the effect of the shield effect of the electrode makes it hard to be affected by noise from a direction along the surface of the semiconductor substrate. In particular, it is effective for high frequency noise.

Further, as set forth in claim 4, a second electrode provided on the first electrode via a second insulating film and connected to the second power supply terminal, and And a capacitor connected in parallel with the third electrode connected to the first power supply terminal at least once on the first power supply terminal.

In the semiconductor device of the present invention, since a plurality of electrodes are formed on the semiconductor substrate, the element formation region is shielded by the plurality of electrodes.
Further, the first diffusion layer, the second diffusion layer, and the first
Is connected in parallel with a capacitor formed of the diffusion layer and the first electrode and a parallel connection capacitor formed of one or more capacitors, so that the element formation region is further less affected by noise. .

According to another aspect of the present invention, a second insulating film formed on the first electrode and a second insulating film formed on the second insulating film are connected to the second power supply terminal. And a second electrode forming a capacitor together with the first electrode. A third insulating film provided on the second electrode via a third insulating film and connected to the first power supply terminal;
A parallel connection capacitor formed by stacking at least once a capacitor composed of a first electrode and a fourth electrode provided on the third electrode via a fourth insulating film and connected to the second power supply terminal. ing.

In the semiconductor device of the present invention, since a plurality of electrodes including the second electrode are formed on the semiconductor substrate, the element formation region is shielded by the plurality of electrodes. In addition, the first diffusion layer and the second diffusion layer and the first electrode, or a capacitor including the diffusion layer and the first electrode and a parallel connection capacitor including one or more capacitors are connected in parallel. This makes the element formation region less susceptible to noise.

According to a sixth aspect of the present invention, the element formation region has a gate insulating film formed of the same member as the first insulating film, and a gate formed of the same member as the first electrode. It has a transistor including an electrode.

In the above semiconductor device of the present invention,
Since the gate insulating film and the gate electrode and the first insulating film and the first electrode included in the element formation region are formed at the same time, the thickness of the first insulating film is small and the capacitance is large. . Further, the number of steps for forming the capacitor does not increase.

Further, according to any one of claims 1 to 3, an interlayer insulating film formed on the entire surface of the semiconductor substrate, and formed over the interlayer insulating film so as to cover the element formation region; And a shield electrode connected to one of the power supply terminals. In the above-described semiconductor device of the present invention, the shield effect is further improved because the shield electrode is formed to cover the entire upper surface of the element formation region.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those in FIG. 7 are denoted by the same reference numerals, and only different parts will be described. (First Embodiment) FIG. 1 is a sectional view showing a configuration of a first embodiment of the present invention.

As shown in FIG. 1, a ring-shaped N-type guard ring 5 composed of an N-type diffusion layer is formed in the P-type semiconductor substrate 2 or the P-well. In the element forming region 4 of the semiconductor substrate 2 located inside the guard ring 5, an analog circuit such as a MOS transistor, a digital circuit, and a mixed analog / digital circuit are formed. Inside the guard ring 5, a P-type diffusion layer 6 is formed along the guard ring 5. The guard ring 5 is connected to a positive power supply terminal VDD which is a stable power supply terminal, and the diffusion layer 6 is connected to a negative power supply terminal VSS which is a stable power supply terminal. Therefore, the shield effect of the guard ring 5 is the same as the conventional one. At the same time, the guard ring 5 and the diffusion layer 6 are reverse-biased, and a bypass capacitor 7 is formed by the PN junction capacitance. That is, the guard ring 5 and the bypass capacitor 7 are integrally formed.

Incidentally, the semiconductor substrate or the well may be of N type, the guard ring 5 may be formed of P type, and the diffusion layer 6 may be formed of N type. In this case, the P-type guard ring is connected to the negative power supply terminal VSS, and the N-type diffusion layer is connected to the positive power supply terminal VDD.

In the above embodiment, since the guard ring and the decap are integrally formed, the decap is formed in the semiconductor device without providing a dedicated area for the decap. That is, a bypass capacitor can be easily formed in a semiconductor device, and a circuit, such as an analog circuit, which is likely to be adversely affected by noise that increases with higher integration and larger scale can be protected. Therefore, the configuration is suitable for an analog hybrid semiconductor device. Further, since the wiring of the decap is shortened and the high-frequency characteristics of the decap are improved,
This is particularly effective when handling signals in a high frequency band. (Second Embodiment) FIG. 2 is a cross-sectional view showing a second embodiment of the present invention, and the position where a decap is formed is different from that of FIG. 1 are given the same reference numerals. Hereinafter, differences will be mainly described.

In FIG. 2, there is no diffusion layer 6 in the guard ring 5. An insulating layer 8a is formed on the guard ring 5 along the guard ring 5 in a ring shape.
The electrode 8 is formed in a ring shape on the insulating layer 8a along the insulating layer 8a. The guard ring 5, the insulating layer 8a, and the electrode 8 form a bypass capacitor 7a. The guard ring 5 is connected to a positive power supply terminal VDD which is a terminal of a stable power supply,
Is connected to a negative power supply terminal VSS which is a stable power supply terminal. In this case, the guard ring 5 may be connected to the negative power supply terminal VSS, and the electrode 8 may be connected to the positive power supply terminal VDD.
The insulating film 8a and the electrode 8 may be formed simultaneously with the gate insulating film and the gate electrode of the MOS transistor formed in the element formation region 4.

In the embodiment of the present invention, a decap is formed in a direction perpendicular to the surface of the semiconductor substrate 2. Therefore, the electrode 8 of this decap has a shielding effect against electromagnetic noise. That is, noise due to the antenna effect is reduced.

When an FET having a gate insulating film and a gate electrode is formed in the element forming region 4, the insulating film 8
Since the a and the electrode 8 can be formed simultaneously with the gate insulating film and the gate electrode, respectively, the thickness of the insulating film 8a is reduced, and the capacitance of the decap 7a is increased. Further, the number of steps for forming the decaps does not increase. (Modification 1) FIGS. 3 and 4 are cross-sectional views showing Modification 1 of the embodiment of the present invention, in which decap forming positions are different from those in FIG. 3 and 4, the same parts as those in FIG. 1 are denoted by the same reference numerals. Hereinafter, differences will be mainly described.

FIG. 3 shows a configuration in which the embodiments of FIGS. 1 and 2 are combined. That is, the guard ring 5
The insulating film 8a and the electrode 8 are formed on the boundary between the diffusion layer 6 and the insulating film 8a. The guard ring 5 and the electrode 8 are connected to the power terminal VDD, and the diffusion layer 6 is connected to the power terminal VSS. In this case, the bypass capacitor between the guard ring 5 and the diffusion layer 6 and the bypass capacitor between the diffusion layer 6 and the electrode 8 are connected in parallel to the power supply, and their capacitances are added. Therefore, the capacity of the entire decap increases.

FIG. 4 is a modification of the embodiment of FIG. An insulating film 11 is formed on the semiconductor substrate 2 including the electrode 8, and an electrode 9 is formed inside the insulating film 11 and above the electrode 8 in a ring shape along the electrode 8.
An electrode 10 is formed on the insulating film 11 so as to cover the element region 4. The electrode 9 is connected to the power supply terminal VSS, and the electrode 10 is connected to the power supply terminal VDD. In this case, the electrodes 8 and 9 and the electrodes 10 and 9 form a bypass capacitor, and the area for shielding the element formation region 4 is increased. The capacitance of the capacitor between the electrode 10 and the electrode 9 may not be large. Further, the insulating film 11 may be an interlayer insulating film. Alternatively, the capacitor 8 may be formed by repeatedly stacking decaps by the electrode 8 and the electrode 9 with the insulating film 11 interposed therebetween. In this case, the power supply terminals VDD and VSS connected to the respective electrodes are connected alternately. Therefore, each capacitor is connected in parallel to the power supply. Further, the electrode 9 may be formed along the surface of the semiconductor device 2 and beside the electrode 8 via the insulating film 11. The guard ring 5 is P
In the case of the type, the guard ring is connected to the negative power supply terminal VSS and the diffusion layer 6
Are connected to the positive power supply terminal VDD, the electrode 8 is connected to the negative power supply terminal VSS, the electrode 9 is connected to the positive power supply terminal VDD, and the electrode 10 is connected to the negative power supply terminal VSS.

In the above embodiment, when the electrode 10 covering the surface of the element formation region 4 is formed, the entire upper surface of the circuit in that region is shielded, and the shield area is increased.
Increases the shielding effect. Further, when a decap is formed by alternately laminating insulating films and electrodes in a direction perpendicular to the surface of the semiconductor substrate 2 to form a multilayer, the noise from the direction along the surface of the semiconductor substrate due to the shielding effect of the electrodes of the decap is provided. Less susceptible. In particular, it is effective for high-frequency noise such as noise associated with the operation of the digital circuit at the rising and falling of the clock. In this case, when two power supply terminals connected to each electrode are connected alternately, those decaps are connected in parallel, and their capacitances are added. Therefore, the capacity of the decaps per unit area can be increased, and the area efficiency is improved. (Modification 2) FIG. 5 is a plan view showing Modification 2 of the embodiment of the present invention. The configurations of the guard ring and the decap are the same as those in the above embodiment, and show how the decaps are arranged inside the semiconductor device 12. 1 are given the same reference numerals. Hereinafter, differences will be mainly described.

For example, an integrated guard ring 5 and a bypass capacitor 7 according to the above-described embodiment are provided for a circuit that generates a large noise or a circuit that is susceptible to the noise. That is, the circuit inside the semiconductor device 12 is divided according to the operation, and the region where the circuit is formed is divided. Alternatively, they are simply divided into regions by layout. A guard ring 5 and a bypass capacitor 7 are formed for each area.

For example, as shown in FIG. 5, an analog circuit 4, a ROM or a RAM 4a, a clock and timing generation circuit (hereinafter referred to as TG) 4b, a central processing unit (hereinafter referred to as CPU) 4c, and other logic circuits (Hereinafter L
C) and divided into five 4d circuit blocks,
The circuit is formed by dividing the circuit into five regions inside the semiconductor device 12. A bypass capacitor 7 is formed around the analog circuit region 4 by the guard ring 5 and the diffusion layer 6. The bypass capacitor 7 has a positive power terminal VDD and a negative power terminal VSS.
Connected between Similarly, a bypass capacitor 7b composed of a guard ring 5a and a diffusion layer 6a is formed around the ROM or RAM area 4a. Similarly, the guard rings 5b, 5c, 5d and the diffusion layers 6 are respectively formed in the TG region 4b, the CPU region 4c, and the LC region 4d.
b, 6c and 6d, respectively, decaps 7c and 7
d and 7e are formed.

In the above embodiment, when this guard ring is formed around a circuit that generates a large noise and a circuit that is vulnerable to the noise, the large noise generated by the circuit that generates the large noise is generated by another circuit. The shield effect is further enhanced by the synergistic effect that the circuit is less likely to be transmitted to the circuit and the circuit that is weak to noise is less likely to be affected by noise from other circuits.

The guard ring may be formed vertically deep. Further, it may be formed so as to cover under the substrate of the circuit to be guarded. In this case, the guard effect, that is, the shielding effect is increased. Note that one of the positive power supply terminal VDD and the negative power supply terminal VSS may be a ground terminal.

[0033]

As described above, according to the present invention, there is provided a semiconductor device which is suitable for high integration, large scale, hybrid of analog and digital circuits, and has high reliability of operation in a noisy environment. Can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a perspective view illustrating an example of a conventional semiconductor device.

FIG. 7 is a cross-sectional view illustrating an example of a conventional semiconductor device.

[Explanation of symbols]

1, 12: semiconductor device, 2: semiconductor substrate, 3, 5, 5a, 5b, 5c, 5d: guard ring, 4, 4a, 4b, 4c, 4d: element formation region, 6, 6a, 6b, 6c, 6d ... Diffusion layers serving as electrodes of decaps, 7, 7a, 7b, 7c, 7d, 7e ... decaps inside the semiconductor device, 8, 9, 10 ... electrodes of decaps, 8a ... insulating film between electrodes of decaps, 11 ... insulation Membrane, VDD: Positive power supply terminal, VSS: Negative power supply terminal.

Continued on the front page F term (reference) 5F038 AC01 AC03 AC05 AC06 AC20 AV06 BH09 BH19 DF12 EZ20 5F048 AA00 AA01 AC03 BA01 CC05 CC19

Claims (7)

[Claims] A semiconductor substrate including an element forming region; a first conductive type formed around the element forming region in the semiconductor substrate, connected to a first power supply terminal, and shielding the element forming region. A first diffusion layer, and a second conductivity type second diffusion layer formed inside the first diffusion layer and connected to a second power supply terminal, wherein the first diffusion layer and the second diffusion layer are A semiconductor device, which is reverse-biased to form a capacitor. A second insulating layer formed on at least the second diffusion layer; a second insulating layer formed on the first insulating film and connected to the first power supply terminal; 2. The semiconductor device according to claim 1, further comprising a first electrode forming a capacitor with the first electrode. 3. A semiconductor substrate including an element formation region, a diffusion layer formed around the element formation region in the semiconductor substrate, connected to a second power supply terminal, and shielding the element formation region; A first insulating film formed on the layer; and a first electrode formed on the first insulating film, connected to a first power supply terminal, and forming a capacitor with the diffusion layer. A semiconductor device characterized by the above-mentioned. 4. A second electrode provided on said first electrode via a second insulating film and connected to said second power supply terminal, and a third insulating film provided on said second electrode. 4. A parallel-connected capacitor formed by stacking at least once a capacitor including a third electrode provided through a film and connected to the first power supply terminal. 3. The semiconductor device according to claim 1. A second insulating film formed on the first electrode; a second insulating film formed on the second insulating film, connected to the second power supply terminal; A second electrode forming a capacitor; a third electrode provided on the second electrode via a third insulating film and connected to the first power supply terminal; and a third electrode provided on the second electrode. A parallel-connected capacitor formed by stacking at least once a capacitor including a fourth electrode provided thereon with a fourth insulating film interposed therebetween and connected to the second power supply terminal. The semiconductor device according to claim 2 or 3. 6. The element forming region includes a transistor including a gate insulating film formed of the same member as the first insulating film and a gate electrode formed of the same member as the first electrode. The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. 7. An interlayer insulating film formed on the entire surface of the semiconductor substrate, and a shield electrode formed on the interlayer insulating film so as to cover the element formation region and connected to one of the power supply terminals. 4. The semiconductor device according to claim 1, wherein the semiconductor device is provided.