JP2007081044A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the shielding effect according to a shielding unit by suppressing the parasitic capacitance between a capacitive element and the shielding unit. <P>SOLUTION: The shielding unit comprises a first conductor formed in the same wiring layer as the electrodes of the capacitive element so as to surround the capacitive element in a plane, and a second conductor formed in the wiring layer upper than that wherein the electrodes of the capacitive element are formed so as to surround the capacitive element in a plane and extended to the side of the capacitive element than the first conductor in the plane. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a capacitive element, and more particularly to a shield of a capacitive element.

  Japanese Patent Application Laid-Open No. 2001-177056 (Patent Document 1) discloses a technique for obtaining a large-capacity capacitive element with a small area by using a multilayer wiring layer on a semiconductor substrate. In this capacitive element, an interlayer insulating film is sandwiched between the first electrode and the second electrode, and the first electrode and the second electrode are arranged so that the first electrode and the second electrode face each other in the planar direction and the thickness direction. It has a structure with multiple arrangements.

  Japanese Patent Laid-Open No. 2001-196536 (Patent Document 2) surrounds a capacitive element with a shield body that is fixed at a predetermined potential to suppress noise on the capacitive element (to stabilize the charge and discharge of the capacitive element). The technology is disclosed. The same Patent Document 2 also discloses the capacitive element of Patent Document 1.

JP 2001-177056 A JP 2001-196536 A

  In the capacitor element described in Patent Document 1, an electrode is formed using a wiring layer in which wirings connecting elements of an integrated circuit are formed, and an interlayer insulating film is used as a capacitor material (dielectric film) as it is. In the multilayer wiring process, both the horizontal direction (planar direction) and the vertical direction (thickness direction) can be used as capacitance. With the progress of microfabrication technology, the distance between the electrodes in the horizontal direction has decreased, and the distance between the electrodes in the vertical direction has also decreased in accordance with the horizontal direction, so that a practical capacitance value can be obtained.

  However, since the capacitive element is formed by a normal wiring process, interference between the capacitive element and the signal wiring occurs. Therefore, interference can be prevented by providing a shield metal (shield body) between the capacitive element and the signal wiring and connecting the shield metal to the GND wiring or the power supply wiring.

  However, if interference is prevented in this way, parasitic capacitance is generated between the capacitive element and the shield metal. This parasitic capacitance cannot be basically reduced to 0, but can be reduced by setting a distance. However, if the parasitic capacitance is reduced at a distance, the shielding effect is reduced. That is, the parasitic capacitance and the shielding effect are in a trade-off relationship.

  An object of the present invention is to provide a technique capable of suppressing a parasitic capacitance generated between a capacitive element and a shield body and improving a shield effect by the shield body.

  The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  The object is to form a first conductor on the same wiring layer as the electrode of the capacitive element so as to surround the capacitive element in a plane, and to form a wiring layer above the wiring layer on which the electrode of the capacitive element is formed. Forming a second conductor extending from the first conductor to the capacitor element side so as to surround the capacitor element in a plan view, and setting the first and second conductors to a predetermined potential. This is achieved by fixing. For example:

(1) A semiconductor device includes a capacitive element, a shield body that is fixed at a predetermined potential, and a plurality of wiring layers that are stacked in multiple stages on the semiconductor substrate with an insulating film interposed therebetween,
The capacitive element has a first electrode and a second electrode formed on the first wiring layer of the plurality of wiring layers so as to face each other with the insulating film interposed therebetween,
The shield body includes a first conductor formed so as to surround the capacitive element in a plane in the first wiring layer, and a first layer higher than the first wiring layer of the plurality of wiring layers. And a second conductor that is formed on the two wiring layers so as to surround the capacitor element in a plan view and extends in a plane more to the capacitor element side than the first conductor.

(2) In the means (1),
The second conductor is extended to the capacitive element side so as not to overlap the first and second electrodes in plan view.

(3) In said means (1),
The insulating film between the second conductor and the first conductor is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the second conductor. Or a conductive plug is embedded,
The second conductor and the first conductor are electrically connected to each other via a part of the second conductor or the conductive plug.

(4) In the means (1),
The distance a between the first electrode and the one of the second electrodes adjacent to the first conductor and the first conductor is the distance between the first electrode and the first electrode. It is larger than the distance b between the two electrodes (a> b).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, a shielding effect is obtained while suppressing the parasitic capacitance generated between the capacitive element and the shield body (suppressing the parasitic capacitance generated between the capacitive element and the shield body and improving the shielding effect by the shield body). Can).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

  In the first embodiment, an example in which a capacitive element in which a first electrode and a second electrode are formed on each of a plurality of wiring layers is shielded by a shield body will be described.

1 to 13 are diagrams related to a system IC (semiconductor device) that is Embodiment 1 of the present invention.
FIG. 1 is a plan layout diagram of a system IC,
FIG. 2 is an equivalent circuit diagram of a filter circuit mounted on the filter circuit unit of FIG.
3 is a schematic cross-sectional view (cross-sectional view taken along the line aa ′ in FIG. 6) showing a schematic configuration of the capacitive element and the shield body of FIG.
4 is a schematic cross-sectional view enlarging a part of FIG.
5 is a schematic cross-sectional view (cross-sectional view taken along the line bb ′ of FIG. 6) showing a schematic configuration of the capacitive element and the shield body of FIG.
6 is a schematic plan view showing a planar pattern of a conductor formed on the fourth metal wiring layer of FIG.
FIG. 7 is a schematic plan view showing a planar pattern of electrodes and conductors formed in the third metal wiring layer of FIG.
FIG. 8 is a schematic plan view showing a planar pattern of electrodes and conductors formed in the second metal wiring layer of FIG.
FIG. 9 is a schematic plan view showing a planar pattern of electrodes and conductors formed in the first metal wiring layer of FIG.
10 is a schematic cross-sectional view taken along the line cc ′ of FIG.
FIG. 11 is a schematic cross-sectional view taken along the line dd ′ of FIG.

  As shown in FIG. 1, the system IC (Integrated Circuit) of the first embodiment includes an amplifier circuit unit 101, each of which is an analog circuit, in a region surrounded by a plurality of external terminals (bonding pads) 107. A configuration having a filter circuit unit 102, an A / D (Analog Digital) conversion circuit unit 103, a PLL (Phase Locked Loop) circuit unit 104, a power supply circuit unit 105, and the like, and further including a logical operation circuit unit 106 formed of a digital circuit It has become. Each of these circuit portions has a CMIS (Complementary MIS) circuit configuration in which, for example, an n-channel conductivity type MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a p-channel conductivity type MISFET are combined as transistor elements.

  A plurality of high-pass filter circuits HPF shown in FIG. The high-pass filter circuit HPF mainly includes an amplifier 108 and a capacitive element C. The capacitive element C is connected to the input portion of the amplifier 108 and shielded by a shield body S that is fixed at a predetermined potential. Hereinafter, specific configurations of the capacitive element C and the shield body S will be described with reference to FIGS. 3 to 11. In the present embodiment, the potential fixed to the shield body S is designed to be the ground potential that is the same as the reference potential of the high-pass filter circuit HPF.

  As shown in FIG. 3, the system IC has a configuration including a semiconductor substrate 1 (hereinafter simply referred to as a substrate 1) and a multilayer wiring layer 1 a provided on the main surface of the substrate 1. As the substrate 1, for example, a p-type substrate made of single crystal silicon is used. The multilayer wiring layer 1a has a structure having a plurality of metal wiring layers, each of which is laminated in multiple stages with an interlayer insulating film interposed therebetween. The multilayer wiring layer 1a of the first embodiment is not limited to this, but has, for example, a seven-layer metal wiring structure. 3 to 5 and FIGS. 10 and 11, the first to fourth metal wiring layers (M1 to M4) counted from the substrate 1 side are shown, and the fifth to seventh layers are shown. The illustration of the metal wiring layers (M5 to M7) of the eyes is omitted.

  As shown in FIG. 3, the capacitive element C of Example 1 is formed in each metal wiring layer across the first to third metal wiring layers (M1 to M3) of the multilayer wiring layer 1a. The formed electrodes (11a, 21a, 31a) are used as first electrodes, and are formed in each metal wiring layer across the first to third metal wiring layers (M1 to M3) of the multilayer wiring layer 1a. The formed electrodes (12a, 22a, 32a) are used as second electrodes, and the interlayer insulating film (10, 20, 30) sandwiched between the first electrodes and the second electrodes is used as a capacitive material (dielectric material). Film).

  Each interlayer insulating film (10, 20, 30) is formed of, for example, a silicon oxide film. Each metal wiring layer (M1 to M4, M5 to M7) is formed of a metal film such as copper (Cu) or a copper alloy, for example.

  The plurality of electrodes 11 a and the electrodes 12 a are formed in the first-layer metal wiring layer M <b> 1 and are embedded in a groove provided in the interlayer insulating film 10 on the substrate 1. The plurality of electrodes 21 a and the electrodes 22 a are formed in the second-layer metal wiring layer M <b> 2 and are embedded in a groove provided in the interlayer insulating film 20 on the interlayer insulating film 10. The plurality of electrodes 31 a and the electrodes 32 a are formed of the third-layer metal wiring layer M <b> 3 and are embedded in a groove provided in the interlayer insulating film 30 on the interlayer insulating film 20.

  The interlayer insulating film 10 is provided mainly for the purpose of electrically separating the substrate 1 and the first metal wiring layer M1. The interlayer insulating film 20 is provided mainly for the purpose of electrically separating the first metal wiring layer M1 from the second metal wiring layer M2. The interlayer insulating film 30 is provided mainly for the purpose of electrically separating the second metal wiring layer M2 and the third metal wiring layer M3.

  In the third-layer metal wiring layer M3, as shown in FIG. 7, the plurality of electrodes 31a and the electrodes 32a extend in a stripe shape along the Y direction, and are alternately specified one by one along the X direction. Are arranged at intervals. One end of each of the plurality of electrodes 31a is formed on the third metal wiring layer M3 and integrated with an electrode 31b extending in a stripe shape along the X direction. One end side of each of the plurality of electrodes 32a is integrated with an electrode 32b formed in the third metal wiring layer M3 and extending in a stripe shape along the X direction. The other end side (opposite side of one end side) of each of the plurality of electrodes 31a is extended to the vicinity of the electrode 32b, and the other end side (opposite side of one end side) of each of the plurality of electrodes 32a is It is extended to the vicinity of the electrode 31b. The electrode 31b and the electrode 32b are embedded in a groove provided in the interlayer insulating film 30 similarly to the electrode 31a and the electrode 32a.

  Here, the X direction and the Y direction indicate directions orthogonal to each other in the same plane, for example, in the plane of the substrate 1.

  In the plane direction of the substrate 1, as shown in FIGS. 7 and 3, the electrode 31 a faces the electrodes 32 a and 32 b with the interlayer insulating film 30 interposed therebetween, and the electrode 32 a is an electrode with the interlayer insulating film 30 interposed therebetween. It faces 31a and the electrode 31b.

  In the second metal wiring layer M2, as shown in FIG. 8, the plurality of electrodes 21a and the electrodes 22a extend in a stripe shape along the Y direction, and are alternately specified one by one along the X direction. Are arranged at intervals. One end side of each of the plurality of electrodes 21a is integrated with an electrode 21b formed in the second metal wiring layer M2 and extending in a stripe shape along the X direction. One end of each of the plurality of electrodes 22a is formed on the second metal wiring layer M2 and integrated with an electrode 22b extending in a stripe shape along the X direction. The other end side (opposite side of one end side) of each of the plurality of electrodes 21a is extended to the vicinity of the electrode 22b, and the other end side (opposite side of one end side) of each of the plurality of electrodes 22a is It is extended to the vicinity of the electrode 21b. The electrode 21b and the electrode 22b are embedded in a groove provided in the interlayer insulating film 20 similarly to the electrode 21a and the electrode 22a.

  In the planar direction of the substrate 1, as shown in FIGS. 8 and 3, the electrode 21a faces the electrode 22a and the electrode 22b with the interlayer insulating film 20 interposed therebetween, and the electrode 22a is an electrode with the interlayer insulating film 20 interposed therebetween. It faces 21a and the electrode 21b.

  In the first metal wiring layer M1, as shown in FIG. 9, the plurality of electrodes 11a and electrodes 12a extend in a stripe shape along the Y direction, and are alternately specified one by one along the X direction. Are arranged at intervals. One end of each of the plurality of electrodes 11a is formed on the first metal wiring layer M1 and integrated with an electrode 11b extending in a stripe shape along the X direction. One end side of each of the plurality of electrodes 12a is integrated with an electrode 12b formed in the first metal wiring layer M1 and extending in a stripe shape along the X direction. The other end side (opposite side of the one end side) of each of the plurality of electrodes 11a is extended to the vicinity of the electrode 12b, and the other end side (opposite side of the one end side) of each of the plurality of electrodes 12a is It is extended to the vicinity of the electrode 11b. The electrode 11b and the electrode 12b are embedded in a groove provided in the interlayer insulating film 10 similarly to the electrode 11a and the electrode 12a.

  9 and 3, in the planar direction of the substrate 1, the electrode 11a faces the electrode 12a and the electrode 12b with the interlayer insulating film 10 interposed therebetween, and the electrode 12a has the electrode with the interlayer insulating film 10 interposed therebetween. 11a and the electrode 11b.

  As shown in FIG. 7, the electrode 31b of the third layer terminates at a portion where one end side is connected to the first-stage electrode 31a among the plurality of electrodes 31a, and the other end side opposite to the one end side is integrated with the wiring 31L. Has been. The third layer electrode 32b terminates at a portion where one end side faces the first-stage electrode 31a among the plurality of electrodes 31a, and the other end side opposite to the one end side is integrated with the wiring 32L. The wirings 31L and 32L are embedded in the trenches provided in the interlayer insulating film 30, like the electrodes 31a and 32a.

  The first layer electrode 11a (see FIG. 9), the second layer electrode 22a (see FIG. 8), and the third layer electrode 31a (see FIG. 7) are as shown in FIGS. In the thickness direction of the substrate 1 (vertical direction orthogonal to the plane direction of the substrate 1), the layers are three-dimensionally arranged with the interlayer insulating films (10, 20, 30) interposed therebetween so as to overlap in a plane.

  The first layer electrode 12a (see FIG. 9), the second layer electrode 21a (see FIG. 8), and the third layer electrode 32a (see FIG. 7) are as shown in FIGS. In the thickness direction of the substrate 1, they are three-dimensionally arranged with the interlayer insulating films (10, 20, 30) therebetween so as to overlap in a plane.

  The first layer electrode 11b (see FIG. 9), the second layer electrode 21b (see FIG. 8), and the third layer electrode 31b (see FIG. 7) are formed on the substrate 1 as shown in FIG. Are arranged in a three-dimensional manner with the interlayer insulating films (10, 20, 30) interposed therebetween so as to overlap in a plane.

  As shown in FIG. 5, the first layer electrode 12b (see FIG. 9), the second layer electrode 22b (see FIG. 8), and the third layer electrode 32b (see FIG. 7) are formed on the substrate 1 as shown in FIG. Are arranged in a three-dimensional manner with the interlayer insulating films (10, 20, 30) interposed therebetween so as to overlap in a plane.

  As shown in FIGS. 8 and 10, a plurality of connection holes 20a are provided in the interlayer insulating film 20 between the first layer electrode 11b and the second layer electrode 21b. For example, a part of the second layer electrode 21b is embedded in each of the plurality of connection holes 20a, and the electrode 11b and the electrode 21b are electrically connected to each other through a part of the electrode 21b. Yes.

  As shown in FIGS. 8 and 10, a plurality of connection holes 20b are provided in the interlayer insulating film 20 between the first layer electrode 12b and the second layer electrode 22b. For example, a part of the second layer electrode 22b is embedded in each of the plurality of connection holes 20b, and the electrode 12b and the electrode 22b are electrically connected to each other through a part of the electrode 22b. Yes.

  As shown in FIGS. 7 and 10, a plurality of connection holes 30a are provided in the interlayer insulating film 30 between the second layer electrode 21b and the third layer electrode 31b. For example, a part of the third layer electrode 31b is embedded in each of the plurality of connection holes 30a, and the electrode 21b and the electrode 31b are electrically connected to each other through a part of the electrode 31b. Yes.

  As shown in FIGS. 7 and 10, a plurality of connection holes 30b are provided in the interlayer insulating film 30 between the second layer electrode 22b and the third layer electrode 32b. For example, a part of the third layer electrode 32b is embedded in each of the plurality of connection holes 30b, and the electrode 22b and the electrode 32b are electrically connected to each other through a part of the electrode 32b. Yes.

  In the plane direction of the substrate 1, as shown in FIG. 4, the interlayer insulating film 10 sandwiched (intervened) between the electrode 11a and the electrode 12a functions as a dielectric film, and a capacitor is formed in this portion. The The interlayer insulating film 20 sandwiched (intervened) between the electrode 21a and the electrode 22a functions as a dielectric film, and a capacitor is formed in this portion. The interlayer insulating film 30 sandwiched (intervened) between the electrode 31a and the electrode 32b functions as a dielectric film, and a capacitor is formed in this portion.

  In the thickness direction of the substrate 1, as shown in FIG. 4, the interlayer insulating film 20 sandwiched between the electrode 11a and the electrode 22a and between the electrode 12a and the electrode 21a functions as a dielectric film. A capacitance is formed in the portion. The interlayer insulating film 30 sandwiched (intervened) between the electrode 21a and the electrode 32a and between the electrode 22a and the electrode 31a functions as a dielectric film, and a capacitance is formed in this portion.

  That is, the capacitive element C of Example 1 has a configuration in which a plurality of first electrodes and second electrodes are arranged so that the first electrode and the second electrode face each other in the planar direction and the thickness direction. ing. With such a configuration, the effective area between the electrodes of the interlayer insulating film (dielectric film) between the first electrode and the second electrode can be increased without increasing the occupied area. Thus, a capacitive element C having a small area and a large capacity can be obtained.

  In the planar direction of the substrate 1, as shown in FIG. 5, the interlayer insulating film 10 sandwiched between the electrode 11a and the electrode 12b, the interlayer insulating film 20 sandwiched between the electrode 21b and the electrode 22a, In addition, the interlayer insulating film 30 sandwiched between the electrode 31a and the electrode 32b also functions as a dielectric film, and a capacitance is also formed in this portion.

  As shown in FIG. 10, the interlayer insulating film 10 sandwiched between the electrode 11b and the electrode 12a, the interlayer insulating film 20 sandwiched between the electrode 21a and the electrode 22b, and the electrode 31b and the electrode 32a The interlayer insulating film 30 sandwiched between them also functions as a dielectric film, and a capacitor is formed also in this portion.

  Therefore, the electrodes 11b, 21b, and 31b may be regarded as the first electrode of the capacitive element C, and the electrodes 12b, 22b, and 32b may be regarded as the second electrode of the capacitive element C.

  One of the first and second electrodes of the capacitive element C is electrically connected to the input portion of the amplifier 108 via one of the wirings 31L and 32L.

  As shown in FIG. 3, the shield body S of Example 1 was formed in the same metal wiring layer as the electrode of the capacitive element C corresponding to the number of layers of the metal wiring layer in which the electrode of the capacitive element C was formed. A conductor (13, 23, 33) and a conductor 43 formed in a metal wiring layer one layer higher than the uppermost metal wiring layer among the metal wiring layers in which the electrodes of the capacitive element C are formed. And an n-type semiconductor region 3 formed on the main surface of the substrate 1. In Example 1, the capacitor C has electrodes formed on each metal wiring layer across the first to third metal wiring layers (M1 to M3). Therefore, the conductors (13, 23, 33) are formed on the first to third metal wiring layers (M1 to M3), and the conductor 43 is formed on the fourth metal wiring layer M4. Is formed.

  As shown in FIGS. 3 and 9, the first-layer conductor 13 is continuously formed so as to surround the first-layer electrodes (11a, 11b, 12a, 12b) of the capacitive element C in a plane. As with these first layer electrodes, they are buried in the trenches provided in the interlayer insulating film 10.

  As shown in FIGS. 3 and 8, the second-layer conductor 23 is continuously formed so as to surround the second-layer electrodes (21a, 21b, 22a, 22b) of the capacitive element C in a plane. Like the second-layer electrodes, these are buried in the trenches provided in the interlayer insulating film 20.

  As shown in FIGS. 3 and 7, the third-layer conductor 33 is partially removed so as to surround the third-layer electrodes (31a, 31b, 32a, 32b) of the capacitive element C in a plane. It is formed continuously, and is embedded in a groove provided in the interlayer insulating film 30 like the third layer electrode. As shown in FIG. 7, a part of the conductor 33 is interrupted, and wirings 31L and 32L are drawn across the part.

  As shown in FIGS. 3 and 6, the fourth-layer conductor 43 is formed so as to surround the capacitive element C in a plane, and like the other conductors (13, 23, 34), the interlayer insulating film 40. Embedded in a groove provided in the. As shown in FIG. 6, a part of the conductor 43 is integrally connected with a wiring 43 </ b> L formed in the same metal wiring layer M <b> 4 as the conductor 43. The wiring 43 </ b> L is embedded in a groove formed in the interlayer insulating film 40 as with the conductor 43.

  As shown in FIGS. 3 and 5, the n-type semiconductor region 3 is formed in a larger planar size than the capacitive element C so as to overlap the capacitive element C in a plane. The n-type semiconductor region 3 is covered with a field insulating film 2 formed on the main surface of the substrate 1 in a region overlapping with the capacitive element C.

  An n-type semiconductor region 4 having a hole impurity concentration higher than that of the n-type semiconductor region 3 is provided on the main surface of the n-type semiconductor region 3. The n-type semiconductor region 4 is formed so as to surround the capacitive element C in a plane and to overlap the conductor 13 in a plane. The n-type semiconductor region 4 is formed mainly for the purpose of reducing the contact resistance between the n-type semiconductor region 3 and the conductor 13.

  First layer conductor 13 (see FIG. 9), second layer conductor 23 (see FIG. 8), third layer conductor 33 (see FIG. 7), and fourth layer conductor As shown in FIG. 5, 43 is arranged in a three-dimensional manner with interlayer insulating films (10, 20, 30, 40) sandwiched in a plane in the thickness direction of the substrate 1.

  As shown in FIGS. 3 and 10, a plurality of connection holes 10 c are provided in the interlayer insulating film 10 between the n-type semiconductor region 4 and the first-layer conductor 13. In each of the plurality of connection holes 10 c, for example, a part of the first-layer conductor 13 is embedded, and the n-type semiconductor region 4 and the conductor 13 are mutually connected via a part of the conductor 13. Electrically connected. Further, the conductor 13 is electrically connected to the n-type semiconductor region 3 through a part of the conductor 13 and the n-type semiconductor region 4.

  As shown in FIGS. 3 and 8, a plurality of connection holes 20 c are provided in the interlayer insulating film 20 between the first-layer conductor 13 and the second-layer conductor 23. In each of the plurality of connection holes 20 c, for example, a part of the second-layer conductor 23 is embedded, and the conductor 13 and the conductor 23 are electrically connected to each other through a part of the conductor 23. It is connected to the.

  As shown in FIGS. 3 and 7, a plurality of connection holes 30 c are provided in the interlayer insulating film 30 between the second-layer conductor 23 and the third-layer conductor 33. In each of the plurality of connection holes 30 c, for example, a part of the third-layer conductor 33 is embedded, and the conductor 23 and the conductor 33 are electrically connected to each other through a part of the conductor 33. It is connected to the.

  As shown in FIGS. 3 and 6, a plurality of connection holes 40 c are provided in the interlayer insulating film 40 between the third-layer conductor 33 and the fourth-layer conductor 43. In each of the plurality of connection holes 40 c, for example, a part of the conductor 43 of the fourth layer is embedded, and the conductor 33 and the conductor 43 are electrically connected to each other through a part of the conductor 43. It is connected to the.

  The shield body S configured as described above is fixed at, for example, a reference potential (for example, 0 V) among power supply potentials used in the system IC during circuit operation. In the first embodiment, the potential of the shield body S is fixed through the wiring 43L shown in FIG.

  As shown in FIG. 4, the fourth-layer conductor 43 is planarly extended to the capacitive element C side from the first-layer to third-layer conductors (13, 23, 33). Yes. In other words, the conductor 43 protrudes closer to the capacitive element C than the conductors (13, 23, 33). As shown in FIGS. 4 to 6, the conductor 43 is extended to the capacitive element C side so as not to overlap the electrode of the capacitive element C in a plan view. That is, the conductor 43 includes the conductors 13, 23, and 33 that form the first to third wiring layers in a plan view, and the outermost conductor (of the conductor that forms the capacitor element C). 11a, 22a, 31a, etc.).

  As shown in FIGS. 4 to 10, the distance m1 between the third-layer conductor 33 and the third-layer electrodes (31a, 31b, 32a, 31b) adjacent to the conductor 33 is It is larger than the distance m2 between the electrode 31a and the electrode 32b. Also in the second layer and the first layer, the conductors (23, 13) and the electrodes (21a, 21b, 22a, 21b: 11a, 11b, 12a, 12b) adjacent to the conductors 23 The distance m1 is larger than the distance m2 between the electrodes (21a, 11a) and the electrodes (22b, 12b).

  As shown in FIGS. 3 and 6 to 9, signal wirings (14, 24, 34, 44) are formed in the first to fourth metal wiring layers (M1 to M4), respectively. Yes. A shield body S is formed between the signal wires (14, 24, 34, 44) and the capacitive element C. The signal wiring (14, 24, 34, 44) is embedded in the groove provided in each interlayer insulating film, like the electrode of the capacitive element C and the conductor of the shield body S. The conductor forming the shield body S is connected to the p-type semiconductor region 4 provided on the substrate 1 and is formed to have a ground potential.

  By the way, metal capacitors used in LSIs are desired to have high accuracy and small parasitic capacitance. It is desirable that the unit capacity is large, but when used at high frequencies, accuracy is a priority, the size is determined to obtain accuracy, and the capacity value may be better in terms of speed. Not necessarily good.

  In general, a parallel plate type metal capacitor in which a high dielectric film is sandwiched between two electrodes is used. The capacity of this parallel plate type is satisfactory in terms of performance, but since an extra mask and manufacturing process are required, a capacity capable of obtaining equivalent performance at a lower price is desired. A metal capacitor that uses the capacitance between wirings in the same layer and the interlayer capacitance in the upper and lower layers is attracting attention as an inexpensive capacitance that does not require an extra manufacturing process.

  However, if the layout as a capacitive element is not devised, the metal wiring (metal electrode) as the capacitive element and the metal wiring (signal wiring) extending in the vicinity may interfere with each other, causing abnormal operation. is there. In order to prevent the metal electrode of the capacitive element and the metal wiring from interfering with each other, a shield metal (shield body) may be disposed between the capacitive element and the metal wiring.

  However, a capacitance is generated between the shield metal and the metal electrode of the capacitive element, and this becomes a parasitic capacitance for the capacitive element (see the parasitic capacitance pc in FIG. 2). In order to reduce this parasitic capacitance, it is necessary to increase (increase) the distance between the metal electrode of the capacitive element and the shield metal. If this distance is increased, the parasitic capacitance decreases, but the shielding effect Will fade. In many cases, the shield effect is insufficient when the parasitic capacitance is suppressed so that the design can be compromised.

  When the shield effect is given priority, a method of completely enclosing the upper, lower, left, and right sides of the capacitive element can be considered. However, a problem is that the parasitic capacitance between the shield metal in the vertical direction increases. Therefore, as a countermeasure, a method of separating one layer in order to take a distance in the vertical direction can be considered. Thus, a capacitive element having a shielding effect and a small parasitic capacitance can be obtained, but the capacitance value becomes small because the metal layer originally used can be sacrificed. Further, as the capacitance value becomes smaller, the variation of the capacitance value becomes worse.

  A feature of the present invention is that the shield metal in the vertical direction is provided only around the capacitor element and not on the upper surface of the capacitor element.

  The state of interference can be easily understood by drawing electric lines of force. FIG. 12 is a schematic cross-sectional view showing a state of lines of electric force when a shield metal is disposed between two electrodes.

  In FIG. 12, the electrode z1 is set to 1V, and both the electrode z2 and the shield metal s1 are set to 0V. The electric lines of force go from the electrode z1 to the electrode z2 and the shield metal s1, but most electric lines of force are absorbed by the shield metal s1 and do not reach the electrode z2. However, a slight electric field line going in the vertical direction gets over the shield metal s1 and reaches the electrode z2.

  The effect of the shield metal s1 can be seen from FIG. FIG. 13 is a schematic cross-sectional view showing each pattern ((a) to (e)) used in the simulation of the shielding effect. FIG. 14 summarizes the simulation results of the patterns of (a) to (e) in FIG. 13, and is a diagram illustrating the capacitance value as a result of coupling with the lines of electric force leaked.

In FIG.
(A) is a pattern in which the shield metal s1 is not disposed between the electrode z1 and the electrode z2.
(B) is a pattern in which a shield metal s1 is disposed between the electrode z1 and the electrode z2. This pattern (b) is the same as FIG.
(C) The upper and lower sides of the shield metal s1 between the two electrodes so as to surround the electrode z1 with the shield metal s1, project the shield metal s1 upward from the electrode z1, and not cover the electrode z1. Is a pattern that protrudes toward the electrode z1.
(D) is a pattern in which the upper part of the shield metal s1 between the two electrodes (between the electrodes z1 and z2) is not protruded toward the electrode z1 as compared with (c).
(E) is a pattern in which the shield metal s1 on the side opposite to the electrode z2 (left side in the figure) is set to the same height as the electrode z1 as compared with (c).

  Referring to FIG. 14, as a result of inserting the shield metal s1 as shown in FIGS. 13A to 13B, the coupling capacity is reduced to about 1/10. It is expected that a greater shielding effect can be obtained by inserting the shield metal s1 so as to block the lines of electric force. In the upper surface open patterns of FIGS. 13C to 13E, the shield effect is the largest in the case of (d). Comparing (c) and (d), it can be seen that a large effect can be obtained by projecting the shield metal s1 to the periphery.

  In the first embodiment, as shown in FIG. 3, the conductor 43 formed in the metal wiring layer one layer higher than the uppermost metal wiring layer of the metal wiring layers in which the electrodes of the capacitive element C are formed. Than the conductor (13, 23, 33) formed in the same metal wiring layer as the electrode of the capacitive element C corresponding to the number of metal wiring layers in which the electrode of the capacitive element C is formed. Projected sideways on the side. With such a configuration, the shielding effect of the shield body S can be improved without covering the capacitive element C with the conductor 43. Therefore, the parasitic capacitance pc generated between the capacitive element C and the shield body S is suppressed, and the shielding effect by the shield body S is improved (the shield is performed while suppressing the parasitic capacitance generated between the capacitive element C and the shield body S small). Effect).

  When the third layer electrode (31a, 31b, 32a, 32b) and the conductor 43 overlap in a plane, the parasitic capacitance between the third layer electrode and the conductor 43 increases. Therefore, it is desirable to extend the conductor 43 to the capacitive element C side as much as possible so that the third layer electrode and the conductor 43 do not overlap in plan view.

  Referring to FIG. 4, the capacitance of the capacitive element C is increased by reducing the distance m2 between the first electrode and the second electrode. On the other hand, the parasitic capacitance generated between the electrode of the capacitive element C and the conductor of the shield body S is increased by reducing the distance m1 between the electrode of the capacitive element C and the conductor of the shield body S. Therefore, considering the parasitic capacitance, it is desirable that the distance m1 be larger than the distance m2 (m1> m2).

  As shown in FIG. 11, the shield body S is configured by stacking conductors (13, 23, 33, 43) formed on the metal wiring layers (M1 to M4). Each conductor is electrically connected through a connection hole (10c, 20c, 30c, 40c) formed in each interlayer insulating film (10, 20, 30, 40). The interval between the connection holes is indicated by T. As the interval T is smaller, the shielding effect is increased, but since the surface facing the capacitor element electrode is increased, the parasitic capacitance is also increased. Therefore, it is desirable to determine the interval T in consideration of the parasitic capacitance and the shielding effect.

  The capacitive element C according to the first embodiment is connected to the input section of the amplifier 108 as shown in FIG. In this case, the noise on the capacitive element C is amplified as it is. Therefore, in the capacitive element C connected to the input unit of the amplifying unit 108, it is desirable to shield with the shield body S in which the conductor 43 is extended to the capacitive element C side.

  The shield body S according to the first embodiment includes an n-type semiconductor region 3 provided under the capacitive element C. On the other hand, the capacitive element C includes an electrode formed on the first metal wiring layer. In this case, a parasitic capacitance is generated between the first layer electrodes (11a, 11b, 12a, 12b) and the n-type semiconductor region 3, but the n-type semiconductor region 3 under the capacitive element C is formed on the substrate 1. Since the interlayer insulating film 10 and the field insulating film 2 formed on the main surface of the substrate 1 are covered, the parasitic capacitance generated between the first layer electrode and the n-type semiconductor region 3 is reduced. be able to.

  In the case of a parallel plate type capacitive element, the spread of electric lines of force in the plane direction is small, so that it is difficult to interfere with signal wiring extending in the vicinity. On the other hand, in the capacitive element C of Example 1, a first electrode and a second electrode that form a capacitor with an interlayer insulating film interposed therebetween are arranged in a planar direction. Such a capacitive element C has a large spread of lines of electric force applied in the plane direction, and therefore easily interferes with a signal wiring extending in the vicinity. Therefore, the present invention is particularly effective in the capacitor element C in which the first electrode and the second electrode that form a capacitor with the interlayer insulating film interposed therebetween are arranged in the plane direction as in the first embodiment.

  In the first embodiment, the example in which the capacitive element C in which the electrode is formed on each metal wiring layer across the first to third metal wiring layers is shielded by the shield body S has been described. The present invention can be applied regardless of the number of metal wiring layers in which the electrodes of the capacitive element C are formed. That is, the metal on which the electrode of the capacitive element C is formed rather than the conductor formed on the same metal wiring layer as the electrode of the capacitive element C corresponding to the number of metal wiring layers on which the electrode of the capacitive element C is formed. The conductor 43 formed in the metal wiring layer that is one layer higher than the uppermost metal wiring layer of the wiring layers may be planarly extended to the capacitor element C side. Therefore, the present invention can also be applied to a case where a capacitive element in which an electrode is formed on one metal wiring layer or a capacitive element having a larger number of layers than in the first embodiment is shielded.

  FIG. 15 is a schematic cross-sectional view showing a schematic configuration of a capacitive element and a shield body in a system IC that is Embodiment 2 of the present invention.

  The shield body S of the first embodiment includes the n-type semiconductor region 3 formed so as to overlap the capacitor element C on the main surface of the substrate 1 in a planar manner. As shown in FIG. 15, the shield body S includes a conductor 13 formed on the first metal wiring layer M1 so as to overlap the capacitor element C in a plan view.

  The capacitive element C of the second embodiment is basically the same as that of the first embodiment, and the first to the respective metal wiring layers straddling the third to fifth metal wiring layers (M3 to M5). The electrode (31a, 41a, 51a) and the second electrode (32a, 42a, 52a) are formed.

  The shield body S of the second embodiment includes a conductor 13 formed in the first metal wiring layer M1, a conductor 23 formed in the second metal wiring layer M2, and a capacitor element C. Corresponding to the number of metal wiring layers on which the electrodes are formed, the conductors (33, 43, 53) formed on the same metal wiring layer as the electrodes of the capacitive element C, and the metal on which the electrodes of the capacitive element C are formed It has a configuration having a conductor 63 formed in a metal wiring layer M6 that is one layer above the uppermost metal wiring layer M5 of the wiring layers (M3 to M5).

  The first-layer conductor 13 is formed to have a larger planar size than the capacitive element C so as to overlap the capacitive element C in a planar manner. The second to fifth layer conductors (23, 33, 43, 53) are formed so as to surround the capacitive element C in a plane. The sixth-layer conductor 63 is formed so as to surround the capacitive element C in a plan view, and conductors (23, 33, 43, 53) formed in the second to third metal wiring layers. ) To the capacitive element C side. Although not shown, the conductor forming the shield body S of the present embodiment is connected to the p-type semiconductor region 4 provided on the substrate 1 in the same manner as in the first embodiment, and is connected to the ground potential. It is formed to become.

  A plurality of connection holes 50 c are provided in the interlayer insulating film 50 between the fourth-layer conductor 43 and the fifth-layer conductor 53. In each of the plurality of connection holes 50 c, for example, a part of the fifth-layer conductor 53 is embedded, and the conductor 43 and the conductor 53 are electrically connected to each other through a part of the conductor 43. It is connected to the.

  A plurality of connection holes 60 c are provided in the interlayer insulating film 60 between the fifth-layer conductor 53 and the sixth-layer conductor 63. In each of the plurality of connection holes 60 c, for example, a part of the conductor 63 of the sixth layer is embedded, and the conductor 53 and the conductor 63 are electrically connected to each other through a part of the conductor 63. It is connected to the.

  The first-layer conductor 13 is formed in a plane size larger than that of the capacitor element C so as to overlap the capacitor element C in a plan view. One layer is formed. In this way, the electrode of the capacitive element C is formed with one layer separated from the conductor 13, in other words, the conductor 13 is formed with one layer separated from the lowermost electrode of the capacitive element C. Since the parasitic capacitance generated between the first-layer conductor 13 and the third-layer electrode can be reduced, the parasitic capacitance pc generated between the capacitive element C and the shield S can be suppressed, and the shield The shielding effect by S can be improved (the shielding effect can be obtained while suppressing the parasitic capacitance generated between the capacitive element C and the shield body S).

  FIG. 16: is typical sectional drawing which shows schematic structure of a capacitive element and a shield body in system IC which is Example 3 of this invention.

  The capacitive element C of the third embodiment is basically the same as that of the first embodiment, and the first to second metal wiring layers (M1 to M2) extending from the first to the second metal wiring layers. The electrode (11a, 21a) and the second electrode (12a, 22a) are formed.

  The shield body S of Example 3 is a conductor formed on the same metal wiring layer (M1 to M2) as the electrode of the capacitive element C corresponding to the number of metal wiring layers on which the electrode of the capacitive element C is formed. (13, 23), the conductor 33 formed on the third metal wiring layer M3, the conductor 23 formed on the fourth metal wiring layer M4, and formed on the main surface of the substrate 1. The n-type semiconductor region 3 is formed. As in the first embodiment, the conductor forming the shield body S is connected to the p-type semiconductor region 4 provided on the substrate 1 and is formed to have a ground potential.

  The conductors (13, 23, 33) from the first layer to the third layer are formed so as to surround the capacitive element C in a plane. The conductor 13 of the fourth layer is formed in a larger plane size than the capacitive element C so as to overlap the capacitive element C in a planar manner (so as to cover the capacitive element C in a planar manner).

  The fourth-layer conductor 43 is formed in a plane size larger than that of the capacitor element C so as to overlap the capacitor element C in a plan view. One layer is formed. In this way, one layer is formed with respect to the conductor 43 to form the electrode of the capacitive element C. In other words, by forming one layer with respect to the uppermost electrode of the capacitive element C, the conductor 43 is formed. Since the parasitic capacitance generated between the fourth-layer conductor 43 and the third-layer electrode can be reduced, the parasitic capacitance pc generated between the capacitive element C and the shield body S is suppressed, and the shield The shield effect by the body S can be improved (the shield effect can be obtained while suppressing the parasitic capacitance generated between the capacitive element C and the shield body S).

FIG. 17 is a schematic cross-sectional view showing a schematic configuration of a capacitive element and a shield body in a system IC (semiconductor device) that is Embodiment 4 of the present invention.
The fourth embodiment is an example in which the second and third embodiments are combined.

  The capacitive element C of the fourth embodiment is basically the same as that of the first embodiment, and the first to the respective metal wiring layers straddling the third to fourth metal wiring layers (M3 to M4). The electrode (31a, 41a) and the second electrode (32a, 42a) are formed.

  The shield body S of the fourth embodiment includes a conductor 13 formed in the first metal wiring layer M1, a conductor 23 formed in the second metal wiring layer M2, and a capacitor element C. Corresponding to the number of metal wiring layers on which the electrodes are formed, the conductors (33, 43) formed on the same metal wiring layer as the electrode of the capacitor C, and the fifth metal wiring layer M5 are formed. The conductor 53 and the conductor 63 formed in the sixth metal wiring layer M6 are configured. Although not shown, the conductor forming the shield body S is connected to the p-type semiconductor region 4 provided on the substrate 1 and formed to have a ground potential, as in the first embodiment. Has been.

  The first-layer conductor 13 is formed to have a larger planar size than the capacitive element C so as to overlap the capacitive element C in a planar manner. The second to fifth layer conductors (23, 33, 43, 53) are formed so as to surround the capacitive element C in a plane. The sixth-layer conductor 63 is formed in a larger planar size than the capacitive element C so as to overlap the capacitive element C in a planar manner.

  The first-layer conductor 13 is formed in a plane size larger than that of the capacitor element C so as to overlap the capacitor element C in a plan view. One layer is formed. Further, the conductor 63 in the sixth layer is formed in a plane size larger than the capacitor element C so as to overlap the capacitor element C in a plane, but the capacitor element C is formed in the conductor 63 in the sixth layer. One layer is formed with respect to. In this way, by forming one electrode layer of the capacitor C with respect to the conductor 13, the parasitic capacitance generated between the first layer conductor 13 and the second layer electrode is reduced. In addition, by forming the electrode of the capacitor C with one layer being separated from the conductor 63, the parasitic capacitance generated between the sixth-layer conductor 63 and the fourth-layer electrode can be reduced. Since the capacitance can be reduced, the parasitic capacitance pc generated between the capacitive element C and the shield body S is suppressed, and the shielding effect by the shield body S is improved (the parasitic capacitance generated between the capacitive element C and the shield body S). Shielding effect can be obtained while holding down small.

  In the first to fourth embodiments described above, in the shield body S, as an example of electrically connecting the conductors between the upper and lower two layers, an example in which a part of the upper conductor is embedded in the connection hole has been described. A conductive plug may be embedded in the hole to electrically connect the conductors between the upper and lower layers. Even when the n-type semiconductor region 4 of the substrate 1 and the first-layer conductor 13 are electrically connected, a conductive plug may be embedded in the connection hole 10c.

  As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

  For example, the present invention can be applied to a semiconductor device having an analog circuit or a digital circuit configured using a capacitor.

  Further, the present invention can be applied to a capacitor element inserted for decoupling between power supply wirings in order to suppress fluctuations in the power supply potential due to switching noise.

1 is a plan layout view of a semiconductor device that is Embodiment 1 of the present invention; FIG. 2 is an equivalent circuit diagram of a filter circuit mounted on the filter circuit unit of FIG. 1. FIG. 8 is a schematic cross-sectional view (a cross-sectional view taken along the line a-a ′ of FIG. 7) illustrating a schematic configuration of the capacitive element and the shield body of FIG. 2. It is typical sectional drawing to which a part of FIG. 3 was expanded. FIG. 8 is a schematic cross-sectional view (cross-sectional view taken along the line b-b ′ in FIG. 7) illustrating a schematic configuration of the capacitive element and the shield body in FIG. 2. FIG. 4 is a schematic plan view showing a planar pattern of a conductor formed on a fourth metal wiring layer in FIG. 3. FIG. 4 is a schematic plan view showing a planar pattern of electrodes and conductors formed in a third metal wiring layer in FIG. 3. FIG. 4 is a schematic plan view showing a planar pattern of electrodes and conductors formed on a second metal wiring layer in FIG. 3. FIG. 4 is a schematic plan view showing a planar pattern of electrodes and conductors formed in the first metal wiring layer of FIG. 3. It is typical sectional drawing which follows the c-c 'line | wire of FIG. It is typical sectional drawing which follows the d-d 'line | wire of FIG. It is a figure which shows the mode of an electric force line when arrange | positioning a shield body between two electrodes. (A)-(e) is a figure which shows each pattern used for the simulation of a shield effect. It is a figure which simulated the simulation result of each pattern of (a)-(e) of FIG. In the semiconductor device which is Example 2 of this invention, it is typical sectional drawing which shows schematic structure of a capacitive element and a shield body. In the semiconductor device which is Example 3 of this invention, it is typical sectional drawing which shows schematic structure of a capacitive element and a shield body. In the semiconductor device which is Example 4 of this invention, it is typical sectional drawing which shows schematic structure of a capacitive element and a shield body.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Field insulating film, 3, 4 ... N-type semiconductor region,
10 ... interlayer insulating film, 10a, 10b, 10c ... connection hole,
M1 ... 1st metal wiring layer, 11a, 11b, 12a, 12b ... Electrode, 13 ... Conductor, 14 ... Signal wiring,
20 ... Interlayer insulating film, 20a, 20b, 20c ... Connection hole,
M2: second metal wiring layer, 21a, 21b, 22a, 22b ... electrode, 23 ... conductor, 24 ... signal wiring,
30 ... interlayer insulating film, 30a, 30b, 30c ... connection hole,
M3: third metal wiring layer, 31a, 31b, 32a, 3b ... electrodes, 32L, 32L ... wiring, 33 ... conductor, 34 ... signal wiring,
40 ... interlayer insulating film, 40a, 40b, 40c ... connection hole,
M4: Fourth metal wiring layer, 41a, 42a ... Electrode, 43 ... Conductor, 44 ... Signal wiring,
50 ... interlayer insulating film, 50c ... connection hole,
M5: fifth-layer metal wiring layer, 51a, 52a ... electrode, 52 ... electrode, 53 ... conductor,
60 ... interlayer insulating film, 60c ... connection hole,
M6: Sixth metal wiring layer, 63: Conductor, 64: Signal wiring,
DESCRIPTION OF SYMBOLS 101 ... Amplifier circuit part, 102 ... Filter circuit part, 103 ... A / D conversion circuit part, 104 ... PLL circuit part, 105 ... Power supply circuit part, 106 ... Logic circuit part, 107 ... External terminal, 108 ... Amplifier,
C: capacitive element, HPF: high-pass filter circuit, S: shield body, pc: parasitic capacitance.

Claims (26)

A capacitive element, a shield body that is fixed at a predetermined potential, and a plurality of wiring layers that are stacked in multiple stages on the semiconductor substrate with an insulating film interposed therebetween,
The capacitive element has a first electrode and a second electrode formed on a first wiring layer of the plurality of wiring layers with the insulating film interposed therebetween,
The shield body includes a first conductor formed so as to surround the capacitive element in a plane in the first wiring layer, and a first layer higher than the first wiring layer of the plurality of wiring layers. And a second conductor that is formed on the two wiring layers so as to surround the capacitor element in a plane and is extended in a plane toward the capacitor element rather than the first conductor. Semiconductor device. The semiconductor device according to claim 1,
The semiconductor device, wherein the second conductor is extended to the capacitor element side so as not to overlap the first and second electrodes in plan view. The semiconductor device according to claim 1,
The insulating film between the second conductor and the first conductor is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the second conductor. Or a conductive plug is embedded,
The semiconductor device, wherein the second conductor and the first conductor are electrically connected to each other through a part of the second conductor or the conductive plug. The semiconductor device according to claim 1,
Of the first electrode and the second electrode, the distance between the first conductor adjacent to the first conductor and the first conductor is the first electrode and the second electrode. A semiconductor device characterized by being larger than the distance between the electrodes. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the shield body includes a semiconductor region formed on the semiconductor substrate so as to overlap with the capacitor element in a planar size larger than the capacitor element. The semiconductor device according to claim 5,
A semiconductor device, wherein a field insulating film is formed on a main surface of the semiconductor substrate so as to cover the semiconductor region. The semiconductor device according to claim 5,
The insulating film between the first conductor and the semiconductor region is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the first conductor or a conductive layer. Sex plug is embedded,
The semiconductor device, wherein the first conductor and the semiconductor region are electrically connected to each other through a part of the first conductor or the conductive plug. The semiconductor device according to claim 1,
The shield body includes a third conductor formed in a third wiring layer below the first wiring layer of the plurality of wiring layers so as to surround the capacitive element;
A fourth wiring layer formed on the fourth wiring layer below the third wiring layer of the plurality of wiring layers and having a larger planar size than the capacitive element so as to overlap the capacitive element in a plane; A semiconductor device comprising: a conductor. The semiconductor device according to claim 8,
A plurality of connection holes formed in the insulating film are provided between the first conductor and the third conductor, and each of the plurality of connection holes includes the first conductor. Or a conductive plug is embedded,
The first conductor and the third conductor are electrically connected to each other via a part of the first conductor or the conductive plug,
A plurality of connection holes formed in the insulating film are provided between the third conductor and the fourth conductor, and each of the plurality of connection holes includes the third conductor. Or a conductive plug is embedded,
The semiconductor device, wherein the third conductor and the fourth conductor are electrically connected to each other through a part of the third conductor or the conductive plug. The semiconductor device according to claim 1,
The first wiring layer is provided in multiple stages with the insulating film interposed therebetween,
The first and second electrodes are formed on each of the plurality of first wiring layers,
The semiconductor device according to claim 1, wherein the first conductor is formed in each of the plurality of first wiring layers. The semiconductor device according to claim 10.
The insulating film between each of the plurality of first conductors is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the first conductor or a conductive layer. Sex plug is embedded,
Each of the plurality of first conductors is electrically connected to each other through a part of the first conductor or the conductive plug. The semiconductor device according to claim 10.
The semiconductor device according to claim 1, wherein the first and second electrodes are formed in the plurality of first wiring layers so as to face each other in a planar direction and a thickness direction. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the capacitor element is used in an analog circuit. The semiconductor device according to claim 1,
The semiconductor device, wherein the capacitive element is connected to an input portion of an amplifier. A capacitive element, a shield body fixed at a predetermined potential, and a multilayer wiring layer provided on the semiconductor substrate;
The multilayer wiring layer has a plurality of wiring layers each laminated in multiple stages with an insulating film interposed therebetween,
The capacitive element has a first electrode and a second electrode formed on the first wiring layer of the plurality of wiring layers so as to face each other with the insulating film interposed therebetween,
The shield body includes a first conductor formed so as to surround the capacitive element in a plane in the first wiring layer, and a first layer higher than the first wiring layer of the plurality of wiring layers. A second conductor formed on the two wiring layers so as to surround the capacitive element in a plane, and the capacitor on the third wiring layer above the second wiring layer of the plurality of wiring layers. And a third conductor formed so as to cover the element. The semiconductor device according to claim 15,
The insulating film between the second conductor and the first conductor is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the second conductor. Or a conductive plug is embedded,
The second conductor and the first conductor are electrically connected to each other via a part of the second conductor or the conductive plug,
The insulating film between the third conductor and the second conductor is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the third conductor. Or a conductive plug is embedded,
The semiconductor device, wherein the third conductor and the second conductor are electrically connected to each other through a part of the third conductor or the conductive plug. The semiconductor device according to claim 15,
The semiconductor device according to claim 1, wherein the shield body includes a semiconductor region formed on the semiconductor substrate so as to overlap with the capacitor element in a planar size larger than the capacitor element. The semiconductor device according to claim 17,
A semiconductor device, wherein a field insulating film is formed on a main surface of the semiconductor substrate so as to cover the semiconductor region. The semiconductor device according to claim 17,
The insulating film between the first conductor and the semiconductor region is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the first conductor or a conductive layer. Sex plug is embedded,
The semiconductor device, wherein the first conductor and the semiconductor region are electrically connected to each other through a part of the first conductor or the conductive plug. The semiconductor device according to claim 15,
The shield body includes a fourth conductor formed in a fourth wiring layer lower than the first wiring layer of the plurality of wiring layers so as to surround the capacitive element;
The fifth wiring layer formed below the fourth wiring layer of the plurality of wiring layers and having a larger planar size than the capacitive element so as to overlap the capacitive element in a planar manner. A semiconductor device comprising: a conductor. The semiconductor device according to claim 20, wherein
The insulating film between the first conductor and the fourth conductor is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the first conductor. Or a conductive plug is embedded,
The first conductor and the fourth conductor are electrically connected to each other through a part of the first conductor or the conductive plug,
The insulating film between the fourth conductor and the fifth conductor is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the fourth conductor. Or a conductive plug is embedded,
The semiconductor device, wherein the fourth conductor and the fifth conductor are electrically connected to each other through a part of the fourth conductor or the conductive plug. The semiconductor device according to claim 15,
Each of the first wiring layers is provided in multiple stages with the insulating film interposed therebetween,
The first and second electrodes are formed on each of the plurality of first wiring layers,
The semiconductor device according to claim 1, wherein the first conductor is formed in each of the plurality of first wiring layers. 23. The semiconductor device according to claim 22,
The insulating film between each of the plurality of first conductors is provided with a plurality of connection holes, and each of the plurality of connection holes includes a part of the first conductor or a conductive layer. Sex plug is embedded,
Each of the plurality of first conductors is electrically connected to each other through a part of the first conductor or the conductive plug. 23. The semiconductor device according to claim 22,
The semiconductor device according to claim 1, wherein the first and second electrodes are formed in the plurality of first wiring layers so as to face each other in a planar direction and a thickness direction. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the capacitor element is used in an analog circuit. The semiconductor device according to claim 15,
The semiconductor device, wherein the capacitive element is connected to an input portion of an amplifier.

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