JP2000048132A - IC card test method and device - Google Patents

Abstract

(57) [Problem] An IC card capable of realizing a parallel individual test corresponding to the test speed of each IC card without increasing the cost of a tester, thereby increasing the test speed at a low cost. Provide testing technology. SOLUTION: An EE of a non-contact type or a contact type IC card is provided.
In the test for writing data to the PROM, immediately after receiving the write completion statuses a1 to a3 for the write command A from each IC card, the next write command B is transmitted independently to each IC card, and the process proceeds. At this time, since there is a variation in response among devices due to a difference in process, a 3ch IC card, a 1ch I
Since the write completion statuses a3, a1 and a2 from the C card and the 2ch IC card are sequentially received, the 3ch IC card, the 1ch IC card and the 2c
The next write command B is transmitted in the order of the IC card of h.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card test technique, and more particularly to an effective technique applied to an IC card test method and apparatus capable of constructing a high-speed distributed architecture at low cost.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, an IC card is a card having the same shape as a card with a magnetic stripe, such as a credit card and a bank cash card, which are now widely used in society. inside,
A portable information storage medium that incorporates a CPU and a memory and utilizes the latest technology suitable for the advanced information society is expected to develop in the future. This IC card is C
Under the control of a PU control program, information can be exchanged with an external device through a contact-type contact terminal or a non-contact-type antenna coil. In addition, the built-in memory is controlled so as to be accessed only when processing is performed in a certain procedure for security.

Since such an IC card has various and various functions, a test before shipment is important. For example, regarding the test method of IC card,
JP-A-5-108905, JP-A-3-90983
And the like. The technique disclosed in Japanese Patent Application Laid-Open No. Hei 5-108905 relates to a test method for testing a plurality of IC cards simultaneously.
A write test to M is performed at the same time. Also,
The technique disclosed in JP-A-3-90983 relates to a test apparatus for providing a plurality of test units and simultaneously testing different types of IC cards, and constitutes a plurality of test groups which can be independently tested by a plurality of test boards. Things.

[0004]

The inventors of the present invention have studied the test method for an IC card as described above, and have found the following.

(1) According to the technique disclosed in Japanese Patent Laid-Open No. 5-108905, a write command A is transmitted from a tester to each IC card as shown in FIG. Each of the IC cards responds to the write command A by writing completion statuses a1 to a3.
Reply to each. Then, the next write command B
Are simultaneously transmitted to each IC card to perform a write operation to the EEPROM. In this case, because of the writing by the internal clock signal of the IC card, the response of the status varies among the devices, and it is considered necessary that the tester always waits for the status of the slow response and then transmits the next command. This leads to an increase in test time. Note that X shown in FIG. 8 is a response request command when the test fails.

(2) In the technique disclosed in Japanese Patent Laid-Open No. 3-90983, hardware such as a pattern generator is mounted on a test board of each test group in order to form a plurality of test groups that can be tested independently. It is considered necessary to mount it. For this reason, these hardware-based pattern generators and the like are expensive, and providing a hardware-based pattern generator and the like for each test group increases the cost of the tester.

Therefore, an object of the present invention is to focus on the test time of a tester and the cost of hardware, and realize a parallel individual test corresponding to the test speed of each IC card without increasing the cost of the tester. The present invention also provides an IC card test method and apparatus capable of inexpensively increasing the speed of a test.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the IC card test method according to the present invention is applied to an IC card test method in which electrical characteristic tests of a plurality of IC cards are performed in parallel. Test information such as a command is transmitted independently to the IC card, and immediately after receiving response information to the test information, the next test information is transmitted independently to each IC card and the process proceeds.

Particularly, in parallel writing to an internal memory such as an EEPROM, test information includes data to be commonly written such as test data, a serial number, and a user ID.
There is an asynchronous test method for testing different types in parallel, and information such as the number of test retries is written to the IC card during the test.

Further, the IC card test apparatus according to the present invention transmits test information to each IC card independently, and immediately after receiving response information to the test information, independently performs the next test for each IC card. It has a plurality of transmitting / receiving means for transmitting information and a plurality of measuring means for independently measuring the electrical characteristics of each IC card based on response information from each IC card. In particular, the test information is generated by being processed by an algorithm by software.

According to the method and apparatus for testing an IC card, the next test information is transmitted immediately after the response information to the test information is received, and the process proceeds.
Since the test can be performed individually corresponding to the test speed of each IC card, the speed of the test can be increased.

In particular, since individual write data such as a user ID can be written, it can be used as an IC card issuing device. Further, since different types of products can be tested in parallel, it is possible to cope with a wide variety of IC cards.

Further, by writing the number of test retries, the number of erasures / rewrites of the internal memory of the IC card can be managed and recognized before erasure / rewrite becomes impossible. Further, since the test information can be generated by software, the cost of the tester can be reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

FIG. 1 is an explanatory view showing a schematic structure of an IC card according to an embodiment of the present invention, and FIG.
FIG. 3 is a configuration diagram showing an IC card tester, FIG. 4 is a configuration diagram showing software of the IC card tester, and FIG. 5 is an explanatory diagram showing a parallel connection configuration of the IC card tester and the IC card. FIG. 6 is a timing chart showing a parallel test of IC cards, and FIG. 7 is an explanatory view showing a memory area configuration in an internal memory.

First, an example of a schematic structure of the IC card according to the present embodiment will be described with reference to FIG. FIG. 1A is a non-contact type IC card capable of exchanging information without contacting an external device, and FIG. 1B is a contact type I card capable of exchanging information by contacting an external device.
C cards are shown. In the non-contact type IC card, an LSI chip 2 and an antenna coil 3 electrically connected to the LSI chip 2 are incorporated in a plastic card 1. On the other hand, in a contact type IC card, an LSI chip 2 and a contact terminal 4 electrically connected to the LSI chip 2 are incorporated in a plastic card 1. The shape of this IC card is, for example, about 54 mm in length, about 85 mm in width, and about 0.25 to 0.8 mm in thickness.

An example of the internal configuration of this IC card is, as shown in FIG. 2, for example, a CPU 11 for controlling the entire control inside a chip 2, and a read-only memory for storing programs and data. A ROM 12, a writable / readable RAM 13, and an electrically erasable / rewritable EEPROM 14, an arithmetic unit 15 for performing arithmetic processing, and an interface 16 for controlling input / output with the outside are provided. Data transfer is possible. The data transfer between the chip 2 and the external device is performed by radio waves from the antenna coil 3 through the interface 16 inside the chip 2 and, in the case of the non-contact type, through the modulation / demodulation circuit 17 under the control of a control program by the CPU 11. On the other hand, in the case of the contact type, the contact is performed by the contact of the contact terminal 4. ROM12, R
Internal memories such as the AM 13 and the EEPROM 14 are controlled so as to be accessed only when processing is performed according to a certain procedure in order to protect data.

The test contents of the IC card include a DC test and various margin tests, and an IC card function operation test (AC function test). The DC test and various margin tests include a margin test for power supply voltage fluctuation, a margin test for timing fluctuation, an input signal voltage level margin test, an output voltage level test, open / short of each terminal, power supply current and leak current measurement, and the like. As the IC card function operation test, the CPU in the card
There are an operation test, a RAM and ROM data rewriting / reading function test, an EEPROM data writing / reading function test, and an IC card floating arithmetic unit function test.

Next, an example of the configuration of the IC card tester will be described with reference to FIGS. FIG. 3 shows the configuration of the IC card tester, and FIG. 4 shows the software configuration. This IC card tester shows a configuration example applied to a contact type IC card. However, a non-contact type IC card is almost the same except that the input / output configuration with the IC card tester is different.

The IC card tester has functions of a tester, a reader / writer, a card issuing device, etc., and as shown in FIG. 3, a host CPU unit 20 for developing a test condition program and managing test data, and a test execution unit. And a tester main unit 30 for executing control and test plan / debugging, and are connected by a LAN. Host CP
The U unit 20 is connected with a printer 21 for print output, an MO drive 22 for auxiliary storage, and the like, so that a user can create a test plan and manage measurement results. The tester main unit 30 is connected to each corresponding IC card 33 via a common contact probe unit 32 from each measurement control unit 31 which can operate independently corresponding to the device under test. Can be increased or decreased (for example, up to about 32 sheets), so that a test system can be constructed according to the performance before and after the testing process.

The tester main body 30 includes a satellite CPU 3
4, a handler i / f 35, a system power supply 36, a safety circuit 37, and a plurality of measurement control units 31. Each measurement control unit 31 is provided with a controller 38, a device power supply 39, an AC measurement unit 40, a DC measurement unit 41, an MPX 42, a test head 43, and the like. Tests are possible. Hereinafter, each component will be described in detail.

The satellite CPU 34 transfers test conditions, reads test results, and controls handlers to a plurality of measurement control units 31. Also, test plan debugging can be executed from the satellite CPU 34.

The handler i / f 35 is a unit for controlling a handler of the IC card 33 or a soft COB handler. Perform parallel communication.

The controller 38 sends a device power supply 39 to the tester hardware in accordance with the user-written test conditions.
Voltage setting, condition setting of AC measuring unit 40, DC measuring unit 4
Perform the condition setting of 1 and pin assignment of various conditions.
The test of the IC card 33 is executed. It also manages the measurement results.

The device power supply 39 sets the voltage level applied to the power supply terminal of the IC card 33 and
It has a function of measuring a power supply current flowing through the card 33.

The AC measuring section 40 sets the clock frequency and duty ratio to be applied to the IC card 33, sets the output voltage level of the driver, sets the comparator level, and the like. Perform the test.

The DC measuring unit 41 is a unit that performs open / short check of input / output pins of the IC card 33 and measures leak current.

The MPX 42 has a function of allocating the AC measuring section 40 and the DC measuring section 41 to predetermined pins of the IC card 33 by relay switching.

The test head 43 has a signal driver applied to the IC card 33, an output signal judgment comparator, and the like. In addition, a virtual ground that minimizes measurement errors due to cable loss is supplied to improve measurement accuracy.

In this IC card tester, the host C
As shown in FIG. 4, the software of the PU unit 20 includes a test plan editor 51, a test plan compiler 52,
It is composed of data communication software 53, data output display software 54, system operation management software 55, and the like. The software of the satellite CPU 34 includes a measurement control system 61, an online debugger 62, test condition and data communication software 63, a histogram utility 64, a calibration software 65, and the like. Host CPU unit 20 and satellite CPU 3
The four are connected by a network (LAN). Hereinafter, each software will be described in detail.

The test plan editor 51 is an editor for creating test conditions, and can directly activate the test plan compiler 52 from the test plan editor 51. If a condition description error or the like occurs in the compilation result, the cursor is moved to a predetermined error occurrence location and the description error location is indicated. As a result, a test plan can be efficiently created.

The test plan compiler 52 translates the test plan created by the test plan editor 51 into an object that can be executed by the tester. The test plan compiler 52 also generates detailed information for test plan debugging.

The software of the data communication software 53 is
Transfers (assigns) test plans, reads measurement results, and sets and issues various other functions.

The software of the data output display software 54 converts a test result read by data communication into a CRT,
Output to printer, HD, etc. In addition, it is possible to output a test result report (lot number, worker name, test start time, end time, total number of tests, number of good / defective products, number of defects by test number, etc.).

The software of the system operation management software 55 performs security management of the apparatus by using a password or the like.

The measurement control system 61 controls the handler and controls the controller 38 (test execution unit).
Controls test plan execution. With this software, the measurement results of the plurality of measurement control units 31 are managed and transmitted to the host CPU unit 20 as needed. The test status is output to the liquid crystal display panel of the tester main unit 30, and the number of tests, the number of good / defective products, and the like up to the present can be viewed.

The online debugger 62 is a test plan debugging tool. Functions include execution of a test plan line by line, test stop (pause) at a source line number or a test number of a predetermined test plan, change of test conditions, DC test, execution from an AC test keyboard, measurement result Display and the like can be performed. Thus, the test plan can be efficiently debugged. It can also be used as a failure analysis tool.

The software of the data communication software 63 is
The test plan (test conditions) received from the host CPU unit 20 is transmitted to the controller 38. Also, the measurement results received from each controller 38 are put together and the host CPU
Or to the unit 20.

The histogram utility 64 obtains the distribution of measured data for each DC test for a predetermined production lot of the IC card 33. By using this, the user can use this data as an index for process control.

The software of the calibration software 65 is used when calibrating the hardware of the system. This IC card tester
Since the measurement control unit 31 is compatible with maintenance by replacing the unit, this calibration is performed when the unit is replaced.

The test process of the IC card 33 is performed using the IC card tester configured as described above. This test process is included in the IC card manufacturing process 0th issue process, the IC card inspection process, the 1st issue process, the 2nd issue process, and the like. Tests are performed.

The IC card manufacturing process 0th issuance step is a step of checking hardware components. The IC card 33 checks the normal operation of the IC card 33,
Processing such as initialization of the card 33, creation of an MF, writing of a card identifier (manufacturer, version information, etc.), writing of a card ID, writing of a cryptographic function, and a loop test are performed.

In the IC card inspection step, reading of the card ID is repeatedly performed as a screening test on the IC card 33 on which the manufacturing process has been completed. The card ID written by writing the card ID of the IC card manufacturing processing function is used for the test.

The primary issuance processing step is a step of performing an operational check.
Write basic information, confirm basic information,
Processing such as F, EF, key creation, data writing, data confirmation, and security setting is performed.

The secondary issuance processing step is a step of writing individual information such as a user ID. This allows
After the DC test, various margin tests, and functional operation tests of the IC card 33 are completed, the IC card 33 in which individual information and the like are written is completed, and can be issued to the user.

Next, according to an example of the parallel connection configuration of the IC card tester and the IC card 33 in FIG. 5 and an example of the timing of the IC card parallel test in FIG. A data write (read) test will be described. This writing test is performed in the parallel connection configuration of the IC card tester and the IC card 33 shown in FIG. 3. Here, as shown in FIG. 5, a test example by the parallel connection of the IC cards 33 of 1ch to 3ch is shown. .

(1) The IC card tester transmits a write command A from each measurement control unit 31 to each of the corresponding IC cards 33 of 1ch to 3ch (t1). At this time, the first write command A is
It is transmitted to the C card 33 at the same timing.

(2). Each IC card 33 for 1ch to 3ch
Receives the write command A, performs a data write operation to the EEPROM 14 based on the write command A, and returns a write completion status a. For example, in order, the 3ch IC card 33 returns the write completion status a3 (t2), the 1ch IC card 33 returns the write completion status a1 (t3), and the 2ch IC card 33 returns the write completion status a2 (t4).

(3) Immediately after receiving the write completion status a, the IC card tester
Then, the next write command B is transmitted to each of the corresponding IC cards 33 of 1ch to 3ch. At this time, the write completion status a3 from the 3ch IC card 33, the write completion status a1 from the 1ch IC card 33, and the write completion status a2 from the 2ch IC card 33 are sequentially received.
IC card 33 (t5), 1ch IC card 33
(T6) The next write command B is transmitted in the order of the 2ch IC card 33 (t7).

(4). Each IC card 33 for 1ch to 3ch
Receives the next write command B, performs an operation of writing data to the EEPROM 14 based on the write command B, and returns a write completion status b. At this time, according to the order in which the write command B is received, the 3ch IC card 33 and the 1ch IC card 3
The write completion status b3 (t8), the write completion status b1 (t9), and the write completion status b2 (t1)
0) is returned.

(5). Similarly, each measurement control unit 3
The transmission of the write command to each of the corresponding 1ch to 3ch IC cards 33 from 1 and the return of the write completion status from each of the 1ch to 3ch IC cards 33 are repeatedly executed.

As described above, the test for writing data to the EEPROM 14 in each IC card 33 can be performed in parallel and independently in each measurement control unit 31. This is effective when the timing difference of the internal clock signal occurs between the devices due to the difference in the process and the response varies. Similarly, in the data read test from the EEPROM 14, the next read command can be transmitted immediately after receiving the read completion status for the read command, and the read test can be performed independently.

In this parallel test, the IC card 33 has means for changing the level of the input / output pin and informing the IC card tester of the end of the data writing / reading, and monitors the level change of the input / output pin with the IC card tester. This can be realized by employing a method of controlling the test processing sequence by using the method and synchronizing the devices by software by a result request command from the IC card tester.

For example, in the IC card 33, the level of the input / output line is changed from the intermediate level to the high level at the same time when the data writing is completed. The IC card tester monitors the input / output lines and senses the flag from the intermediate level to the high level. Then, when a predetermined time including a margin for the response has elapsed, or when responses have been returned from all devices, the processing shifts to the determination processing.

Further, a test result request command is transmitted from the IC card tester to the IC card 33. The IC card 33 transmits the test result to the IC card tester in synchronization with the clock signal. Then, the transmitted result data is subjected to simultaneous determination processing by the IC card tester. As a result, a large number of parallel tests can be realized simultaneously.

Next, a test for writing data to the internal memory will be described with reference to an example of a memory area configuration in the internal memory such as the EEPROM 14 shown in FIG.

As shown in FIG. 7, in addition to the IC card hardware, the IC card 33 stores an OS (operating system), applications 1, 2 and user data 1, 2 in a memory area of an internal memory such as the EEPROM 14. Software is stored. The OS and the applications 1 and 2 become the common write data 71, and the user data 1 and 2 become the individual write data 72. As described above, in the internal memory of the IC card 33, there are data to be written in parallel, such as test data and OS, and data to be written individually, such as a serial number and a user ID.

(1) Common write data 71 The common write data 71 has an area for storing common data such as test data and OS. The number of bytes specified from the beginning of the storage data specified by the test plan can be read from the IC card tester. The data is continuously transmitted to the IC card 33. Then, the IC card tester receives the result of the transmitted data sequence,
The pass / fail judgment is performed by comparing with the expected value pattern. At this time, if it is determined that the pattern matches the expected value pattern or is defective, the retry is performed a predetermined allowable number of times.

(2). Individual write data 72 Before starting the test, an IC card tester (host CPU unit 20)
Etc.), an area for receiving individual write data such as a serial number and a user ID corresponding to the target IC card 33 is provided, and this data is written to and read from the IC card 33 according to a test plan. Then, the IC card tester compares the result received from the IC card 33 with the expected value, and performs good / bad determination. At this time, if it is determined that the value matches the expected value or is defective, the retry is performed a predetermined allowable number of times.

As described above, after performing the write test / read test of the internal memory, the common write data 71
In addition, by writing individual write data 72 such as a serial number in a manufacturer shipping test and a user ID in a user acceptance test, an individual IC
A card 33 can be issued.

Further, since each corresponding IC card 33 can be independently tested by each measurement control unit 31 using an IC card tester, for example, a bank card for a bank, an electronic wallet card and a cash card,
Different types of IC cards 33, such as a public health insurance card, a driver's license card, and a medical card, can be tested asynchronously in parallel.

Further, by writing and issuing the number of retries in the data write test / read test to the IC card 33, the user can manage the number of erasures / rewrites of the internal memory.
It becomes possible to recognize beforehand before rewriting becomes impossible. Information such as a test head number of an IC card tester and a production line number can be written into the IC card 33 at the time of testing, and can be used for verification when a problem or the like occurs.

Therefore, according to the test technique for the IC card 33 of the present embodiment, the controller 38 is provided inside, and the IC card tester has the respective measurement control units 31 capable of performing independent and parallel tests. The following operational effects can be obtained by conducting a test using

(1) EEPRO inside each IC card 33
In the data write test / read test to M14, immediately after the write / read completion status for the write / read command is received, the next write / read
By transmitting the read command, the write test and the read test can be performed independently according to the test speed of each IC card 33, so that the test can be performed at high speed.

(2) Since individual write data 72 such as a serial number and a user ID can be written in addition to the common write data 71, the IC card tester can be used as an IC card issuing device.

(3) Since various types of IC cards 33 such as various cards for banks and various cards for public can be tested in parallel and asynchronously, it is possible to cope with various types and diversification of IC cards 33. be able to.

(4) By writing and issuing the number of retries in the data write test / read test to the IC card 33, the user can manage the number of erasures / rewrites. Can be recognized.

(5) Since the test information can be generated by the software of the IC card tester, the cost of the IC card tester can be reduced as compared with the case where a pattern generator or the like is provided by hardware.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible. For example, the EEPROM inside the IC card is
However, the present invention is not limited to this, and can be applied to other erasable / rewritable memories such as a flash EEPROM.

[0072]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) In the parallel (synchronous) test, the next test information is transmitted independently to each IC card immediately after the response information to the test information from each IC card is received, and the process proceeds. Since the test can be performed individually in accordance with the test speed of each IC card, it is possible to speed up the test.

(2) In parallel writing to an internal memory such as an EEPROM, since there is data to be written in common to test information and data to be individually written, user I
Since individual write data such as D can be written, it can be used as an IC card issuing device.

(3) By using an asynchronous test method for testing in parallel, different types can be tested in parallel, so that it is possible to cope with a wide variety of IC cards.

(4) By writing information such as the number of test retries to the IC card during the test, the user can manage the number of erasures / rewrites in the internal memory of the IC card. It becomes possible to recognize beforehand.

(5) Since the test information is processed and generated by an algorithm by software, there is no need to provide a pattern generator or the like by hardware.
The cost of the tester can be reduced.

(6) According to the above (1) to (5), parallel individual tests corresponding to the test speed of each IC card can be performed without increasing the cost of the tester. It is possible to realize a high-speed test.

[Brief description of the drawings]

FIGS. 1A and 1B are explanatory views showing a schematic structure of an IC card according to an embodiment of the present invention.

FIG. 2 is an internal configuration diagram showing an IC card according to an embodiment of the present invention.

FIG. 3 is a configuration diagram showing an IC card tester in one embodiment of the present invention.

FIG. 4 is a configuration diagram showing software of an IC card tester in one embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a parallel connection configuration of an IC card tester and an IC card in one embodiment of the present invention.

FIG. 6 is a timing chart showing a parallel test of an IC card in one embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a memory area configuration in an internal memory according to an embodiment of the present invention.

FIG. 8 is a timing chart showing a parallel test of an IC card as a premise of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Plastic card 2 LSI chip 3 Antenna coil 4 Contact terminal 11 CPU 12 ROM 13 RAM 14 EEPROM 15 Operation unit 16 Interface 17 Modulation / demodulation circuit 20 Host CPU unit 21 Printer 22 MO drive 30 Tester main unit 31, Measurement control unit 32 Contact Probe unit 33 IC card 34 Satellite CPU 35 Handler i / f 36 System power supply 37 Safety circuit 38 Controller 39 Device power supply 40 AC measurement unit 41 DC measurement unit 42 MPX 43 Test head 51 Test plan editor 52 Test plan compiler 53 Data communication Software 54 Data output display software 55 System operation management software 61 Measurement control system 62 Online debugger 63 Data communication software 64 Histogram utility 65 calibration software 71 common write data 72 individual writing data

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hideaki Mayuzumi 3-3-2 Fujihashi, Ome-shi, Tokyo F-term in Hitachi Tokyo Electronics Co., Ltd. 5B048 AA00 CC00 CC07 DD00 FF00 5B058 CA23 KA28

Claims (9)

[Claims] 1. An IC card test method for performing electrical characteristic tests of a plurality of IC cards in parallel, comprising: transmitting test information independently to each IC card; The respective IC cards independently returning response information; and the respective IC cards immediately after receiving the response information.
Independently transmitting the next test information to the card;
The respective IC cards independently returning the next response information to the next test information, and thereafter repeatedly transmitting the test information and returning the response information. Card testing method. 2. The IC card test method according to claim 1, wherein the test information includes data to be written in an internal memory of each of the IC cards and data to be individually written. IC card testing method. 3. The IC card test method according to claim 2, wherein the data to be written in common includes test data. 4. The IC card test method according to claim 2, wherein the data to be individually written is a serial number,
An IC card test method including a user ID. 5. The method for testing an IC card according to claim 2, wherein the internal memory of each of the IC cards includes an EEPROM.
A method for testing an IC card, comprising M. 6. The method for testing an IC card according to claim 1, wherein the plurality of IC cards are of different types. 7. The IC card test method according to claim 1, wherein the IC card has a test retry count written therein. 8. An IC card test apparatus for performing electrical characteristic tests of a plurality of IC cards in parallel, wherein test information is transmitted independently to each IC card, and response information to the test information is received. A plurality of transmission / reception means for immediately and independently transmitting the next test information to each of the IC cards, and independently measuring the electrical characteristics of each of the IC cards based on response information from each of the IC cards. For testing an IC card, comprising: a plurality of measuring means for measuring the size of the IC card. 9. An IC card test apparatus according to claim 8, wherein said test information is generated by processing with an algorithm by software.
Card testing equipment.