JP2000048064A - Lsi delay analytic system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute analysis in a short time by simulating a verification circuit before delay analysis and storing the state values of respective logic cells in a database. SOLUTION: A test pattern 1 is inputted to a circuit model 2 to analyze delay and a simulation 3 is performed. A flip-flop(F/F) to be operated at the clock edge of a clock pattern, the logic cell name of a combination circuit to change a signal value, high impedance after the change and unspecified logic value are outputted for each clock pattern and stored in a simulation database. The input of the circuit model at the start point of observation or output terminal name of the F/F and the input terminal of the F/F at the end point of observation and the output terminal name of the circuit model are inputted 5. All signal lines and logic cells related to the start and end points of observation are extracted from signal lines in the circuit model 2 by signal route retrieval 6, the pattern value of the test pattern used at the time of simulation 3 is inputted 7 to these data, and the logic cell and signal line to be operated in this pattern are extracted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a delay analysis method, and more particularly to a delay analysis method in LSI (Large Scale Integrated Circuit) design.

[0002]

2. Description of the Related Art In an LSI, particularly a digital circuit LSI, a delay time of each signal becomes a problem when designing a circuit.
Delay occurs in a plurality of signals, and if there is a delay time difference between the signals, noise called a glitch occurs in an output signal.
This glitch causes a malfunction of the digital circuit.

Performing a delay analysis at the time of designing such an LSI is essential for obtaining a highly reliable LSI. Conventionally, a method or an apparatus for this purpose is disclosed in, for example, JP-A-6-19.
5407, "Signal propagation path analyzer"
No. 249058, "Integrated Circuit Design Apparatus" and JP-A-4-128661, "Line Delay Test Apparatus"
Etc.

[0004]

However, in the above-mentioned conventional LSI delay analysis technique, since a logic (logic) is not taken into account, a signal path search is performed by obtaining it. It takes a long time.

In LSI design, between an input and a flip-flop (hereinafter referred to as F / F), between F / F and F / F,
The delay analysis of the gate and wiring between / F and the output executes a simulation. That is, a delay analysis tool that displays the interval between the observation start point and the end point on a waveform viewer (display) and visually observes it, or inputs the names of the delay observation start point and end point and displays the path and delay on a text screen ( Static delay analysis tool).

In the method of delay analysis by simulation, a circuit is simulated by a test pattern, and a delay value is obtained by observing a waveform time difference between a start point and an end point by a waveform display function of the simulator. In the display method, the total value of the logic cell and the wiring delay between the designated observation points is displayed, and the observation is performed visually.

In the analysis by the delay analysis tool, a route and a wiring delay value for each logical cell are calculated by designating a start point and an end point. Regarding the display method, all the delay values of all designated paths are displayed in text regardless of the logic.

At present, the use of logic synthesis tools is increasing with the spread of HDL design. However, the circuit after logic synthesis, which is an input for performing delay analysis, is optimized for combinational circuits. In this case, it is difficult to grasp which path the output result logically takes through the path, and the designer needs to analyze the path together with the delay based on the circuit diagram.

The "signal propagation path analyzer" disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 6-195407 analyzes a signal path by simulation and stores it in a database. However, this prior art aims to improve the analysis efficiency of simulation-in. For that purpose, the change point of the signal is stored in the database during the simulation, and the path between the input and output of each logic element is specified at the time of analysis,
This is a technique of sequentially searching for the propagation path on the upstream side along the signal flow. According to this, it is necessary to dump all the change point information into the database during the simulation.
Therefore, there is a disadvantage that the capacity of the database becomes enormous, and that much time is required to extract information from the database.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an LSI delay analysis method capable of performing analysis in a short time and efficiently.

[0011]

In order to solve the above-mentioned problems, an LSI delay analysis system according to the present invention has the following characteristic configuration.

(1) In an LSI delay analysis method for performing a delay analysis of an LSI verification circuit having a plurality of designed logic cells, a simulation of the verification circuit is performed before performing the delay analysis, and a state of each of the ethical cells is determined. An LSI delay analysis method in which values are stored in a database and the database is used at the time of the delay analysis.

(2) The LSI delay analysis method according to the above (1), wherein the database stores observation route data at the time of the simulation.

(3) The LSI delay analysis method according to the above (1) or (2), wherein the delay analysis includes inputting an observation start point and an end point of the verification circuit.

(4) The LSI delay analysis method according to (3), wherein the delay analysis includes a signal path search step.

(5) A logic simulation by inputting verification circuit data and a test pattern, a delay analysis for inputting an observation start point and an end point and analyzing a delay, and a database for storing the simulation result. LSI delay analysis method using data stored in the database as a signal path of the LSI.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an LSI analysis device according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a processing flowchart of a preferred embodiment of the LSI delay analysis system of the present invention. FIG. 2 is an example of a circuit model analyzed by the present invention. FIG.
FIG. 4 is an output waveform diagram when a simulation is performed on the circuit model of FIG. 2 by the present invention.

First, a flow chart of the LSI delay analysis method of the present invention will be described with reference to FIG. A test pattern 1 and a circuit model 2 created by logic synthesis or the like are input to a simulation 3. After determining that the circuit model 2 logically operates the same as the specification, a delay analysis tool is used to determine whether the circuit model 2 operates with a delay that satisfies the specification. The delay analysis taking into account the wiring between the input terminal of the circuit model 2 and the input terminal of the F / F, the output terminal of the F / F and the output terminal of the circuit model, and the delay of the logic cell is performed as follows.

A test pattern 1 is input to a circuit model 2 for performing delay analysis, and a simulation 3 is performed. For each clock pattern (between the rising and falling edges of the active clock), the change in the F / F operating at that clock edge and the F / F connected to that F / F Output the logic cell name of the combinational circuit whose signal value has changed and the logical values of 0, 1, Z (high impedance), and X (indefinite) after the change, and store the information in the simulation database.

Thereafter, in order to search for a signal path of the circuit model 2 for which delay analysis is performed, first, input of a circuit model as an observation start point or input of an F / F output terminal name and an F / F as an observation end point is performed. Input 5 the terminal or the output terminal name of the circuit model. First, by this observation start point / end point input 5,
The signal path search 6 extracts all signal lines and logic cells related to the observation start and end points from the signal lines in the circuit model 2. The pattern value of the test pattern 1 used in the simulation 3 is input 7 to the extracted data.

Thus, the logic cells and signal lines actually operating in this pattern are extracted by the signal path search 8. The signal route search 8 based on the input of the pattern value of the test pattern refers to the simulation database 4 created in the simulation 3 and uses the pattern value of the test pattern in the signal line and the signal route search 6 searched in the observation start / end point input 5. Only operating signal lines and logic cells can be extracted.

After extraction 8 of the signal path to be subjected to delay analysis, wiring delay information 9 for the signal line of the signal path and delay information addition 1 of the logic cell extracted from the delay library 10
1 and store it in the delay information file.

The signal path search 8 based on the observation start point / end point input 5 and the pattern value input 7 of the test pattern 1 enables the delay analysis of the signal path in consideration of the logic in performing the delay analysis.

Next, the present invention will be described in more detail with reference to FIGS. FIG. 3 shows an output waveform diagram when a simulation of the circuit model of FIG. 2 is performed. The circuit model of FIG. 2 has two F / Fs 21 and 22 and six logic cells a.
Including f. The outputs of logic cells c, e and f are connected to output A, output B and output C, respectively. In addition, FIG.
This is a circuit after logic synthesis, and it is assumed that the designer does not know what circuit configuration the combinational circuit portion has.

FIGS. 3A and 3B are simulation output waveform diagrams of the circuit model of FIG. 2, wherein FIG. 3A shows a clock, and FIG.
/ F21, output of F / F22, (d) output A, (e) output B, and (f) output C. Here, it is assumed that the active edge is a rising edge.

When the simulation 3 of FIG. 2 was performed,
The F / F and the logic cell name whose output has changed at each rising edge and the signal value after the change at that time are stored in the simulation database 4.

When a simulation is performed using the circuit model of FIG. 2, the F / F and the logic cell name of which the output terminal is changed with the number of patterns α in FIG. 3 are F / F21, and the logic cells a, c, and d. , E, the F / F and the logic cell name are stored in the database 4 for each clock pattern of the signal value after the change. In this case, the F / F 21,
The names of a, c, d, and e and the changed signal value are stored.
Similarly, α-2, α-1, α + 1, α + 2,.
F / F whose signal value has changed even when the clock pattern is
The logic cell name and the signal value are stored in the database 4.

In the route search method for performing the delay analysis between the F / F 21 and the output terminal B, the name of the output terminal of the F / F 21 is input to the observation start point, and the terminal name of the output B is input to the observation end point.
In this case, the signal path search outputs all the logical cell names connected between the observation start point and the end point. In the case of the circuit model of FIG. 2, three paths of F / F21-a-be output B F / F21-ad-e output B F / F21-fe-e output B are searched.

In order to narrow the path of F / F 21-output B, the simulation database 4
Refer to the data stored in.

According to the waveform diagram after execution of the simulation in FIG. 3, the signal output from the output terminal of the F / F 21 is output to the output B as the number of patterns α. The corresponding path is output in correspondence with the logical cell name stored in α on the simulation database. The logical cell name with the number of patterns α stored in the simulation database 4 is F / F
Since the path is 21-a-de, the path finally searched is a F / F 21-a-de-output B.

For the logic cell of the signal path after the search for the signal path, the delay information extracted from the delay library 10 is added, and for the wiring, the wiring delay information after the layout wiring is added. The delay analysis of the desired signal path can be performed more easily than before.

Although the preferred embodiment of the LSI delay analysis system of the present invention has been described above, the present invention should not be limited to only such a specific example, and various modifications and changes can be made in accordance with a specific application. Can understand.

[0034]

As can be understood from the above description, according to the LSI delay analysis method of the present invention, since the simulation and the delay analysis are conventionally performed separately, the logic is not considered when performing the delay analysis. , The signal route was searched manually. However, according to the LSI delay analysis method of the present invention, by performing delay analysis using the result of logic verification by simulation, it is easy to search for a signal path, and it is possible to perform delay analysis extremely efficiently. It is possible.

[Brief description of the drawings]

FIG. 1 is a processing flowchart for implementing an LSI delay analysis method according to the present invention.

FIG. 2 is a diagram showing an example of a circuit model for explaining the operation of the LSI delay analysis method of the present invention.

FIG. 3 is an output waveform diagram when a simulation is performed on the circuit model of FIG. 2;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test pattern 2 Verification circuit (circuit model) 3 Simulation 4 Simulation database 5 Input of observation start point / end point 6, 8 Signal route search 9 Wiring delay information 10 Delay library 11 Add delay information 12 Delay information

Claims (5)

[Claims] An LSI having a plurality of designed logic cells
In the LSI delay analysis method for performing a delay analysis of a verification circuit, a simulation of the verification circuit is performed before the delay analysis is performed, and a state value of each ethical cell is stored in a database, and the database is used at the time of the delay analysis. An LSI delay analysis method, characterized in that: 2. The LSI delay analysis method according to claim 1, wherein the database stores observation route data at the time of the simulation. 3. The LSI delay analysis method according to claim 1, wherein said delay analysis includes an observation start point and end point input step of said verification circuit. 4. The LSI delay analysis method according to claim 3, wherein said delay analysis includes a signal path search step. 5. A logic simulation comprising inputting verification circuit data and a test pattern, a delay analysis for inputting observation start points and end points and analyzing delays, and a database for storing the simulation results. An LSI delay analysis method, wherein data stored in the database is used as a signal path.