JP2000047975A - Memory access control circuit - Google Patents

Abstract

[PROBLEMS] To provide a highly versatile memory access control circuit having a simple structure capable of improving system performance and minimizing MPU-memory access. Reference numeral 22 handles priority processing for memory access from a non-MPU. The activation access permission instructing unit 67 receives an access permission for the memory access from the non-MPU from the memory arbiter 22, and when the memory bus is used or when the memory access from the non-MPU and the memory access from the MPU occur simultaneously. Otherwise, the memory access right is directly given to the MPU. In addition to the above, the memory access from the non-MPU is transferred to the rotation priority processing in the priority processing of the memory arbiter 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory access control of a processor for controlling an exchange and the like.

[0002]

2. Description of the Related Art In an exchange, as shown in FIG. 1, a CPU (Central Processing Unit) for a line exchange switch for controlling a switch for switching a communication line is a system control CPU for controlling the entire exchange.
1 via a bus A.

Further, the system control CPU 1 is provided with a system control CPU 2 so as to cope with a failure of the exchange.
With a duplex configuration. Therefore, the system control CPU 1 and the system control CPU 2 have the configuration shown in FIGS. 2, 3 and 5 described later, and the area surrounded by the broken line in FIG. 1 actually has the configuration shown in FIG. I have.

In FIG. 2, a memory 4 is mounted on an I / O bus (a bus to which I / O is connected) 8 and an MPU (Micro Processor) is mounted.
The ssing unit (small processing unit) 1 is connected to an I / O bus 8 via a bus bridge 6 for performing format conversion. On the other hand, FIG. 3 shows that the memory 4 is connected to an MPU bus (MPU bus).
The I / O 3 is connected to the MPU bus 10 via the bus bridge 7.

[0005] The configuration of FIG. 2 and FIG. 3 is replaced by a duplicated memory configuration (for example, the own system is used as an act system and the other system is used as a standby system).
4 and FIG. 5 are obtained. The memories 4 and 14 are written and read under control of the main storage controllers 2 and 12 via memory buses (buses connected to the memories) 9 and 19. Own system and other system,
Transfer between the memories 4 and 14 is performed via the memory crossing buses 5 and 15.

[0006] The memory data is transferred via the memory crossing buses 5 and 15 so that the contents of the memories always coincide with each other. Further, when switching between the act system and the standby system, it is necessary to perform data transfer or the like for inheriting data from the old act system to the new act system. These data transfer controls are performed by the main storage controllers 2 and 12. The main storage controllers 2 and 12 have a function as a bus bridge for bridging each bus and a memory bus, a function of a refresh circuit when the memory element is a DRAM, and a function of an error correction / detection circuit. Error correction is
A real-time correction performed at the time of memory reading and a memory patrol function for autonomously inspecting the memory at certain fixed periods are enabled.

The main storage controllers 2 and 12 are provided with an MPU.
1. Arbitration for external access such as I / O3, memo refresh from the main storage control units 2 and 12 itself, and memory access from inside such as memory patrol. In the configuration of FIG. 4, the access requesting use of the memory bus 9 to the main storage controllers 2 and 12 is performed by the MPU 1, the I / O 3, the memory intersection device 5 and the main storage controller itself (memo refresh) via the bus bridge 6. And for processing such as memory patrol).

When the MPU 1 performs memory access, it first requests the main storage controller 2 to use the memory bus via the bus bridge 6. The main memory control device 2 performs a memory access by requesting the use of another memory bus and arbitrating the memory bus. As a result, the response is transmitted to the bus bridge 6.
, A handshake control of notifying the MPU 1 is performed.

[0009]

However, the conventional one has the following problems. 1. The prior art shown in FIGS. 4 and 5 is a means for constructing a processor system while making use of the interface of the existing system. Although there is an advantage in that the existing technology can be used, the bus bridges 6 and 7 are used. However, there is a problem that the performance of the system is deteriorated. 2. Conventional one-to-one memory access control between a memory access master such as an MPU and a memory is performed in a multi
(U, I / O, memory crossing device, main memory control device, etc.) When applied to one-to-one memory access control, the circuit configuration of the main memory access control circuit and the like becomes complicated. In the case of configuring a many-to-one architecture, specific control such as DRAM-specific refresh control (normally, a refresh counter and a physical interface control circuit are built in the main memory control circuit) and external memory access. However, there is a problem that it is difficult to control to avoid the conflict between the two. 3. In the case of a redundant system configuration, since the confounding operation between the memories of both systems operates as a subordinate to the memory access operation, the transfer amount of the memory intersection (for example, the transfer of the old act side memory data at the time of switching between the act system and the standby system) ) Causes a problem that the operation speed of the system decreases. 4. In the case of a many-to-one architecture, the priority of MPU access is controlled to be equal to that of I / O and the like, so that there is a problem that the system performance is not improved even if only the external bus arbitration is improved. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is a memory access control circuit capable of improving system performance and minimizing access between an MPU and a memory. It is an object of the present invention to provide a memory access memory control circuit with high performance.

[0011]

According to the first aspect of the present invention, a processor MPU, an input / output device I / O, and a main storage device 2 are connected, and the processor and the input / output device are connected to the main storage device. A memory arbiter 22 for arbitrating the memory access request of the above and a memory access control circuit comprising a main memory access circuit 21 for controlling memory access from the processor and the input / output device. It has fixed priority processing means 50 for permitting access by fixed priority processing of the access right, and rotation priority processing means 51 for performing processing by shifting the access right according to the state of the request. Switching between the fixed priority processing means and the rotation priority processing means depending on the state of the access request of A memory access control circuit and performing.

According to the first aspect of the present invention, the memory arbiter is provided with the fixed priority processing means 50 and the rotation priority processing means 51 for giving the right of access to the main storage device to access from the processor and the input / output device. By switching between fixed priority processing means and rotation priority processing means according to the state of a request and controlling access to a main storage device, system performance is improved, and a memory access control circuit with a simple structure and high versatility is provided. be able to. Also, operations for ensuring the premise of using the memory, such as a refresh operation, a protection operation in the event of a reset during access, and a memory error correction operation, are given a fixed priority, and DMA operation, memory read /
By setting the normal memory use operation such as the write operation to the rotation priority, fine-grained priority processing can be performed to ensure the use of the memory.

According to a second aspect of the present invention, in the memory access control circuit of the first aspect, after the access request from the processor is permitted, the fixed priority process 50 is performed, and the processor and the main storage device are executed. The memory arbiter controls the main memory access circuit 21 so as to enable DMA transfer between them. According to the second aspect of the present invention, after the access request from the processor is permitted, the fixed priority process 50 is performed to minimize the MPU-memory access and to speed up the memory access to the MPU. A possible memory access control circuit can be provided.

According to a third aspect of the present invention, in the memory access control circuit of the first aspect, the main storage device 2
Is provided in the memory access control circuit, and is processed by the fixed priority processing 50. According to the third aspect of the present invention, an error correction function of the main storage device 2 is provided in the memory access control circuit and is processed by the fixed priority processing 50, so that the error correction operation is performed with the highest priority, quickly and reliably. Can be done.

According to a fourth aspect of the present invention, in the memory access control circuit of the first aspect, the input / output device I
For the memory access from the / O, priority processing is handled by the rotation priority processing means 51 and the fixed priority processing means 50. The memory access from the processor is performed when the memory bus is already used or when the input / output is performed. Only when memory accesses from the device occur at the same time, the memory access from the processor is processed by the rotation priority processing means.

According to the fourth aspect of the present invention, priority processing is performed by the rotation priority processing means 51 and the fixed priority processing means 50 for memory access from the input / output device I / O. For the memory access from the processor, the memory access from the processor is processed by the rotation priority processing means only when the memory bus is already used or when the memory access from the input / output device occurs at the same time. By doing so, the memory access from the MPU can be made direct memory access except when the memory bus is already in use or when memory access from the input / output device occurs at the same time.
Control is performed as if the memory is directly connected to the MPU, and memory access to the MPU can be performed at high speed.

[0017]

FIG. 6C shows a basic configuration diagram of the present invention. The main memory access control circuit 21 and the memory arbiter 22 shown in FIG. 6C are a main memory integrated with the bus bridge 7, the main memory control circuit 2 and the memory intersection device 5 shown in FIG. 6A (corresponding to the configuration in FIG. 5). Storage control circuit and bridge circuit 2
0 is functionally divided. That is, of the main memory control circuit and the bridge circuit 20, the memory arbiter function is provided to the memory arbiter 22, and the other memory access control functions are provided to the main memory access control circuit 21.

The main memory access control circuit 21 of the present configuration
MPU1, I / O3, other system memory 14, and firmware 23
Memory bus use request for the memory 4 from
Together with the memory arbiter 22, it performs unified access control. FIG. 7 shows a configuration example of the main memory access control circuit 21. The main memory access control circuit 21 includes a multiplexer and a register (Multiplexer & Regis).
ter) 31, 32, a RAM access control circuit 33, and a read data reception and ECC circuit 34.
The multiplexers and registers 31 and 32 have registers for timing control, and the RAM access control circuit 33
And selects and outputs one of the input signals to which the access right has been granted. Multiplexer and register 3
1 receives the memory access information permitted to be accessed from the RAM access control circuit 33, and receives an MPU, an I / O, another memory receiving circuit, another memory transmitting circuit, and a firmware (F
irm), the access request from the ECC check circuit and the ECC correction circuit to the memory 4 is treated equally, and has a function as an address selector for generating an access-permitted address. Multiplexer and register 32
Similarly, upon receiving the memory access information permitted to be accessed from the RAM access control circuit 33, the MPU,
The I / O, the other-system memory receiving circuit, the firm (Firm), and the write-back data writing circuit generate RAM write data for memory access to the memory 4 to which access is permitted, and have a function as a data selector. The RAM write data is generated by ECC generation after selection.
CC is given. RAM read data from the memory 2 is received by the read data reception and ECC circuit 34,
An ECC check is performed, and if an error is detected, writing back is performed.

FIG. 8 shows a configuration example of the RAM access control circuit 33. The RAM access control circuit 33 includes a RAM access activation control circuit 36, an address selection control circuit 37, and a read data control circuit 38. The RAM access activation control circuit 36 provides the memory arbiter 22 with access activation signals of a write access activation (Write Start), a read access activation (Read Start), a refresh cycle activation (Refresh Start), and a data size signal from the bus master I / F. data size), and activates each sequence of word access and byte access.

Upon receiving the start signal, the RAM access start control circuit 36 receives the address output position information (Row).
The sequencer that controls the address cycle and the column address cycle operates and sends an address strobe signal. In addition, the write / read type and access direction control (memory selection, data path driver control, etc.) for the mounted memory are output during the access period.

The address selection control circuit 37 instructs the selection of the bus master address as a Row / Column address under the address position control in which the address position is determined by the selection and activation control of the address of the bus master permitted to use the bus. The selection of the write data uses the bus use permission signal as it is. Read data control circuit 38
Determines the data reception position according to the reading time of the RAM by the address position control, and performs the read data reception position and the write control of the read data storage buffer.

FIG. 9 shows a read data reception and control circuit 34.
An example of the configuration will be described. The read data includes a reception register 41 that stores the read data according to the read data reception position of the access control circuit, an ECC check and correction circuit 40,
It comprises a syndrome buffer 42 attached to the ECC circuit, and a burst read data buffer 43 for storing memory data correction data.

The ECC check and correction circuit 40 compares the ECC with the regenerated ECC code based on the read data, and if there is a 1-bit error, calculates the correction part from the syndrome (ECC comparison result) and corrects it. 1 at the same time
A bit / 2-bit error flag is sent out to notify an error state and start ECC correction. Syndrome buffer 4
2 is stored when an error occurs in order to determine whether the one-bit error is an intermittent error or a fixed error.

The burst read data buffer 43 has 1
Correction data for performing correction writing at the time of a bit error is temporarily stored. Reading is selected by the error correction RAM access permission signal of the memory arbiter 22. FIG. 10 shows a configuration example of the memory arbiter 22. The memory arbiter 22 includes a fixed priority processing unit 50 and a rotation priority processing unit 51. The fixed priority processing unit 50 handles a memory access set with a higher priority than the rotation priority processing unit 51. For a device that requires a fixed high priority, such as a refresh operation, a protection operation in the event of a reset during access, and a memory error correction operation, a fixed priority system is adopted.
A rotation priority method is adopted for a memory write / read operation including an MA operation and a memory maintenance (including a memory patrol operation and the like). The MPU is automatically permitted to use the memory bus when there is no other memory bus access request. However, if a memory bus is used at the time of memory access by the MPU, the rotation priority method is adopted. The bus use permission signal of the fixed priority processing unit 50 includes access type information indicating any one of read, write, and refresh in the bus use permitted signal.

FIG. 13 shows an example of the rotation priority sequence. The numbers indicate transition conditions. The right to use the bus access is given in the direction of the arrow. For example, when a bus permission is given to another system read and another system read is performed (8), then a bus use right is given to another system write. In this way, the sequence proceeds in the order of the transition numbers, but if there is no other high priority, the current bus access jumps to the highest priority location.

In the example of FIG. 13, after reset, the right to use the bus is set to the I / O read with the first priority. When the power of the processor system is turned on, the memory bus use request is masked to temporarily give a fixed priority, and only the memory initialization, firmware transfer, and refresh are performed without processing other bus accesses. good. FIG.
The other-system transmission in 3 is the other-system transmission or the like accompanying the exchange of memories by DMA transfer from the old memory to the new memory when the CPU 1 and CPU 2 in FIG. 1 switch between the active system and the standby system. FIG. 13 is an example, and various rotation priority sequences can be considered.

FIG. 11 is a diagram for explaining a memory access permission for the MPU 1. Memory arbiter 22
Handles priority processing for memory accesses from non-MPUs. The non-MPU access permission is notified to the main memory access control circuit 21. The MPU access control unit 69 includes a start control unit 66 and an access permission instruction unit 67.
The activation access permission instructing unit 67 always receives an access permission signal for memory access from the non-MPU from the memory arbiter 22, and when the memory access from the MPU,
Unless the memory bus is used or the memory access from the non-MPU and the memory access from the MPU occur at the same time, the MPU and the memory are directly connected to each other by directly granting the MPU the right to use the memory. Enable transfer.

However, the activation access permission instructing unit 67
When a memory bus is already in use or when a memory access from a non-MPU and a memory access from the MPU occur at the same time at the time of memory access from the MPU, the memory access from the MPU is given priority for rotation in the priority processing. Delivered to processing. Next, access control from I / O will be described.

At the time of a read request from I / O, MPU
And a read request to the memory. If there is a cache miss on the MPU side, control is performed to read data from the memory. If there is data in the MPU cache, control is performed to read data from the MPU cache. . At the time of a write request from I / O, M
A read request is made to the PU and the memory, respectively, and the same operation as in reading is performed.

If there is a hit in the MPU cache, the contents are replaced with write data from I / O,
Write processing to the memory. If there is no hit in the MPU cache, the corresponding content is read from the memory, and the content is replaced with the write data from the I / O,
Perform write processing to the memory.

FIG. 12 is a diagram for explaining the arbiter core 68 and the MPU memory access control unit 69. Memory access is controlled by an arbiter body (arbiter core) 68 and an MPU memory access control unit 69 built in the MPU I / F. The arbiter core 68 includes a request reception and mask processing unit 61, 62, a bus right destination determination unit 63, an access type determination and activation instruction unit 65.

Request reception and mask processing units 61 and 6
Reference numeral 2 denotes an MPU (memory access request transmitted from the MPU reception determination unit) and a non-MPU bus request (refresh, ECC correction request, I / O bus access, other system memory transmission request, firmware transfer request, other system memory reception request And an ECC check request), and performs a mask process according to the state of the system. An example of the mask processing is shown below.

MPU request: When the memory crossing transmission buffer is full during system initialization and duplex operation Refresh: None ECC correction: None I / O bus access: Memory initialization transmission buffer during system initialization and duplex operation When full Other system memory transmission: When system initialization, duplex operation, and memory crossing transmission buffer is full Farm transfer: None Other system memory reception: During system initialization, non-redundant operation ECC check: System non-initialization When the ECC check is disabled, the logical output C of the request reception and mask processing units 61 and 62 is as follows: C = Request A × [Negation of (Mask B)], where Mask condition is Mask B for Request A. .

It should be noted that the addressing for memory initialization at the time of system initialization when the power is turned on and the addressing for memory ECC check control during system operation are shared. By sharing, the request signal can be deleted regardless of the presence or absence of the initialization mode, and the number of arbitrations can be reduced. The bus right destination determination unit 63 determines the bus right destination based on the masked request signal and the arbitration timing transmitted from the timing control unit 68. In the determination of the bus right, the fixed priority has priority over the rotation priority.
The fixed priority is determined, for example, by the following priority. The fixed priority order and the access type are shown in parentheses.

1. 1. Even bank refresh (refresh) 2. Odd-numbered bank refresh (refresh) 3. ECC error correction first word (write) 4. ECC error correction and reconfirmation first word (read) 5. ECC error correction second word (write) 6. ECC error correction and reconfirmation 2nd word (read) 7. Third word of ECC error correction (write) 8. Third word of ECC error correction and reconfirmation (read) 9. ECC error correction 4th word (write) Fourth word (read) for reconfirmation after ECC error correction Rotation priority access (read or write) In consideration of current consumption when refresh is operated simultaneously, it has two refresh cycles of even and odd banks, and is configured to reduce peak current consumption by interleaving operation. I have. ECC supports up to 4-word burst read. These conditions can be set arbitrarily.

The timing control section 68 monitors the memory access state and detects a phase (corresponding to arbitration timing) at which bus access permission is determined. The arbitration timing is determined based on the following conditions. 1. When a memory bus access end notification is received from the memory access circuit (at this time, the next access permission determination is made to block the arbitration cycle, and to suppress a decrease in throughput due to arbitration when a plurality of bus masters are accessing. 1.) MPU with all non-MPU access permissions negated
A state in which access from the I / F is not suspended (such as at the time of read-modify-write or continuous write) and a state in which no memory access exists. When this is expressed by a logical expression, arbitration timing = (memory access completion notification) or (not All MPU access permissions are negated) and (access from the MPU I / F is not suspended).

The rotation priority determining section 64 sets a rotation priority as shown in FIG. Even if the priority is low, the access right is granted if there is no memory access request having a higher priority. The access type determination and activation instructing unit 65 determines the type of the permitted bus access (refresh, read, write), and generates a unique activation signal (refresh activation, read activation, write activation). Thus, the main memory access control circuit can simplify the sequence determination circuit and reduce the hardware load. Note that the activation instruction signal is constituted by a differentiating circuit that transmits at the same time as the rise of the access permission signal.

On the other hand, the MPU memory access control section 69 having a built-in MPU includes an access permission instructing section 67 and an activation control section 66. The start control unit 66 merges a start instruction signal from the arbiter core 68 (a write start instruction, a read start instruction, and refresh is irrelevant for the memory operation assurance function) and an access start signal for MPUI / F autonomous start. To the main memory access control circuit 21. Further, it receives the end notification from the main memory access control circuit 21 and transmits it to the arbiter core 68 and clears the access permission signal.

The access permission instructing unit 67 checks the MPU access permission state from the arbiter core 68, and if the MPU access permission state is received at the time of receiving the access from the MPU,
The memory access is immediately started without going through the arbiter core 68. That is, the MPU access enable signal is received from the memory arbiter, and the arbiter is enabled (MPU
Is recognized as the status of the memory arbiter. When this signal is asserted, the configuration is such that the memory access permission can be determined by the MPU I / F. This permission signal is negated asynchronously with the memory access unit, and waits until this signal is negated. The wait state is a handshake mode of request / access permission as in the other bus masters. The access request can be expressed by the following logical expression.

MPU request = [negation of (access enable signal)] AND memory access reception OR (during read-modify-write) When access is permitted and read-modify-write is received, a request signal is transmitted to arbiter core 68, and rotation priority is given. Wait for the bus right permission judgment. FIG. 14 shows a flowchart example of the operation of the arbiter core and the MPU memory access control unit described above.

[0041]

According to the present invention as described above, the following various effects can be realized. According to the first aspect of the present invention, the memory arbiter gives the access right to the main storage device the fixed priority processing means 50 and the rotation priority processing means 5
1 to control the access to the main storage device by switching between the fixed priority processing means and the rotation priority processing means according to the state of the access request from the processor and the input / output device, thereby improving the system performance and improving the structure. A simple and versatile memory access control circuit can be provided.
Also, operations for ensuring the premise of memory use, such as a refresh operation, a protection operation in the event of a reset during access, and a memory error correction operation, are given fixed priority, and DMA
Since the rotation and the normal memory use operation such as the operation and the memory read / write operation are prioritized for rotation, fine-grained priority processing can be performed to ensure the use of the memory.

According to the second aspect of the present invention, after the access request from the processor is granted, the fixed priority processing 50
By doing so, it is possible to provide a memory access control circuit capable of minimizing MPU-memory access and increasing the speed of memory access to the MPU. According to the third aspect of the present invention, an error correction function of the main storage device 2 is provided in the memory access control circuit and is processed by the fixed priority processing 50, so that the error correction operation is performed with the highest priority, quickly and reliably. Can be done.

According to the fourth aspect of the present invention, priority processing is performed by the rotation priority processing means 51 and the fixed priority processing means 50 for memory access from the input / output device I / O. For the memory access, the memory access from the processor is processed by the rotation priority processing means only when the memory bus is already used or when the memory access from the input / output device occurs at the same time. Memory access from the MPU is performed unless the memory bus is already in use or memory access from the input / output device occurs at the same time.
By enabling direct memory access, control is performed as if the memory were directly connected to the MPU.
Memory access to the PU can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a basic configuration of an exchange.

FIG. 2 is a diagram illustrating a configuration example (part 1) of a conventional processor device.

FIG. 3 is a diagram illustrating a configuration example (part 2) of a conventional processor device.

FIG. 4 is a diagram illustrating a configuration example (part 3) of a conventional processor device.

FIG. 5 is a diagram for describing a configuration example (part 4) of a conventional processor device.

FIG. 6 is a basic configuration diagram of the present invention.

FIG. 7 is a diagram illustrating a configuration example of a main memory access control circuit.

FIG. 8 is a diagram illustrating a configuration example of a RAM access control circuit.

FIG. 9 is a diagram for describing a configuration example of a read data reception and ECC circuit.

FIG. 10 is a diagram for describing a configuration example of a memory arbiter.

FIG. 11 is a diagram for explaining memory access permission for an MPU.

FIG. 12 is a diagram for explaining an arbiter core and an MPU memory access control unit.

FIG. 13 is a diagram for describing an example of a rotation priority sequence.

FIG. 14 is an example of a flowchart of an operation of an arbiter core and an MPU memory access control unit.

[Explanation of symbols]

 Reference Signs List 1 MPU 3 I / O 4 memory 5 memory intersection device 21 main memory access control circuit 22 memory arbiter 69 MPU memory access control unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeru Shinohara 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu Digital Technology Co., Ltd. In-house (72) Kenji Fujizono 2 Momochihama, Sawara-ku, Fukuoka-shi, Fukuoka No.2-1, Fujitsu Kyushu Communication System Co., Ltd. (72) Inventor Yasuhiro Ishikawa 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture F-term in Fujitsu Limited 5B060 CD12 KA03 KA04

Claims (4)

[Claims] 1. A processor, an input / output device, and a main storage device are connected, and a memory arbiter for arbitrating a memory access request from the processor and the input / output device to the main storage device, and the processor and the input / output device A memory access control circuit comprising a main memory access circuit for controlling memory access from the memory access control circuit, wherein the memory arbiter includes a fixed priority processing means for granting an access right to the main storage device by a fixed priority process; A rotation priority processing unit for performing a process by making a transition according to a request state, and switching between the fixed priority processing unit and the rotation priority processing unit according to the state of the access request from the processor and the input / output device; A memory access control circuit for controlling access to a storage device. 2. After the access request from the processor is granted, fixed priority processing is performed, and the memory arbiter controls the main memory access circuit so as to enable DMA transfer between the processor and the main storage device. 2. The memory access control circuit according to claim 1, wherein the control is performed. 3. The memory access control circuit according to claim 1, wherein an error correction function of said main storage device is provided in said memory access control circuit, and processing is performed by fixed priority processing. 4. A priority process is handled by the rotation priority processing means and the fixed priority processing means for a memory access from the input / output device, and a memory access from the processor is already performed using a memory bus. 2. The memory access control circuit according to claim 1, wherein the memory access from the processor is processed by the rotation priority processing means only when the memory access is performed or when the memory access from the input / output device occurs simultaneously.