JP2000040964A - Comparison circuit and AD conversion circuit - Google Patents

Abstract

(57) Abstract: In a successive approximation type AD conversion circuit including a comparison circuit using a conventional CMOS inverter type amplifier circuit, an output of a local DA conversion is almost equal to an analog input at a final stage of a conversion operation. Therefore, there is a problem that the input voltage of the amplifier circuit approaches the logic threshold value and the through current flows for a long time, so that the power consumption is large. SOLUTION: A CMOS inverter type amplifier circuit (AM)
P), a first switch means (SW2) connected between the input and output terminals of the amplifier circuit, a sampling capacitor (Cs) connected between the input terminal and the analog input terminal of the amplifier circuit, In a comparison circuit (CMP) comprising a switching switch means (SW1) capable of selectively supplying a voltage of the analog input terminal or a comparison voltage to one terminal of the sampling capacitor, a MOSF constituting the amplification circuit
The second switch means (MP4, MN4) is connected in series with the ET, and this switch means is turned on only during the sampling period of the analog input to the sampling capacitor and during the stable period of the input of the amplifier circuit to perform the amplification operation. It was configured to do so.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for reducing the power consumption of a comparison circuit using a CMOS (complementary MOSFET) inverter type amplifier circuit, and is used, for example, for a comparison circuit constituting a successive approximation type AD conversion circuit. Effective technology.

[0002]

2. Description of the Related Art Conventionally, as a comparison circuit constituting a successive approximation type AD conversion circuit, for example, there is a circuit as shown in FIG.

The comparison circuit shown in FIG. 6 is a p-channel MOSFET connected in series between power supply voltage terminals.
C composed of MP1 and n-channel MOSFET MN1
The sampling capacitor Cs and the changeover switch SW1 are connected to the gate input terminal side of the MOS inverter type amplifier circuit AMP, and a switch SW2 is provided between the input and output terminals.
W1 is connected to the input terminal INa side, and the analog input Vin
And the logic threshold voltage V of the amplifier circuit (inverter) AMP
The capacitor Cs is charged with a voltage difference from LT, then the switch SW2 is turned off to open the input / output terminals of the amplifier circuit AMP, and the switch SW1 is switched to the input terminal INc side of the comparison voltage Vc, thereby obtaining an analog input signal. The comparison between Vin and the comparison voltage Vc is performed, and the comparison result is amplified and output.

More specifically, if the comparison voltage Vc is lower than the voltage Vin charged to the capacitor Cs immediately before, the input voltage of the amplifier circuit AMP is lower than the logical threshold, and the output becomes high level. If the comparison voltage Vc is higher than the voltage Vin charged in the capacitor Cs, the amplifier circuit AMP
Since the input voltage is higher than the logical threshold, the output becomes low level, so that the analog input voltage Vin and the comparison voltage Vc
The output according to the magnitude of the above is obtained. The comparison result is latched by a latch circuit LTH that performs a latch operation in synchronization with the clock CK.

FIG. 7 shows operation waveforms when the comparison circuit of FIG. 6 is used in a successive approximation type AD conversion circuit. In the successive approximation type A / D conversion circuit of FIG. 6, a voltage (a voltage that changes in a step-like manner) is sequentially supplied to a comparison voltage side of the switch SW1 from a local D / A conversion circuit LDAC that performs D / A conversion of a comparison result by the comparison circuit CMP. . In FIG. 7, since the output of the amplifier circuit AMP is latched by the latch circuit LTH at timings t3, t5, and t7, the voltage from the local DA conversion circuit LDAC changes, and the input terminal of the amplifier circuit AMP is correspondingly changed. The potential of (node A) is also changing.

[0006]

In the successive approximation type AD conversion circuit using the comparison circuit shown in FIG.
At the final stage of the conversion operation (period Tc3 in FIG. 7), the local DA
Since the output of the conversion circuit LDAC becomes almost equal to the analog input, the input voltage of the amplifier circuit approaches the logic threshold,
As a result, a through current flows through the MOSFETs MP1 and MN1.

As described above, the comparison circuit shown in FIG. 6 has a long time for the through current to flow and consumes a large amount of power. In addition, when the through current flows, noise is generated in the power supply voltage. It became clear that there was a problem that the circuit could be adversely affected.

An object of the present invention is to provide a comparison circuit with low power consumption and low noise. It is another object of the present invention to prevent a through current of a comparison circuit using a CMOS inverter type amplifier circuit, and to reduce power consumption and noise of a successive approximation A / D conversion circuit including the comparison circuit. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a serial p-channel MOSF
A CMOS inverter-type amplifier circuit composed of an ET and an n-channel MOSFET; first switch means connected between input / output terminals of the amplifier circuit; and an input terminal connected to an analog input terminal of the amplifier circuit. And a changeover switch means for selectively supplying a voltage of the analog input terminal or a comparison voltage to one terminal of the sampling capacitor. The second switch means is connected, and the switch means is turned on only during the sampling period of the analog input to the sampling capacitor and only during the stable period of the input of the amplifier circuit to perform the amplification operation.

According to the above-mentioned means, the current path of the amplifier circuit is cut off during an unnecessary period, so that the potential difference between the analog input and the comparison voltage is small, and the p-channel MOS transistor of the serial type is used.
Even when both the FET and the n-channel MOSFET are turned on, it is possible to prevent a through current from flowing, thereby achieving the object of reducing power consumption and noise. .

Further, a latch circuit is provided at the next stage of the amplifier circuit, and the latch circuit and the second switch means are controlled by the same signal (clock signal). This makes it possible to easily form a control signal for the newly provided current cutoff switch means.

Further, the second switch means for interrupting the current is a p-channel MO of a serial form constituting an amplifier circuit.
It is provided on each side of the SFET and the n-channel MOSFET. As a result, the operating characteristics when the output of the amplifier circuit changes to a high level and when the output changes to a low level can be made substantially the same, and the characteristic balance of the amplifier circuit can be improved.

The amplifier circuit may be connected not only in one stage but also in two or three or more stages. In that case, a switch means for preventing a through current is connected to each amplifier circuit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a successive approximation type AD conversion circuit using a comparison circuit according to the present invention. The AD conversion circuit shown in FIG. 1 includes a comparison circuit CMP that compares an analog input Vin input to an analog input terminal INa with a comparison voltage Vc input to a comparison-side input terminal INc, and an output of the comparison circuit CMP. A latch circuit LTH for latching
A code forming circuit CDC for forming a code based on a plurality of bits output from the latch circuit LTH, and a local DA converting circuit LDAC for DA converting the code output from the code forming circuit CDC and forming the comparison voltage Vc. It is configured.

The code forming circuit CDC determines a code generated by a local DA conversion circuit LDAC to be used, and may be constituted by, for example, a simple shift register.

The comparison circuit CMP includes a p-channel MOSFET connected in series between power supply voltage terminals.
CM consisting of MP1 and n-channel MOSFET MN1
OS inverter type amplifier circuit AMP and said amplifier circuit AMP
Capacitor Cs and changeover switch S connected between the gate input terminal of
W1, a switch SW2 connected between the input and output terminals of the amplifier circuit, and a current cutoff MOSF connected between the p-channel MOSFET MP1 and the power supply voltage terminal Vcc.
ET MP4 and current blocking MOSFET MN4 connected in series with n-channel MOSFET MN1
It is composed of And these current interrupting M
OSFETs MP4 and MN4 are connected to the latch circuit LTH.
Is controlled by a clock CK for operating the clock signal and a signal obtained by inverting the clock CK by an inverter INV.

In the comparison circuit CMP of this embodiment, the switch SW1 is connected to the input terminal I while the switch SW2 is turned on.
Na, and charges a sampling capacitor Cs with a difference voltage between the analog input Vin and the logical threshold voltage VLT of the amplifier circuit (inverter) AMP.
2 is turned off, the input and output terminals of the amplifier circuit AMP are opened, and the switch SW1 is switched to the input terminal INc side of the comparison voltage Vc.
In is compared with the comparison voltage Vc, and the comparison result is amplified and output.

Specifically, the sampling capacitance Cs immediately before
If the comparison voltage Vc is lower than the voltage Vin charged to the amplifier circuit AMP, the input voltage of the amplifier circuit AMP is lower than the logical threshold, so that the output goes to a high level, and is compared with the voltage Vin charged to the sampling capacitor Cs immediately before. If the voltage Vc is higher, the input voltage of the amplifier circuit AMP is higher than the logical threshold and the output becomes low level, so that an output corresponding to the magnitude of the analog input voltage Vin and the comparison voltage Vc is obtained. is there. The result of the comparison is a latch circuit LT that performs a latch operation in synchronization with clock CK.
Latched to H. Moreover, in this embodiment, the clock C
The current interrupt MOSFETs MP4, M
N4 is turned on only during the sampling period of the analog input to the sampling capacitor Cs and during the period when the input of the amplifier circuit AMP is stabilized, so that the amplification operation is performed.

FIG. 2 shows operation waveforms of the AD conversion circuit shown in FIG.

In the AD conversion circuit of this embodiment, first, the switch SW2 is turned on to turn on the inverter type amplification circuit A.
With the input / output terminal of MP short-circuited, switch SW1
Is connected to the input terminal INa side (period Ts). At this time, the clock CK is set to the low level and the switch MO
The SFETs MP4 and MN4 are turned on. Then, the input / output terminals of the amplifier circuit AMP are short-circuited, so that the potentials of the nodes A and B become the logical threshold voltage VLT of the inverter (AMP) as shown in FIGS.
Changes to Therefore, a through current flows through the amplifier circuit AMP during this time.

FIG. 2 shows a case where the potential of node A approaches VLT from the ground potential. However, depending on the state before the AD conversion circuit, the potential of node A is changed to the power supply voltage as shown by a broken line. It may approach VLT from the Vcc side. Then, by setting the potentials of the nodes A and B to the logic threshold voltage VLT of the inverter (AMP), the difference voltage between the analog input Vin and the logic threshold voltage VLT is charged to the sampling capacitor Cs.

Thereafter, the clock CK is set to a high level to turn off the MOSFETs MP4 and M4, and the switch S
W2 is turned off to open the input and output terminals of the amplifier circuit AMP, and the switch SW1 is switched to the terminal INc to which the comparison voltage Vc supplied from the local DA converter LDAC is input (timing t1). Then, the input of the amplifier circuit AMP, that is, the potential of the node A in FIG. 1 changes according to the level of the analog input signal Vin and the level of the comparison voltage Vc (period Tc1). FIG. 2 shows a case where the comparison voltage Vc is lower than the analog input signal Vin.

Then, the clock CK is changed to a low level when the potential of the node A is stabilized. Thus, the output of the amplifier circuit AMP, that is, the potential of the node B changes to a high level or a low level (high level here) (timing t2). That is, the result of comparison between the analog input signal Vin and the comparison voltage Vc appears at the node B. The output state is latched by the subsequent latch circuit LTH by changing the clock CK to the high level at the timing t3.

When the output is determined by the latch operation of the latch circuit LTH, the output is output to the code forming circuit CD.
Since the new code is supplied to C and the new code is generated, the output of the local DA conversion circuit LDAC changes. for that reason,
Local DA conversion circuit LDAC via switch SW1
Is transmitted to the capacitor Cs, and the potential of the node A changes (period Tc2). In the AD conversion circuit of this embodiment, the local D / A conversion circuit LD is used for each comparison operation in the comparison circuit CMP.
The code is generated by the code forming circuit CDC so that the AC output voltage approaches the logical threshold value VLT of the amplifier circuit AMP (the potential difference from VLT becomes smaller).

Then, when the potential of the node A is stabilized, the clock CK is changed to the low level again. As a result, the output of the amplifier circuit AMP, that is, the potential of the node B becomes high level or low level (high level here) (timing t4). This output state is latched by the subsequent latch circuit LTH by changing the clock CK to the high level at the timing t5.

By repeating the above operation, node A
Gradually approaches the logic threshold VLT of the amplifier circuit AMP. As a result, a result (code) obtained by AD-converting the analog input Vin is obtained from the latch circuit LTH.
In addition, since the potential of the node A gradually approaches the logical threshold value VLT of the amplifier circuit AMP as the final step of the AD conversion operation, a through current easily flows through the amplifier circuit AMP. However, in this embodiment, the MOSFETs MP1 and MN1 constituting the amplification circuit AMP are connected in series with the MOSFETs MP1 and MN1.
Since MP4 and MN4 are provided and controlled by the clock CK, and the amplifier circuit AMP is activated only in the last part of each conversion step, a slight period like the hatched period Tc3 in FIG. The through current will flow only for a short time. As is clear from comparison with FIG. 7D showing the through current in the same state in the AD converter circuit using the conventional comparison circuit, it is clear that the AD converter circuit using the comparison circuit of this embodiment has a large through current. It can be seen that is reduced.

The output of the latch circuit LTH is supplied to the code forming circuit CDC, and is immediately output as an AD conversion result via an interface circuit as it is depending on the configuration of the circuit receiving the output, or the output of the latch circuit LTH is serially output. -In some cases, the data is output after being converted into parallel data by a parallel conversion circuit.

FIG. 3 shows another embodiment of the successive approximation type AD conversion circuit using the comparison circuit according to the present invention. In this embodiment, a CMOS inverter type amplifier circuit is cascade-connected in three stages, and a p-channel MOSFET constituting each amplifier circuit is connected.
P-channel MOSFETs MP4, MP5, and MP6 for interrupting current in series with T MP1, MP2, and MP3, and n-channel MOSFETs M that constitute each amplifier circuit.
N1, MN2 and MN3 are connected in series with n-channel MOSFETs MN4, MN5 and MN6 for interrupting current, respectively, and their switch MOSFETs MP4 and MPN are connected.
5, MP6 by clock CK and MOSFET
MN4, MN5 and MN6 are controlled by the output of an inverter INV that inverts the clock CK.

In the comparison circuit of this embodiment, as in the case of the first embodiment, the amplifier circuits AMP1, AMP2 and AMP3 are activated only during the period when the clock CK is at the low level. Is the amplifier circuit AMP
Of the amplifier circuits AMP1, AMP2, AMP3 also in the final step of the AD conversion operation approaching the logical threshold value VLT.
Can be further reduced, and power supply noise can also be reduced. Moreover, in this embodiment, since the CMOS inverter type amplifier circuits are cascaded in three stages, the gain of the comparison circuit can be increased.

Next, an AD having a comparison circuit according to the present invention will be described.
An example of a suitable system using a conversion circuit will be described.
FIG. 5 shows a schematic configuration of a disk device such as a CD (compact disk) and a DVD (digital video disk).

The structure of the disk device shown in FIG. 5 will be described briefly. 50 is a disk, 51 is a spindle motor for rotating the disk, 52 is a pickup for reading and writing data stored in the disk 50, and 53 is a pickup 52 Is a thread for positioning (tracking), 54 is a motor for driving the thread 53, and 55 is an actuator for focusing the pickup 52.

The AD conversion circuit of the above embodiment is used to convert a signal (analog) from the pickup 52 into a digital signal. The signal converted by the AD conversion circuit 56 is supplied to a signal processing & control circuit 57, where control data is calculated. The signal is converted into an analog signal by a DA conversion circuit 58, and the converted signal is sent to the thread drive motor 54 and the focus actuator 55. Then, feedback control is performed.

In FIG. 5, the AD conversion circuit 56
Shows a case where the signal processing and control circuit 57 is configured as a separate semiconductor integrated circuit from the A / D conversion circuit 5.
6 and the signal processing & control circuit 57 may be formed on the same semiconductor chip to form one chip.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, in the above embodiment, the p-channel MOSF
Between ET MP1, MP2, MP3 and power supply voltage terminal Vcc and n-channel MOSFETs MN1, MN2, M
P-channel MOSF for interrupting current between N3 and ground
ET MP4, MP5, MP6 and n-channel MOSFE
Although T MN4, MN5 and MN6 are connected to each other, MOSFETs for preventing shoot-through current are p-channel MOSFETs MP1, MP2 and MP3 constituting an amplifier circuit.
And n-channel MOSFETs MN1, MN2, and MN3.

Further, in the above embodiment, the latch circuit LTH for latching the output of the amplifier circuit uses the edge trigger type for taking in data at the rising edge of the clock CK, but the level trigger type for taking in data after the level is determined. Latch circuit may be used.

Further, in the above embodiment, the p-channel MOSFETs MP1, MP2, MP
3 and n-channel MOSFETs MN1, MN2, M
A p-channel MOSFET M for interrupting current in series with N3
P4, MP5, MP6 and n-channel MOSFET MN
4, MN5 and MN6 are connected to each other, but the current interrupting MOSFET may be only one of the p-channel side and the n-channel side. However, if only one of them is used, the operation characteristics when the output of each amplifier circuit changes to a high level and when the output changes to a low level become unbalanced.
By providing a current interrupting MOSFET on each channel side, the operating characteristics when the output of the amplifier circuit changes to a high level and when the output changes to a low level can be made almost the same, and the characteristic balance of the amplifier circuit is improved. There is an advantage that can be.

In the above description, the case where the invention made by the present inventor is mainly applied to a comparison circuit used in a successive approximation type A / D conversion circuit, which is the background of the application, has been described. However, the present invention can be widely applied to a comparison circuit including a CMOS inverter type amplifier circuit and a semiconductor integrated circuit incorporating the same.

[0041]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, a CMOS inverter type comparison circuit with low power consumption and low noise is obtained, and the successive approximation type A / D conversion circuit using this comparison circuit is reduced in power consumption and noise. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 shows a successive approximation type A using a comparison circuit according to the present invention.
FIG. 2 is a circuit diagram illustrating a first embodiment of the D conversion circuit.

FIG. 2 is a waveform chart showing operation timings of the AD conversion circuit of FIG. 1 and particularly of a comparison circuit;

FIG. 3 is a successive approximation type A using a comparison circuit according to the present invention.
FIG. 6 is a circuit configuration diagram illustrating a second embodiment of the D conversion circuit.

FIG. 4 is a waveform chart showing operation timings of the AD conversion circuit of FIG. 3, particularly, a comparison circuit;

FIG. 5 is a block diagram showing a schematic configuration of a disk-type medium reproducing apparatus as an example of an application system of a successive approximation type AD conversion circuit to which the present invention is applied.

FIG. 6 is a circuit configuration diagram showing an example of a comparison circuit using a conventional CMOS inverter type amplifier circuit.

FIG. 7 is a waveform chart showing operation timings of the comparison circuit of FIG. 6;

[Explanation of symbols]

 AMP amplification circuit CMP comparison circuit LTH latch circuit CDC code formation circuit LDAC local AD conversion circuit Cs sampling capacitance Vin analog input Vc comparison voltage (output of local AD conversion circuit)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroyuki Yoneya 5-22-1, Josuihoncho, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Co., Ltd. 5J022 AA02 AB01 BA02 BA06 CF01 CF07

Claims (4)

[Claims] 1. A MOSFET comprising a p-channel MOSFET and an n-channel MOSFET in a series configuration.
An amplifier circuit having a gate terminal of T as an input terminal and a drain terminal as an output terminal; first switch means connected between an input terminal and an output terminal of the amplifier circuit; and an input terminal of the amplifier circuit A comparison circuit comprising: a sampling capacitor provided between the input terminal and the analog input terminal; and a switch device capable of selectively supplying a voltage of the analog input terminal or a comparison voltage to one terminal of the sampling capacitor. A second switch is connected in series with the MOSFET constituting the amplifier circuit, and the switch is turned on only during the sampling period of the analog input to the sampling capacitor and during the period when the input of the amplifier circuit is stabilized, thereby performing the amplification operation. A comparison circuit characterized by performing the following. 2. A comparison circuit according to claim 1, wherein a latch circuit is provided at a stage subsequent to said amplification circuit, and said latch circuit and said second switch are controlled by the same signal. . 3. The device according to claim 1, wherein said second switch means is provided on each side of a p-channel MOSFET and an n-channel MOSFET in a series configuration constituting an amplifier circuit. Comparison circuit. 4. A comparison circuit according to claim 1, 2 or 3, a latch circuit for latching an output of the comparison circuit, a code formation circuit for forming a code based on an output of the comparison circuit, and the code An A / D conversion circuit, comprising: a D / A conversion circuit that performs D / A conversion of an output of the formation circuit and supplies the output as a comparison voltage in the comparison circuit.