JP2000040368A - Differential amplifier and its speed adjustment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve yield even when unexpected fluctuation exists in a process condition by providing plural constant current transistors, connecting these plural transistor in parallel and selecting a prescribed transistor from plural transistors. SOLUTION: Plural constant current transistors 2, 3, 4 are connected in parallel, and the prescribed transistor is selected from plural transistors 2, 3, 4 by selection circuits 5, 5a, 5b. When a reset signal 13 is set in L level first beforehand, a switching transistor 9 goes to the on-state, and the transistors 2, 3, 4 goes to the off-state in the selection circuits 5, 5a, 5b. When the reset signal 13 is released, and a terminal 12 of a NAND gate 15 is made to H level, the transistors 2, 3, 4 goes to the on-state. For obtaining prescribed performance, when the fuse circuit 8 of the selection circuit 5 is cut out, the transistor connected to the selection circuit is on/off controlled, and a response speed of a DRAM input circuit is adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a differential amplifier and a speed adjusting method thereof, and more particularly to a differential amplifier suitable for a circuit operating at high speed, for example, an input circuit of a DRAM, and a speed adjusting method thereof.

[0002]

2. Description of the Related Art In a DRAM operating at a high frequency, in an input first-stage circuit in which response speed is emphasized, an N-type transistor of an input first-stage circuit is formed by changing diffusion conditions in order to correct a deviation from a design value. I was But,
In practice, there are many cases where the process conditions fluctuate slightly, and in such a case, there is a disadvantage that the process fluctuation cannot be dealt with.

In order to adjust the variation of the differential amplifier, a plurality of fuse elements are provided, and these fuse elements are appropriately destroyed.
No. 12 publication.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, to provide a novel differential amplifier suitable for use in a circuit operating at high speed, for example, a first stage input circuit of a DRAM. And a method for adjusting the speed thereof. Still another object of the present invention is to provide a novel differential amplifier and a method of adjusting the speed thereof, which can improve the yield even when there is an unexpected fluctuation in the process conditions.

[0005]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of the differential amplifier according to the present invention is a differential amplifier in which a constant current source of the differential amplifier is configured by a transistor. And a predetermined circuit is selected from the plurality of transistors by a selection circuit. In a second aspect, the plurality of transistors are formed to have different gate lengths. In a third aspect, the selection circuit is provided in each of the plurality of transistors, and in a fourth aspect, the selection circuit is The circuit includes a fuse circuit, and in a fifth aspect, the selection circuit includes a fuse circuit and a switch provided between a first power supply and a second power supply. A NAND circuit connecting a drain of the switching transistor to one terminal, inputting a reset signal to the other terminal, and connecting an output to the gate of the switching transistor, and a drain of the switching transistor. And an inverter that leads to the gate of the constant current transistor. In a sixth aspect, the differential amplifier is used in an input circuit of a DRAM. Things.

Another aspect of the method for adjusting the speed of a differential amplifier according to the present invention is to provide a differential amplifier in which a constant current source of a differential amplifier is constituted by a transistor, wherein a plurality of transistors for the constant current are provided and the plurality of transistors for the constant current are provided. Are connected in parallel, and the speed of the differential amplifier is adjusted by selecting a predetermined transistor from the plurality of transistors.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A differential amplifier according to the present invention is a differential amplifier in which a constant current source of the differential amplifier is constituted by a transistor, a plurality of the transistors for the constant current are provided, and the plurality of transistors are connected in parallel. And the configuration is such that a predetermined transistor is selected from the plurality of transistors by the selection circuit, so even if there is a change in the process conditions, it is possible to adjust the response speed,
A predetermined performance can be obtained, and therefore, the yield can be improved.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a differential amplifier according to the present invention. FIG. 1 is a circuit diagram of a specific example of a differential amplifier according to the present invention used for an input first stage circuit of a DRAM,
FIG. 1 shows a differential amplifier 1 in which a constant current source of a differential amplifier is constituted by a transistor, a plurality of the constant current transistors 2, 3, and 4 are provided, and the plurality of transistors 2, 3, and 4 are connected in parallel. And a predetermined transistor is selected from the plurality of transistors 2, 3, and 4 by a selection circuit 5, 5
a and 5b are shown as differential amplifiers, and the selection circuits 5, 5a and 5b are shown as differential amplifiers provided in respective transistors 2, 3, and 4. The selection circuit 5 has a series circuit of a hood circuit 8 and a switching transistor 9 provided between a first power supply 6 and a second power supply 7, and a drain of the switching transistor 9 connected to one terminal 11. And the other terminal 1
2 comprises a NAND gate 15 for inputting a reset signal 13 and connecting an output 14 to the gate of the switching transistor 9 and an inverter 16 for guiding the drain of the switching transistor 9 to the gate of the transistor 2 for constant current. The illustrated differential amplifier is shown.

The selection circuits 5a and 5b are also connected to the selection circuit 5
And the selection circuit 5a switches the transistor 3
Also, the configuration is such that the selection circuit 5b can control the transistor 4. Although not shown,
The gate lengths (W) of the plurality of transistors 2, 3, and 4 are formed so as to be different from each other, and the transistors are designed so that the current values of the respective transistors are different. In the above example,
Although three transistors are shown as constant current transistors, more transistors may be provided.

Hereinafter, the present invention will be described in more detail. The differential amplifier of the present invention forms a differential pair with the transistors 21 and 22, and has a current mirror circuit including transistors 23 and 24 as an active load of these transistors. And a transistor 2 serving as a plurality of constant current sources between the sources of the transistors 21 and 22 and the ground;
3, 4 are provided in parallel.

In the differential amplifier configured as described above,
First, when the reset signal 13 is set to L level, the switching transistors 9 of the selection circuits 5, 5a, 5b are turned on, and the transistors 2, 3, 4 are turned off. Here, the reset signal 13 is released and the NAN
When the terminal 12 of the D gate terminal 15 is set to the H level, the transistors 2, 3, and 4 are turned on.

In this state, for example, when the fuse circuit 8 of the selection circuit 5 is destroyed to obtain a predetermined performance, the transistor 2 is turned off. By cutting the fuse circuit of the selection circuit in this manner, on / off of the transistor connected to the selection circuit is controlled, and the response speed of the input circuit of the DRAM can be adjusted.

[0013]

The differential amplifier and the speed adjusting method according to the present invention are configured as described above, so that the yield can be improved even when there is an unexpected fluctuation in the process conditions.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a differential amplifier according to the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 differential amplifier 2, 3, 4 constant current transistor 5, 5 a, 5 b selection circuit 6 first power supply 7 second power supply 8 fuse circuit 9 switching transistor 13 reset signal 15 NAND gate 16 inverter 21, 22, 23 , 24 transistors

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[Procedure amendment]

[Submission date] June 21, 1999 (1999.6.2
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of the differential amplifier according to the present invention is a differential amplifier in which a constant current source of the differential amplifier is configured by a transistor. connect, composed from the plurality of transistors so as to select the selection circuit a predetermined transistor then
In both cases, the selection circuits are each activated by a reset signal input.
It is those of which characterized by being configured to perform conduction control of the transistor, or, the second aspect is characterized in that the gate length of said plurality of transistors formed differently, In a third aspect, the selection circuit is provided in each of the plurality of transistors. In a fourth aspect, the selection circuit includes a fuse circuit. In a fifth aspect, the selection circuit includes a series circuit of a fuse circuit and a switching transistor provided between a first power supply and a second power supply; A NAND gate for connecting a drain of the switching transistor, inputting a reset signal to the other terminal, and connecting an output to the gate of the switching transistor, And an inverter for guiding the drain of the transistor to the gate of the constant current transistor. In a sixth aspect, the differential amplifier is used in an input circuit of a DRAM. It is a feature.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

Another aspect of the method for adjusting the speed of a differential amplifier according to the present invention is to provide a differential amplifier in which a constant current source of a differential amplifier is constituted by a transistor, wherein a plurality of transistors for the constant current are provided and the plurality of transistors for the constant current are provided. Are connected in parallel, and a selection circuit for selecting a predetermined transistor from the plurality of transistors is provided.
Input a reset signal and turn on each transistor
, The predetermined transistor is selected, and the speed of the differential amplifier is adjusted. ────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 1, 1999 (1999.11.
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object. That is, a first aspect of the differential amplifier according to the present invention is a differential amplifier in which a constant current source of the differential amplifier is configured by a transistor. In the differential amplifier, a plurality of transistors for the constant current are provided, and the plurality of transistors are connected in parallel. Connected circuit, first power supply and second power supply
Fuse circuit and switching transistor
And a switching circuit connected to one terminal.
Connected to the drain of the transistor, and the other terminal
Signal and output the gate of the switching transistor.
A NAND gate connected to the switching gate;
The drain of the transistor is connected to the transistor for the constant current.
Multiple selection circuits composed of inverters leading to gates
From now, the structure as each select a plurality of predetermined transistor from transistors in the selection circuit for constant current
And characterized in that the form has, or, second aspect,
The gate lengths of the plurality of transistors for constant current are formed to be different from each other.
Embodiment, the selection circuit, it is characterized in that provided on the respective transistors for said plurality of constant current, or the fourth aspect, the pre-Symbol differential amplifier, an input circuit of the DRAM It is characterized by being used for.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

Another aspect of the method for adjusting the speed of a differential amplifier according to the present invention is to provide a differential amplifier in which a constant current source of a differential amplifier is constituted by a transistor, wherein a plurality of transistors for the constant current are provided and the plurality of transistors for the constant current are provided. Of a first power supply and a second power supply
Fuse circuit and switching transistor provided between
And a switching transistor connected to one terminal.
Connected to the drain of the
Input and output to the gate of the switching transistor
A NAND gate connected to the
The drain of the transistor is connected to the gate of the constant current transistor.
From multiple selection circuits composed of inverters leading to
A predetermined transistor is selected from the plurality of constant current transistors by the selection circuit.
And inputting the reset signal to the selection circuit.
The constant current transistor was controlled to conduct.
Above, the predetermined transistor is selected by the selection circuit.
Thus, the speed of the differential amplifier is adjusted.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a differential amplifier according to the present invention. FIG. 1 is a circuit diagram of a specific example of a differential amplifier according to the present invention used for an input first stage circuit of a DRAM,
FIG. 1 shows a differential amplifier 1 in which a constant current source of a differential amplifier is constituted by a transistor, a plurality of the constant current transistors 2, 3, and 4 are provided, and the plurality of transistors 2, 3, and 4 are connected in parallel. And a predetermined transistor is selected from the plurality of transistors 2, 3, and 4 by a selection circuit 5, 5
a and 5b are shown as differential amplifiers, and the selection circuits 5, 5a and 5b are shown as differential amplifiers provided in respective transistors 2, 3, and 4. The selection circuit 5 includes a series circuit of a fuse circuit 8 and a switching transistor 9 provided between a first power supply 6 and a second power supply 7, and a drain of the switching transistor 9 connected to one terminal 11. A reset signal 13 is input to the other terminal 12 and an output 14 is connected to the gate of the switching transistor 9.
A differential amplifier including a gate 15 and an inverter 16 for guiding the drain of the switching transistor 9 to the gate of the constant current transistor 2 is shown.

Claims (7)

[Claims] 1. A differential amplifier comprising a transistor as a constant current source of a differential amplifier, wherein a plurality of said constant current transistors are provided, said plurality of transistors are connected in parallel, and a predetermined A differential amplifier characterized in that a transistor is selected by a selection circuit. 2. The differential amplifier according to claim 1, wherein the plurality of transistors have different gate lengths. 3. The differential amplifier according to claim 1, wherein the selection circuit is provided in each of the plurality of transistors. 4. The differential amplifier according to claim 1, wherein said selection circuit includes a fuse circuit. 5. A selection circuit comprising: a series circuit of a hood circuit and a switching transistor provided between a first power supply and a second power supply; and a drain of the switching transistor connected to one terminal and the other connected. A reset signal is input to a terminal, and an NAND gate for connecting an output to the gate of the switching transistor, and an inverter for guiding a drain of the switching transistor to a gate of the constant current transistor. Item 5. The differential amplifier according to any one of Items 1 to 4. 6. The differential amplifier according to claim 1, wherein the differential amplifier is used for an input circuit of a DRAM. 7. A differential amplifier in which a constant current source of a differential amplifier is constituted by a transistor, wherein a plurality of the transistors for the constant current are provided, and the plurality of transistors are connected in parallel. A method for adjusting the speed of a differential amplifier, comprising adjusting a speed of the differential amplifier by selecting a transistor.