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IT9048189A0 - "metodo per ridurre il rumore di accoppiamento su linee di parola in un dispositivo di memoria a smiconduttori" - Google Patents

"metodo per ridurre il rumore di accoppiamento su linee di parola in un dispositivo di memoria a smiconduttori"

Info

Publication number
IT9048189A0
IT9048189A0 IT9048189A IT4818990A IT9048189A0 IT 9048189 A0 IT9048189 A0 IT 9048189A0 IT 9048189 A IT9048189 A IT 9048189A IT 4818990 A IT4818990 A IT 4818990A IT 9048189 A0 IT9048189 A0 IT 9048189A0
Authority
IT
Italy
Prior art keywords
smicoconductor
memory device
coupling noise
reducing coupling
speech lines
Prior art date
Application number
IT9048189A
Other languages
English (en)
Other versions
IT1241524B (it
IT9048189A1 (it
Inventor
Dong-Sun Min
Su-In Cho
Dae-Je Jin
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of IT9048189A0 publication Critical patent/IT9048189A0/it
Publication of IT9048189A1 publication Critical patent/IT9048189A1/it
Application granted granted Critical
Publication of IT1241524B publication Critical patent/IT1241524B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • H10W20/495—
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H10W20/423—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT48189A 1989-12-29 1990-07-31 Metodo per ridurre il rumore di accoppiamento su linee di parola in undispositivo di memoria a semiconduttori IT1241524B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020102A KR930001737B1 (ko) 1989-12-29 1989-12-29 반도체 메모리 어레이의 워드라인 배열방법

Publications (3)

Publication Number Publication Date
IT9048189A0 true IT9048189A0 (it) 1990-07-31
IT9048189A1 IT9048189A1 (it) 1992-01-31
IT1241524B IT1241524B (it) 1994-01-17

Family

ID=19294143

Family Applications (1)

Application Number Title Priority Date Filing Date
IT48189A IT1241524B (it) 1989-12-29 1990-07-31 Metodo per ridurre il rumore di accoppiamento su linee di parola in undispositivo di memoria a semiconduttori

Country Status (9)

Country Link
US (1) US5155700A (it)
JP (1) JPH0783060B2 (it)
KR (1) KR930001737B1 (it)
CN (1) CN1021997C (it)
DE (1) DE4005992C2 (it)
FR (1) FR2656726B1 (it)
GB (1) GB2239556B (it)
IT (1) IT1241524B (it)
NL (1) NL194178C (it)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0713864B2 (ja) * 1989-09-27 1995-02-15 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
JPH03171662A (ja) * 1989-11-29 1991-07-25 Sharp Corp 信号線システム
JPH04271086A (ja) * 1991-02-27 1992-09-28 Nec Corp 半導体集積回路
US5297094A (en) * 1991-07-17 1994-03-22 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory device with redundant rows
US5311477A (en) * 1991-07-17 1994-05-10 Sgs-Thomson Microelectronics, Inc. Integrated circuit memory device having flash clear
US5287322A (en) * 1991-07-17 1994-02-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit dual-port memory device having reduced capacitance
JP2000340766A (ja) * 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
US6327170B1 (en) * 1999-09-28 2001-12-04 Infineon Technologies Ag Reducing impact of coupling noise in multi-level bitline architecture
US6567329B2 (en) * 2001-08-28 2003-05-20 Intel Corporation Multiple word-line accessing and accessor
US6563727B1 (en) * 2002-07-31 2003-05-13 Alan Roth Method and structure for reducing noise effects in content addressable memories
US7244995B2 (en) * 2004-10-18 2007-07-17 Texas Instruments Incorporated Scrambling method to reduce wordline coupling noise
US7952901B2 (en) * 2007-08-09 2011-05-31 Qualcomm Incorporated Content addressable memory
US20090154215A1 (en) * 2007-12-14 2009-06-18 Spansion Llc Reducing noise and disturbance between memory storage elements using angled wordlines
JP5612803B2 (ja) * 2007-12-25 2014-10-22 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
US8411479B2 (en) * 2009-07-23 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuits, systems, and methods for routing the memory circuits
CN113270130B (zh) * 2020-05-29 2024-08-09 台湾积体电路制造股份有限公司 存储器设备
US20250329371A1 (en) * 2024-04-22 2025-10-23 Micron Technology, Inc. Memory device using wordline drivers with crossing row outputs

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57208691A (en) * 1981-06-15 1982-12-21 Mitsubishi Electric Corp Semiconductor memory
JPS59124092A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd メモリ装置
US4729119A (en) * 1984-05-21 1988-03-01 General Computer Corporation Apparatus and methods for processing data through a random access memory system
US4733374A (en) * 1985-03-30 1988-03-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device
CA1305255C (en) * 1986-08-25 1992-07-14 Joseph Lebowitz Marching interconnecting lines in semiconductor integrated circuits
JPS63153792A (ja) * 1986-12-17 1988-06-27 Sharp Corp 半導体メモリ装置
JPH0713858B2 (ja) * 1988-08-30 1995-02-15 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JPH03203369A (ja) 1991-09-05
IT1241524B (it) 1994-01-17
DE4005992C2 (de) 1994-01-27
CN1052967A (zh) 1991-07-10
FR2656726B1 (fr) 1995-02-03
CN1021997C (zh) 1993-09-01
DE4005992A1 (de) 1991-07-11
GB2239556B (en) 1993-08-25
FR2656726A1 (fr) 1991-07-05
KR910013262A (ko) 1991-08-08
US5155700A (en) 1992-10-13
NL194178B (nl) 2001-04-02
IT9048189A1 (it) 1992-01-31
GB2239556A (en) 1991-07-03
JPH0783060B2 (ja) 1995-09-06
NL9000431A (nl) 1991-07-16
KR930001737B1 (ko) 1993-03-12
GB9004448D0 (en) 1990-04-25
NL194178C (nl) 2001-08-03

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970528