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IT1214805B - Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown - Google Patents

Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown

Info

Publication number
IT1214805B
IT1214805B IT8406616A IT661684A IT1214805B IT 1214805 B IT1214805 B IT 1214805B IT 8406616 A IT8406616 A IT 8406616A IT 661684 A IT661684 A IT 661684A IT 1214805 B IT1214805 B IT 1214805B
Authority
IT
Italy
Prior art keywords
junprocess
semiconductor
manufacture
devices
breakdown voltage
Prior art date
Application number
IT8406616A
Other languages
English (en)
Other versions
IT8406616A0 (it
Inventor
Ferla Giuseppe
Musumeci Salvatore
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8406616A priority Critical patent/IT1214805B/it
Publication of IT8406616A0 publication Critical patent/IT8406616A0/it
Priority to GB08518801A priority patent/GB2163597A/en
Priority to FR8512091A priority patent/FR2569495A1/fr
Priority to JP60181920A priority patent/JPH0793312B2/ja
Priority to US06/768,028 priority patent/US4667393A/en
Application granted granted Critical
Publication of IT1214805B publication Critical patent/IT1214805B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/965—Shaped junction formation
IT8406616A 1984-08-21 1984-08-21 Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown IT1214805B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8406616A IT1214805B (it) 1984-08-21 1984-08-21 Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown
GB08518801A GB2163597A (en) 1984-08-21 1985-07-25 Improvements in or relating to manufacture of semiconductor devices of high breakdown voltage
FR8512091A FR2569495A1 (fr) 1984-08-21 1985-08-07 Procede pour la fabrication de dispositifs a semi-conducteur comportant des jonctions planaires a concentration de charge variable et a tres haute tension de rupture
JP60181920A JPH0793312B2 (ja) 1984-08-21 1985-08-21 プレーナ接合を有する半導体装置の製造方法
US06/768,028 US4667393A (en) 1984-08-21 1985-08-21 Method for the manufacture of semiconductor devices with planar junctions having a variable charge concentration and a very high breakdown voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8406616A IT1214805B (it) 1984-08-21 1984-08-21 Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown

Publications (2)

Publication Number Publication Date
IT8406616A0 IT8406616A0 (it) 1984-08-21
IT1214805B true IT1214805B (it) 1990-01-18

Family

ID=11121466

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8406616A IT1214805B (it) 1984-08-21 1984-08-21 Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown

Country Status (5)

Country Link
US (1) US4667393A (it)
JP (1) JPH0793312B2 (it)
FR (1) FR2569495A1 (it)
GB (1) GB2163597A (it)
IT (1) IT1214805B (it)

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EP0632503B1 (en) * 1993-07-01 2001-10-31 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Integrated edge structure for high voltage semiconductor devices and related manufacturing process
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US5869371A (en) * 1995-06-07 1999-02-09 Stmicroelectronics, Inc. Structure and process for reducing the on-resistance of mos-gated power devices
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US6215168B1 (en) * 1999-07-21 2001-04-10 Intersil Corporation Doubly graded junction termination extension for edge passivation of semiconductor devices
JP4785335B2 (ja) * 2001-02-21 2011-10-05 三菱電機株式会社 半導体装置およびその製造方法
US7033950B2 (en) * 2001-12-19 2006-04-25 Auburn University Graded junction termination extensions for electronic devices
EP1635397A1 (en) * 2004-09-14 2006-03-15 STMicroelectronics S.r.l. Integrated high voltage power device having an edge termination of enhanced effectiveness
DE102005004355B4 (de) * 2005-01-31 2008-12-18 Infineon Technologies Ag Halbleitereinrichtung und Verfahren zu deren Herstellung
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US20220157951A1 (en) 2020-11-17 2022-05-19 Hamza Yilmaz High voltage edge termination structure for power semicondcutor devices and manufacturing method thereof
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Also Published As

Publication number Publication date
GB8518801D0 (en) 1985-08-29
JPH0793312B2 (ja) 1995-10-09
US4667393A (en) 1987-05-26
FR2569495A1 (fr) 1986-02-28
IT8406616A0 (it) 1984-08-21
JPS6159868A (ja) 1986-03-27
GB2163597A (en) 1986-02-26

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970829