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IT1122415B - Circuito stampato a piu'strati e procedimento per la sua progettazione - Google Patents

Circuito stampato a piu'strati e procedimento per la sua progettazione

Info

Publication number
IT1122415B
IT1122415B IT24908/79A IT2490879A IT1122415B IT 1122415 B IT1122415 B IT 1122415B IT 24908/79 A IT24908/79 A IT 24908/79A IT 2490879 A IT2490879 A IT 2490879A IT 1122415 B IT1122415 B IT 1122415B
Authority
IT
Italy
Prior art keywords
procedure
design
printed circuit
layer printed
layer
Prior art date
Application number
IT24908/79A
Other languages
English (en)
Other versions
IT7924908A0 (it
Original Assignee
Contraves Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Contraves Ag filed Critical Contraves Ag
Publication of IT7924908A0 publication Critical patent/IT7924908A0/it
Application granted granted Critical
Publication of IT1122415B publication Critical patent/IT1122415B/it

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0287Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09454Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09609Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681Mesh conductors, e.g. as a ground plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09945Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4641Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
IT24908/79A 1978-08-07 1979-08-03 Circuito stampato a piu'strati e procedimento per la sua progettazione IT1122415B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH837178A CH630211A5 (en) 1978-08-07 1978-08-07 Method for designing electrically conductive layers for producing printed circuits, as well as a multilayer base material for carrying out the method

Publications (2)

Publication Number Publication Date
IT7924908A0 IT7924908A0 (it) 1979-08-03
IT1122415B true IT1122415B (it) 1986-04-23

Family

ID=4339288

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24908/79A IT1122415B (it) 1978-08-07 1979-08-03 Circuito stampato a piu'strati e procedimento per la sua progettazione

Country Status (5)

Country Link
BE (1) BE877835A (it)
CH (1) CH630211A5 (it)
DE (2) DE7920553U1 (it)
IT (1) IT1122415B (it)
LU (1) LU81559A1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3020196C2 (de) * 1980-05-28 1982-05-06 Ruwel-Werke Spezialfabrik für Leiterplatten GmbH, 4170 Geldern Mehrebenen-Leiterplatte und Verfahren zu deren Herstellung
FR2512315A1 (fr) * 1981-09-02 1983-03-04 Rouge Francois Ebauche de circuit electrique multicouche et procede de fabrication de circuits multicouches en comportant application

Also Published As

Publication number Publication date
DE2929051A1 (de) 1980-02-21
LU81559A1 (de) 1979-10-31
BE877835A (fr) 1979-11-16
CH630211A5 (en) 1982-05-28
DE7920553U1 (de) 1979-10-11
IT7924908A0 (it) 1979-08-03

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