HK1232683B - Network with integrated passive device and conductive trace in packaging substrate and related modules and devices - Google Patents

Description

Networks, related modules and devices having integrated passive components and conductive traces

Technical Field

The present disclosure relates to electronic systems, and in particular, to electronic systems including passive impedance elements.

Background Art

The physical size of components in mobile phones and other mobile devices is decreasing. Physical implementation of circuit designs and methods can facilitate the reduction in size of such components.

Many mobile devices include a power amplifier module as a component. The power amplifier module typically includes one or more power amplifiers and one or more associated matching networks. The matching network can provide impedance matching and one or more other functions, such as harmonic frequency suppression, filtering, impedance rotation, etc. The matching network can include passive impedance elements implemented on the power amplifier die, as one or more surface mount components on a packaging substrate, on a die including integrated passive devices, or any combination thereof. The passive impedance elements can include one or more transformers, one or more coils, one or more capacitors, one or more inductors, etc., or any combination thereof.

Summary of the Invention

The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some of the notable features of the disclosure will now be described briefly.

One aspect of the present disclosure is a device comprising a package substrate, a die on the package substrate, and conductive traces of the package substrate. The die includes integrated passive devices and contacts that provide electrical connections to the integrated passive devices. The conductive traces are in an electrical path between the contacts of the die and a ground potential.

The conductive trace may be included in a matching network configured to provide impedance matching and suppress harmonics of a radio frequency signal received by the matching network. The length of the conductive trace, together with the capacitance of the integrated passive device, may suppress the harmonics of the radio frequency signal.

The conductive trace may have a length greater than the maximum dimension of the wafer. The conductive trace may have a length of at least 50 micrometers. The conductive trace may have a length of at least 100 micrometers. The conductive trace may be substantially spiral in plan view. The conductive trace may comprise copper.

The device may also include a power amplifier die on the package substrate. The power amplifier die may include a power amplifier configured to provide a radio frequency signal to a matching network including integrated passive components and conductive traces.

The package substrate may be a laminate substrate. The wafer may be a silicon wafer. For example, the wafer may be a silicon wafer and integrated passive devices may be formed using a thin film process. The contacts of the wafer may be bump pads, and the wafer may be a flip-chip mounted on the package substrate. At least a portion of the conductive trace may be disposed below the wafer's footprint.

The integrated passive device may be a capacitor.The apparatus may further include a second conductive trace of the package substrate, the integrated passive device may include a first integrated capacitor, and the die may further include a second integrated capacitor arranged in series with the second conductive trace.

Another aspect of the present disclosure is a device comprising a first die on a laminate substrate, a second die on the laminate substrate, and a conductive trace on the laminate substrate. The first die includes a power amplifier configured to receive a radio frequency (RF) input signal and provide an amplified RF signal. The second die is configured to receive the amplified RF signal. The second die includes an integrated passive device. The conductive trace is an electrical path between the integrated passive device and a ground potential.

The conductive trace may be substantially spiral-shaped in plan view. The length of the conductive trace, together with the capacitance of the integrated passive component, may suppress harmonics of the amplified RF signal. The integrated passive component and the conductive trace may be included in a matching network configured to provide impedance transformation and an L-C filter, such as an elliptical filter, wherein the matching network is configured to receive the amplified RF signal. The integrated passive component and the conductive trace may be included in a matching network configured to provide impedance matching and phase rotation, wherein the matching network is configured to receive the amplified RF signal.

Another aspect of the present disclosure is a mobile device comprising a multi-chip module, an antenna, and a battery. The multi-chip module comprises a power amplifier die on a laminate substrate, an integrated passive device (IPD) die on the laminate substrate, and conductive traces of the laminate substrate. The power amplifier die includes a power amplifier configured to receive a radio frequency (RF) input signal and provide an amplified RF signal. The IPD die includes an integrated capacitor and is configured to receive the amplified RF signal. The conductive trace is connected in series between the integrated capacitor and a ground potential. The antenna is configured to receive a processed version of the amplified RF signal from the IPD die. The battery is configured to provide a supply voltage to the multi-chip module.

The mobile device may be a cellular phone in which the multi-chip module is a multi-band module.

For the purposes of summarizing the present disclosure, certain aspects, advantages, and novel features of the present invention have been described herein. It will be understood that it is not necessary to realize all of these advantages according to any particular embodiment of the present invention. Thus, the present invention can be performed or performed in a manner that realizes or optimizes an advantage or a group of advantages as taught herein without necessarily realizing other advantages that may be taught or proposed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure will now be described, by way of non-limiting examples, with reference to the accompanying drawings.

FIG1 is a schematic diagram of a power amplifier system including a power amplifier and a matching network.

2A is a schematic diagram of a multi-chip module including the power amplifier and matching network of FIG. 1 , according to an embodiment.

2B is a plan view of conductive traces in the package substrate of the multi-chip module of FIG. 2A according to an embodiment.

FIG. 2C is a flowchart of a method for manufacturing a multi-chip module according to an embodiment.

2D is a schematic diagram of a module including the matching network of FIG. 1 , according to an embodiment.

3 is a schematic diagram of an integrated passive device (IPD) die and traces in a package substrate configured to provide impedance matching and harmonic rejection according to an embodiment.

4 is a graph of the frequency response of a matching network including an IPD die with a bump directly connected to a via that provides a path to radio frequency (RF) ground.

FIG. 5 is a graph of the frequency response of a matching network including an IPD die arranged according to FIG. 3 .

6A is a schematic diagram of a power amplifier system including a matching network comprising integrated passive devices and conductive traces in a package substrate, according to an embodiment.

6B is a plot illustrating the frequency response of the elliptical filter of FIG. 6A .

7 is a schematic diagram of an IPD die and traces in a package substrate configured to provide impedance matching and phase rotation according to an embodiment.

FIG. 8 is a Smith chart illustrating impedance rotation achieved by the matching network of FIG. 7 .

9 is a schematic block diagram of an example mobile device including one or more matching networks according to any of the embodiments of FIG. 1 , 2A-2B, 2D, 3 , 6A and/or 7 .

DETAILED DESCRIPTION

The following detailed description presents various descriptions of specific embodiments. However, the innovations described herein may be embodied in a wide variety of ways, such as those defined and covered by the claims. In this description, reference is made to the accompanying drawings, in which like reference numerals may indicate identical or functionally similar elements. It will be understood that the elements illustrated in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that certain embodiments may include more elements than illustrated in the drawings and/or a subset of the elements illustrated in the drawings. In addition, certain embodiments may incorporate any suitable combination of features from two or more of the drawings.

Multi-band front-end modules for mobile phone applications are becoming increasingly miniaturized. Therefore, it may be beneficial to perform multiple electrical functions with a single circuit. For example, an impedance matching circuit or filter may include one or more transformers, one or more capacitors, one or more inductors, etc., or any combination thereof. These circuit elements are typically implemented using a multilayer structure. Examples of such circuit elements are manufactured in or on organic layers with electrolytically deposited copper paths and traces. Other examples of these circuit elements include integrated passive devices (IPDs), which can be manufactured on silicon wafers using thin film processes.

Combined electrical functions, such as impedance matching and harmonic suppression, can be achieved by a matching network. For example, in a power amplifier module, it may be desirable to match the relatively low impedance of the power amplifier die to a standard impedance (such as 50 ohms) within the operating frequency band, and at the same time suppress one or more harmonics that may accompany the output of the power amplifier. Such an impedance matching circuit may include a capacitor connected to a radio frequency (RF) ground in a shunt manner. An inductor of appropriate value may be included between one terminal of the capacitor and the RF ground. The series-connected circuit may be configured to resonate and create a short circuit at a frequency determined by the inductance value of the inductor and the capacitance value of the capacitor, thereby suppressing the transmission of signals at that frequency. Such a frequency may be referred to as a notch frequency and is typically one of the harmonics of the fundamental frequency response.

The value of one or more capacitors in the matching network can be set by the characteristics of the matching circuit (typically the impedance transformation ratio). Therefore, the notch frequency can typically be adjusted by selecting the inductor value instead of adjusting the capacitance in the LC shunt circuit. In relatively low frequency bands (such as the band centered around 700 MHz, the band centered around 800 MHz, the band centered around 900 MHz, the Long Term Evolution Band 13, the Long Term Evolution Band 5, etc.), the inductor value may become sufficiently large that it becomes difficult to effectively implement the inductor using traditional integration methods. This problem may make it difficult to implement a miniaturized front-end module, especially when supporting communications in multiple frequency bands.

Certain previous integration approaches involving LC circuits in all-organic layered circuits have encountered geometric limitations imposed by the layered manufacturing process, which may limit the maximum impedance ratio. Surface mount technology components can consume a relatively large surface area, which may make miniaturization difficult. In addition, implementing harmonic notching on the power amplifier die may result in inductors with relatively low Q, such that in-band loss penalties may occur (e.g., particularly for second harmonic notching) and/or maximum harmonic suppression may be insufficient. Previous integrated passive device (IPD) approaches have provided little or no harmonic suppression.

An impedance matching transformer fabricated on an IPD die can be arranged to connect the RF output of a power amplifier (PA) die, which can have a relatively low impedance (e.g., approximately 2 ohms to 5 ohms) for optimal performance, to a relatively high impedance (e.g., 50 ohms). In some cases, the IPD die is a flip-chip bonded to an underlying layer. While such a circuit can achieve the required in-band performance, out-of-band rejection can often be poor, with little or no notch rejection indicated at the second and third harmonics.

Generally speaking, aspects of the present disclosure relate to integrated passive devices on an IPD die electrically connected to conductive traces of a packaging substrate on which the IPD die is placed. For example, the IPD die can be a flip-chip mounted on a layered packaging substrate. The conductive traces can be included in an electrical path between contacts of the integrated passive device, such as bump pads, and a ground potential, such as a ground plane. The electrical path can also include one or more paths provided between the conductive traces and the ground potential. The integrated passive device can be an IPD capacitor electrically connected to the conductive traces. The length of the conductive traces can achieve an inductive impedance. The impedance of the IPD capacitor, together with the impedance of the conductive traces, can achieve various functions in a matching network, such as harmonic rejection, filtering, impedance rotation, etc., or any combination thereof. The matching network can be electrically connected to the output of a power amplifier.

In an embodiment, one or more IPD capacitors are connected to ground by means of transmission line traces having non-zero lengths implemented in a layered structure. The impedance and length of each trace can be selected so that each IPD capacitor resonates at a desired harmonic frequency. The resulting resonance can provide a notched harmonic response and a transmission zero that shunts it to ground. Two or more shunt IPD capacitors can be fabricated on the same IPD die, and each of these IPD capacitors can resonate at a separate frequency. As an example, one IPD capacitor on an IPD die can resonate at a second harmonic frequency, and another IPD capacitor on the same IPD die can resonate at a third harmonic frequency. As another example, one IPD capacitor on an IPD die can resonate at a third harmonic frequency, and another IPD capacitor on the same IPD die can resonate at a fourth harmonic frequency. More generally, different IPD capacitors on an IPD die can resonate at different desired frequencies by including appropriately configured traces in the layered structure on which the IPD die is disposed.

In another embodiment, several IPD capacitors can resonate similarly to the layered traces at frequencies in the rejection band (e.g., frequencies above the normal passband). These IPD capacitors can be appropriately coupled using the residual inductance of the IPD transformer secondary winding and, in some cases, the stray capacitance between the turns of the winding, to create, for example, an elliptical filter. Because elliptical filters exhibit a balanced ripple (equiripple) response in both the passband and the stopband, this type of filter can provide rejection relatively close to and around the resonant frequency to create a stopband that can suppress any unwanted signals that may be present. Ellipticals are therefore a good option for providing harmonic frequency notching while also providing relatively low insertion loss in the passband.

In another embodiment, the IPD and traces in the layer can together provide impedance rotation. The transmit port impedance of a surface acoustic wave (SAW) duplexer or a bulk acoustic wave (BAW) duplexer can be such that the magnitude of the resistive portion at the edge of the band is maximized. When this impedance is matched to a power amplifier collector electrically coupled to a matching network including an IPD, efficiency is reduced at the band edge relative to the band center. By including a design with relatively long traces in the supporting layer, the SAW duplexer impedance and/or the BAW duplexer impedance can be rotated in the Smith chart. Thus, the matching impedance presented to the power amplifier collector can be rotated so that the magnitude of the resistive portion at the band edge is minimized or close to minimized. Power efficiency can therefore be improved at the band edge relative to the band center by this impedance rotation.

Particular implementations of the subject matter described in this disclosure can be implemented to obtain one or more of the following potential advantages. The IPD and traces of the packaging substrate (e.g., a laminate substrate) on which the die including the IPD is disposed can reject one or more harmonics and/or other spurious signals from appearing at the power amplifier RF output. One or more selective functions can be combined with impedance matching functions in the same IPD die by implementing one or more conductive traces in physical areas that are normally available but typically unused in the layering under the flip-chip mounted IPD die. This can provide a more compact component. For example, by means of phase rotation, the impedance of the external component can be adjusted before being applied to the power amplifier collector.

Referring to FIG1 , a schematic diagram of a power amplifier system including a power amplifier and a matching network will be described. As shown, power amplifier system 10 includes a power amplifier 12 and a matching network 14. Power amplifier 12 is configured to amplify an RF signal RF_IN and provide an amplified RF signal PA_OUT. The RF signal may have a frequency in the range of approximately 30 kHz to 300 GHz, such as in the range of approximately 450 MHz to approximately 4 GHz for radio frequency signals in long-term evolution systems. Power amplifier 12 may be any suitable RF power amplifier. For example, power amplifier 12 may be one or more single-stage power amplifiers, a multi-stage power amplifier, a power amplifier implemented by one or more bipolar transistors, or a power amplifier implemented by one or more field-effect transistors.

The matching network 14 can help reduce signal reflections and/or other signal distortions. The matching network 14 can include one or more capacitors and one or more inductors. The matching network 14 can include one or more shunt capacitors, shunt inductors, shunt series LC circuits, or parallel LC circuits in the signal path between the power amplifier 12 and the output RF_OUT of the matching network 14. The matching network 14 can include an IPD capacitor on an IPD die and conductive traces in a layer on which the IPD die is placed. In some implementations, a portion of the matching network 14 can be implemented on the power amplifier die that includes the power amplifier 10. The output RF_OUT of the matching network 14 can be provided to an antenna via, for example, a switch module. For example, the output RF_OUT can be provided to a duplexer in the switch module, such as a SAW duplexer or a BAW duplexer, and a processed version of the output RF_OUT can be provided to the antenna.

FIG2A is a schematic diagram of a multi-chip module 20 according to an embodiment. The multi-chip module 20 may include a power amplifier die and an IPD die packaged together within a package. When the multi-chip module includes a power amplifier die, the multi-chip module may be referred to as a power amplifier module. The illustrated multi-chip module 20 includes a power amplifier die 22 and an IPD die 24, wire bonds 25, a laminate substrate 26, conductive traces 27, vias 28, and a ground plane 29. Although FIG2A and other embodiments may be discussed with respect to a laminate substrate for illustrative purposes, the conductive traces may be implemented in other suitable packaging substrates according to the principles and advantages discussed herein. As an example, in some implementations, the conductive traces may be implemented in a ceramic packaging substrate.

As shown, the power amplifier die 22 is in electrical communication with the IPD die 24 by means of wire bonds 25. The wire bonds 25 can provide inductance between the power amplifier die 22 and the IPD die 24. More than one wire bond 25 can electrically connect the power amplifier die 22 and the IPD die 24. Such wire bonds can be arranged in parallel with each other. Other appropriate electrical connections can electrically connect the output of the power amplifier of the power amplifier die 22 to the IPD die 24. The power amplifier die 22 can include any power amplifier discussed herein. In some implementations, for harmonics, such as the second harmonic and/or the fourth harmonic, the power amplifier die 22 can include at least a portion of one or more end circuits (such as an LC shunt circuit). In some implementations, the power amplifier die 22 can be a GaAs die, a CMOS die, or a SiGe die.

The IPD wafer 24 may include any IPD discussed herein. As used herein, an "IPD wafer" may refer to any suitable wafer including one or more IPDs. The IPD wafer 24 may be a silicon wafer or a wafer of any other suitable insulating material. In some such implementations, one or more IPDs may be formed using a thin film process. The IPD wafer 24 may be a flip chip mounted on a layered substrate 26 as shown in FIG2A . In other embodiments, the IPD wafer 24 may be coupled to a laminate substrate 26 in other ways. Conductive traces 27 in the laminate substrate 26 may provide inductive impedance. When the IPD wafer 24 is a flip chip mounted on a laminate substrate 26, bumps (e.g., solder bumps or copper pillars) may electrically connect the IPD wafer 24 to the conductive traces 27. The IPD wafer 24 may include bump pads to provide electrical connections for the IPD, and the bump pads may be in physical and electrical contact with the bumps.

In some implementations, the power amplifier of power amplifier die 22 may generate a radio frequency signal having a frequency ranging from approximately 500 MHz to approximately 1 GHz (e.g., from approximately 700 MHz to approximately 900 MHz). In such implementations, the inductance of the LC shunt circuit in the matching network may be sufficiently large that it becomes difficult to effectively implement the inductor of the LC shunt circuit. Therefore, implementing an inductive component is beneficial for implementing conductive traces 27 in laminate substrate 26.

Conductive trace 27 can be implemented, for example, from copper. Conductive trace 27 can extend in a direction substantially parallel to IPD die 24. Conductive trace 27 can have a length greater than the longest dimension of IPD die 24. In certain applications, conductive trace 27 can have a length of at least 50 microns. Depending on some of these applications, conductive trace 27 can have a length of at least 100 microns. The length of conductive trace 27 need not be straight, and turns and/or bends in conductive trace 27 can be considered. In certain applications, conductive trace 27 can have a spiral shape in plan view. Conductive trace 27 can be electrically connected to RF ground 29 in laminate substrate 26 by way of via 28. Therefore, conductive trace 27 can be referred to as a ground trace.

FIG2B is a plan view of an example conductive trace 27 in the laminate substrate 26 of the multi-chip module 20 of FIG2A . As shown in FIG2B , the conductive trace 27 is substantially spiral-shaped when viewed in plan. At least a portion of the conductive trace 27 may be disposed below the footprint of the IPD die 24 . For example, a majority of the conductive trace 27 may be disposed below the footprint of the IPD die 24 . While one conductive trace 27 is shown for illustrative purposes, it will be understood that two or more such conductive traces may be included in certain other embodiments. As an example, the embodiment shown in FIG3 includes four conductive traces 27 a through 27 d in the laminate substrate 26 . As another example, conductive traces in different layers of the laminate substrate 26 may be at least partially stacked on top of one another. Furthermore, other conductive traces (not shown) may be included in the laminate substrate 26 for purposes other than providing a ground connection to the IPD on the IPD die 24 .

FIG2C is a flow chart of a method 30 for manufacturing a multi-chip module according to an embodiment. Multi-chip module 20 can be manufactured according to method 30. At block 32, a laminate substrate having conductive traces in a layered structure can be provided. In some cases, method 30 can include forming such a laminate substrate. At block 34, a die including one or more integrated passive devices can be flip-chip mounted on the laminate substrate. Thus, the devices of the die can be on a side facing the laminate substrate. One or more bumps can electrically connect the integrated passive devices of the die to the conductive traces in the layered structure. At block 36, the output of the power amplifier die on the laminate substrate can be wire-bonded to the input of the die including the integrated passive devices. This can provide an electrical path for the RF signal between the power amplifier and the matching network. In certain embodiments, some or all of the operations discussed with reference to FIG2C can be performed. The actions of any method discussed herein can be performed in any order as desired. Furthermore, the actions of any method discussed herein can be performed serially or in parallel as desired. Furthermore, any method discussed herein can be performed in connection with the manufacture of any device discussed herein.

FIG2D is a schematic diagram of a module 20′ according to an embodiment. Module 20′ is similar to the multi-chip module 20 of FIG2A . Any combination of features of the embodiment of FIG2D may be implemented with respect to the embodiment of FIG2A or any other embodiment discussed herein. While FIG2D focuses on illustrating an IPD die 24 and the associated electrical connection to RF ground, module 20′ may also include a power amplifier die and/or one or more other dies. FIG2D illustrates that conductive trace 27 may be electrically connected to IPD die 24 via a first via 28-1 embedded in laminate substrate 26. In FIG2D , a shunt capacitor on IPD die 24 may be electrically connected to RF ground via trace 27 embedded in substrate 26, a bump, a first via 28-1, and a second via 28-2. In certain other embodiments, two or more vias in the same layer of the substrate and/or two or more vias in different layers of the substrate may be included in the electrical path between trace 27 and RF ground. Alternatively or additionally, two or more vias in the same layer of the substrate and/or two or more vias in different layers of the substrate may be included in the electrical path between trace 27 and IPD die 24 .

FIG3 is a schematic diagram of an IPD die and traces in a layered configuration for providing impedance matching and harmonic rejection, according to an embodiment. The IPD die 24′ of FIG3 is an example of the IPD die 24 of FIG2A . In FIG3 , the IPD die 24′ includes IPD capacitors C _VCC , Cmatch, C2foB, Cfilt1, Cfilt2, and Cblock, and IPD inductors Pri and Sec. The IPD capacitors and/or IPD inductors can be formed, for example, using a thin film process on a silicon die or a die of any other suitable insulating material. The IPD capacitors and IPD inductors of the IPD die 24′ can be included in the matching network 14 of FIG1 . As shown, the IPD die 24′ can receive the power amplifier output signal PA_OUT and provide an RF output RF_OUT.

Instead of directly connecting the IPD capacitors to the bumps of the vias in the laminate substrate, the IPD shunt capacitors C2foB, Cfilt1, Cfilt2, and C _VCC of IPD die 24' are each connected to ground via conductive traces 27a through 27d in the laminate substrate. In the embodiment of FIG3 , conductive traces 27a through 27d are sequentially connected to the vias in the laminate substrate. In FIG3 , the IPD shunt capacitors are connected to conductive traces, such as copper traces, in the laminate substrate via individual bumps. Thus, each IPD shunt capacitor is electrically connected to the RF ground via the bumps, the conductive traces, and the vias. In certain implementations, one or more IPD shunt capacitors can be electrically connected to the RF ground, for example, via the bumps, the vias, the embedded traces, and another via, as shown in FIG2D . For a module including a power amplifier die and an IPD die, the RF ground can be implemented by a ground plane. In the embodiment of FIG. 3 , the electrical connections between the shunt capacitors and the conductive traces may be made by bumps, and the contacts of the die to Gnd1 , Gnd2 , Gnd3 , and Gnd4 may be made by bump pads.

Conductive traces 27a through 27d act as inductors between the respective IPD capacitors and the RF ground. Conductive traces 27a through 27d can each have a length selected to resonate with the respective IPD shunt capacitor electrically connected thereto. The lengths of conductive traces 27a through 27e can be selected so that the impedance of the conductive traces, together with the impedance of the IPD shunt capacitors electrically connected thereto, provides a frequency notch at a specific frequency (e.g., a harmonic frequency). Thus, the lengths of the conductive traces can be selected to provide rejection at a specific harmonic frequency. As an example, the capacitance of capacitor C2foB and the impedance of conductive trace 27a can be selected to provide harmonic rejection at the second harmonic frequency of the power amplifier's output. The capacitance of capacitor C2foB can be selected based on characteristics of the matching circuit (e.g., an impedance transformation ratio), and the length of conductive trace 27a can be selected based on the capacitance of capacitor C2foB to provide harmonic rejection at the second harmonic.

Figure 4 is a graph of the frequency response of a matching network including an IPD die having bumps directly connected to vias providing an electrical path to RF ground. As shown in the frequency response of Figure 4, without a conductive ground trace in the layer to resonate the shunt capacitor on the IPD die, no harmonic rejection is exhibited and out-of-band suppression is relatively poor.

By adding ground traces in layers of appropriate length to resonate the shunt capacitors on the IPD die (e.g., as shown in FIG3 ), desired harmonic rejection can be achieved. FIG5 is a graph of the frequency response of a matching network including an IPD die arranged according to FIG3 . As shown in FIG5 , third harmonic rejection of greater than 35 dB has been demonstrated.

Referring again to FIG3 , the IPD die 24 ′ and conductive traces in the laminate substrate can implement an impedance transformer with an elliptical low-pass filter response. As shown, capacitors Cfilt1 and Cfilt2, inductors Pri and Sec, and conductive traces 27 b and 27 _c can together implement this elliptical low-pass filter frequency response. The second inductor Sec of the transformer, implemented with approximately 3 ^1/2 turns, can have a residual inductance of approximately 7 nH. This inductor can be applied as a series element in a three-stage elliptical filter. The series inductance in this transformer can improve out-of-band suppression and provide a frequency notch at the third harmonic (for example, at approximately 2.7 GHz in some implementations). The notch frequency can be set by the tank capacitance of the LC tank of the tuning network. At certain frequencies, such as around the third harmonic, the inter-turn capacitance may be sufficient.

FIG6A is a schematic diagram of a power amplifier system including a matching network comprising integrated passives and conductive traces in a package substrate according to an embodiment. The illustrated power amplifier system includes power amplifier die 22′ and IPD die 24″, wire bonds 25a to 25n, and conductive traces 27b, 27c, and 27d. Power amplifier die 22′ of FIG6A is an example of power amplifier die 22 of FIG2A . IPD die 24″ of FIG6A is another example of IPD die 24 of FIG2A .

The matching network illustrated in FIG6A can implement an L-C filter such as a low-pass elliptical filter. The elliptical filter response can be implemented using shunt IPD capacitors on the IPD die 24″ and conductive traces 27b and 27c in the laminate substrate. Resonating the IPD shunt capacitors Cfilt1 and Cfilt2 with sufficiently long conductive traces 27b and 27c, respectively, can provide the desired performance of the elliptical filter response. To resonate the IPD shunt capacitors, the conductive traces may be too long to be included on the IPD die 24″. Therefore, conductive traces 27b and 27c are implemented in the laminate substrate 26 on which the IPD die 24″ is disposed. Conductive traces 27b and 27c can each have a length greater than 100 microns. For example, in some applications, conductive traces 27b and 27c can each have a length of approximately 300 microns. In some applications, the width of the conductive traces can be approximately 60 microns.

As shown, the power amplifier die 22' includes an input capacitor Cin, a bipolar power amplifier transistor 60, a first frequency notch 62, and a second frequency notch 64. FIG6A illustrates that the power amplifier die may include one or more harmonic notches. For example, the first frequency notch 62 may be a second harmonic notch, and the second frequency notch 64 may be a fourth harmonic notch. FIG6A also illustrates that the power amplifier may include a bipolar power amplifier transistor 60. The bipolar power amplifier transistor 60 may be a GaAs heterojunction bipolar transistor. The base of the bipolar power amplifier transistor 60 may receive an RF input signal RF_IN via the input capacitor Cin. The base may also receive a bias signal (not shown), such as a bias voltage. The collector of the bipolar power amplifier transistor 60 may provide a power amplifier output signal PA_OUT. As shown, wire bonds 25a to 25n provide the power amplifier output signal PA_OUT from the power amplifier die 22' to the IPD die 24". Any suitable number of wire bonds 25a to 25n may be implemented in parallel with one another. These wire bonds may provide inductance in the signal path between the collector of the bipolar power amplifier 60 and the IPD die 24".

FIG6B is a plot illustrating the frequency response of the elliptical filter of FIG6A . As illustrated in FIG6B , simulation data indicates that the elliptical filter implemented by the matching network of FIG6A can provide frequency suppression at the third harmonic (approximately 2.7 GHz in the plot) and can be such that there is less than approximately −70 dB of power at the third harmonic, such as no more than approximately −74 dB of power at the third harmonic. The illustrated frequency response can provide the desired out-of-band suppression.

Figure 7 is a schematic diagram of an IPD die and traces in a laminate substrate configured to provide impedance matching and phase rotation according to an embodiment. The IPD die 24'" of Figure 7 is another example of the IPD die 24 of Figure 2A. In Figure 7, the IPD die 24'" includes IPD capacitors _CVCC , Cfilt1, Cfilt2, and Cblock and IPD inductors Pri and Sec. The IPD capacitors and/or IPD inductors can be formed, for example, on a silicon wafer or a wafer of any other suitable insulating material using a thin film process. The IPD capacitors and IPD inductors of the IPD die 24'" can be included in the matching network 14 of Figure 1. As shown, the IPD die 24'" can receive a power amplifier output signal PA_OUT and provide an RF output RF_OUT. Harmonic termination can be implemented on the power amplifier die with respect to the embodiment of Figure 7.

A duplexer, such as a SAW duplexer or a BAW duplexer, may be included in the electrical path between the matching network and the antenna. The duplexer may receive the output RF_OUT of the matching network of the IPD included on the IPD die 24″′. The transmit port impedance of the duplexer may be configured such that the magnitude of the resistive portion at the band edge is close to maximum. When this impedance matches the output of a power amplifier (e.g., the collector of the power amplifier) electrically connected to the matching network, efficiency may be reduced at the band edge.

An impedance converter IPD die, such as IPD die 24'" of FIG. 7 , and conductive traces in a layer on which the IPD die is placed can be used to provide duplexer-to-collector matching in an electronic system having bipolar power amplifier transistors. Conductive traces 27b and 27c of FIG. 7 can provide inductance in an electrical path between the IPD shunt capacitors Cfilt1 and Cfilt2, respectively, of IPD die 24'" and RF ground. Using relatively long conductive traces in the supporting laminate substrate can rotate the impedance of the transmit port of the duplexer in the Smith chart. The length of the conductive trace can affect the inductance of the conductive trace. Therefore, the length of the conductive traces shown in FIG. 7 can be selected to achieve the desired impedance rotation.

Conductive traces 27b, 27c, and 27d can each have a length greater than 100 microns. For example, in some applications, conductive trace 27b can have a length of approximately 275 microns, and conductive trace 27c can each have a length of approximately 950 microns to achieve the desired impedance rotation. As an example, conductive trace 27d can have a length of approximately 2 millimeters. In some applications, the width of each of conductive traces 27b, 27c, and 27d can be approximately 60 microns.

FIG8 is a Smith chart illustrating the impedance rotation achieved by the matching network of FIG7 . The duplexer impedance can be matched and rotated by the matching network so that the magnitude of the resistive component at the band edge is at or near a minimum. FIG8 illustrates this impedance rotation. When the rotated impedance is presented to the collector of the bipolar power amplifier transistor providing the power amplifier output signal PA_OUT, the efficiency of the power amplifier system can be improved at the band edge.

FIG9 is a schematic block diagram of an example wireless or mobile device 90 that may include one or more power amplifiers and one or more matching networks. In one embodiment, the wireless device 90 may be a mobile phone, such as a smartphone. The wireless device 90 may include one or more matching networks 14a, 14b. For example, the matching network of the wireless device 90 may include any suitable combination of features of the matching networks of any of FIG1 , FIG2A-2B , FIG2D , FIG3 , FIG6A , or FIG7 . As another example, any power amplifier discussed herein may be included in the wireless device 90 of FIG9 .

The example wireless device 90 shown in FIG9 can represent a multi-band and/or multi-mode device such as a multi-band/multi-mode mobile phone. For example, the wireless device 90 can communicate according to Long Term Evolution (LTE). In this example, the wireless device can be configured to operate in one or more frequency bands defined by the LTE standard. The wireless device 90 can alternatively or additionally be configured to communicate according to one or more other communication standards, including but not limited to one or more of the Wi-Fi standard, the 3G standard, the 4G standard, or the Advanced LTE standard. The power amplifier system of the present disclosure can be implemented in a mobile device that implements any combination of the aforementioned example communication standards, for example.

As shown, wireless device 90 may include a switch module 91 , a transceiver 92 , an antenna 93 , power amplifiers 12 a and 12 b , a control component 94 , a computer-readable storage medium 95 , a processor 96 , and a battery 97 .

The transceiver 92 can generate RF signals for transmission via the antenna 93. In addition, the transceiver 92 can receive incoming RF signals from the antenna 93. It will be understood that various functions associated with the transmission and reception of RF signals can be implemented by one or more components collectively represented as the transceiver 92 in FIG. 9 . For example, a single component can be configured to provide both transmit and receive functions. In another example, the transmit and receive functions can be provided by separate components.

In FIG9 , one or more output signals from transceiver 92 are shown as being provided to antenna 93 via one or more transmission paths 98. In the example shown, different transmission paths 98 may represent output paths associated with different frequency bands (e.g., a high frequency band and a low frequency band) and/or different power outputs. Transmission paths 98 may be associated with different transmission modes. One of the illustrated transmission paths 98 may be active while, for example, one or more other transmission paths 98 are inactive. Other transmission paths 98 may be associated with different power modes (e.g., a high power mode and a low power mode) and/or paths associated with different transmission bands. Transmission paths 98 may include one or more power amplifiers 12 a and 12 b to help boost RF signals having relatively low power to higher powers suitable for transmission. Power amplifiers 12 a and 12 b may include the power amplifier 12 discussed above. Although FIG9 illustrates a configuration using two transmission paths 98, wireless device 90 may be adapted to include more or fewer transmission paths 98.

In FIG9 , one or more detected signals from antenna 93 are depicted as being provided to transceiver 92 via one or more receive paths 99. In the example shown, different receive paths 99 may represent paths associated with different signal modes and/or different receive frequency bands. While FIG9 illustrates a configuration using four receive paths 99, wireless device 90 may be adapted to include more or fewer receive paths 99.

To facilitate switching between receive and/or transmit paths, an antenna switch module 91 may be included and may be used to selectively electrically connect the antenna 93 to a selected transmit or receive path. Thus, the antenna switch module 91 may provide a number of switching functions associated with the operation of the wireless device 90. The antenna switch module 91 may include a multi-throw switch configured to provide functionality associated with, for example, switching between different frequency bands, switching between different modes, switching between transmit and receive modes, or any combination thereof.

9 illustrates that in certain embodiments, a control component 94 may be provided for controlling various control functions associated with the operation of the antenna switch module 91 and/or one or more other operating components. For example, the control component 94 may help provide control signals to the antenna switch module 91 to select a particular transmit or receive path.

In some embodiments, the processor 95 may be configured to facilitate implementation of various processes on the wireless device 90. The processor 95 may be, for example, a general-purpose processor or a special-purpose processor. In some implementations, the wireless device 90 may include a non-transitory computer-readable medium 96, such as a memory, that may store computer program instructions, which may be provided to and executed by the processor 90.

The battery 97 may be any suitable battery for use in the wireless device 90 including, for example, a lithium-ion battery. The battery may provide a supply voltage to a multi-chip module, such as a multi-chip module including one or more power amplifiers 12a/12b and/or one or more matching networks 14a/14b.

Certain embodiments described above provide examples of power amplifiers and/or mobile devices. However, the principles and advantages of the embodiments can be used in any other system or device that may benefit from any circuit described herein. The teachings herein can be applied to various power amplifier systems, including systems with multiple power amplifiers, such as multi-band and/or multi-mode power amplifier systems. The power amplifier transistors discussed herein can be, for example, gallium arsenide (GaAs), CMOS, or silicon germanium (SiGe) transistors. The power amplifiers discussed herein can be implemented by field effect transistors and/or bipolar transistors (such as heterojunction bipolar transistors).

Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronic products, parts of consumer electronic products, electronic test equipment, cellular communication infrastructure, such as base stations, and the like. Examples of electronic devices may include, but are not limited to, mobile phones, such as smartphones, telephones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, vehicle electronic systems, such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players, such as MP3 players, radios, camcorders, cameras, digital cameras, portable memory chips, washing machines, dryers, washer/dryers, copiers, fax machines, scanners, multi-function peripheral devices, watches, clocks, and the like. In addition, electronic devices may include semi-finished products.

Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprises," "comprising," "containing," "having," and the like are to be interpreted as inclusive, rather than exclusive or exhaustive; that is, in the sense of "including, but not limited to." The term "coupled," as generally used herein, means that two or more elements can be connected directly, or by way of one or more intermediate elements. Similarly, the term "connected," as generally used herein, means that two or more elements can be connected directly, or by way of one or more intermediate elements. In addition, the terms "herein," "above," "below," and terms of similar meaning, when used in this application, should refer to the application as a whole and not to any particular part of the application. Where the context permits, terms in the above specific embodiments that use the singular or plural may also include the plural or singular, respectively. When referring to a list of two or more items, the term "or" covers all of the following interpretations of the term: any item in the list, all items in the list, and any combination of items in the list.

Furthermore, conditional language used herein, such as, for example, "may," "could," "might," "might," "for example," "for instance," "such as," and the like, unless specifically stated otherwise or otherwise understood within the context of use, is generally intended to indicate that some embodiments include, while other embodiments do not include, certain features, elements, and/or states. Thus, such conditional language is generally not intended to imply that features, elements, and/or states are in any way required for one or more embodiments, or that one or more embodiments must include logic for determining, with or without author input or prompting, whether such features, elements, and/or states are included or to be performed in any particular embodiment.

Although certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms; in addition, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, although the blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and/or circuit topologies, and certain blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any appropriate combination of the elements and actions of the various embodiments described above may be combined to provide additional embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications that would fall within the scope and spirit of the present disclosure.

Claims (21)

1. A module with integrated passive components, the module comprising: Packaging substrate; A wafer on a package substrate, the wafer including an integrated capacitor, a transformer, a second integrated capacitor coupled to a terminal of the transformer configured to receive a power supply voltage, and contacts providing an electrical connection to the integrated capacitor; A conductive trace on a package substrate, the conductive trace being in an electrical path between a die contact and ground potential, the conductive trace, the transformer, and the integrated capacitor being included in a matching network configured to receive radio frequency signals, and the capacitance of the integrated capacitor and the inductance of the conductive trace being configured together to provide frequency notch filtering at harmonics of the radio frequency signal; and A second conductive trace on the packaging substrate, the second conductive trace being arranged in series with the second integrated capacitor. 2. The module of claim 1, wherein the packaging substrate comprises layers and the conductive traces are in the layers. 3. The module of claim 1 further includes a third conductive trace and a third integrated capacitor of the wafer, the third conductive trace and the third integrated capacitor of the wafer being configured together to provide another frequency notch at different harmonics of the radio frequency signal. 4. The module of claim 1, wherein the inductance of the conductive trace corresponds to the length of the conductive trace. 5. The module of claim 1, further comprising a power amplifier chip on the package substrate, the power amplifier chip including a power amplifier configured to provide radio frequency signals to the matching network. 6. The module of claim 1, wherein the contacts of the wafer are bump pads, and the wafer is a flip chip mounted on a package substrate. 7. The module of claim 6, wherein at least a portion of the conductive trace is disposed below the coverage area of the wafer. 8. The module of claim 1, wherein the conductive trace has a length of at least 100 micrometers. 9. The module of claim 1, wherein the conductive trace is substantially spiral in plan view. 10. The module of claim 1, wherein the wafer is a silicon wafer. 11. The module of claim 1, wherein the conductive trace comprises copper. 12. A module with integrated passive components, the module comprising: Packaging substrate; A wafer on a package substrate, the wafer including a transformer, a capacitor including an integrated capacitor, and contacts providing electrical connections to the integrated capacitor; A conductive trace comprising a conductive trace of a package substrate, a capacitor configured to resonate with the residual inductance of the conductive trace and the secondary coil of the transformer to create an elliptic filter, the conductive trace being in an electrical path between a die contact and ground potential, the capacitance of the integrated capacitor and the inductance of the conductive trace being configured together to provide frequency notch filtering at harmonics of the radio frequency signal, and the conductive trace, the transformer, and the integrated capacitor being contained in a matching network configured to receive the radio frequency signal. 13. The module of claim 12, wherein the conductive trace includes a second conductive trace of the package substrate and a third conductive trace of the package substrate, and the capacitor includes a second integrated capacitor connected in series with the second conductive trace and a third integrated capacitor connected in series with the third conductive trace. 14. The module of claim 12, wherein the capacitor includes a second integrated capacitor coupled to a terminal of the transformer configured to receive a power supply voltage. 15. A power amplifier system, comprising: A first wafer on a laminated substrate, the first wafer including a power amplifier configured to receive a radio frequency input signal and provide amplified radio frequency signal; A second chip on a laminated substrate, the second chip being configured to receive an amplified radio frequency signal, the second chip including an integrated capacitor, a transformer connected to the output of the power amplifier, and a second integrated capacitor coupled to the transformer and configured to receive a power supply voltage of the second chip; A conductive trace on a laminated substrate, the conductive trace being in an electrical path between the integrated capacitor and ground potential, the impedance of the conductive trace being configured to cause the integrated capacitor to resonate at a harmonic frequency of the amplified radio frequency signal; and A second conductive trace on a laminated substrate, the second conductive trace being arranged in series with the second integrated capacitor. 16. The power amplifier system of claim 15, wherein the conductive trace is substantially spiral in plan view. 17. The power amplifier system of claim 15, wherein the length of the conductive trace is at least 100 micrometers, and the impedance of the conductive trace corresponds to the length of the conductive trace. 18. The power amplifier system of claim 15, wherein the transformer, the integrated capacitor, and the conductive trace are included in a matching network configured to provide impedance transformation and elliptic filtering. 19. The power amplifier system of claim 15, further comprising a third conductive trace on a laminated substrate, the second wafer further comprising a third integrated capacitor, the inductance of the third conductive trace being configured to cause the third integrated capacitor to resonate at a different harmonic frequency of the radio frequency signal relative to the harmonic frequency of the radio frequency signal. 20. A mobile device, comprising: A multi-chip module comprising (i) a power amplifier chip on a laminated substrate, the power amplifier chip including a power amplifier configured to receive a radio frequency input signal and provide an amplified radio frequency signal; (ii) an integrated passive device chip on a laminated substrate, the integrated passive device chip including an integrated capacitor, a transformer configured to receive the amplified radio frequency signal, and a second integrated capacitor coupled to a power contact of the integrated passive device chip and coupled to the transformer; (iii) a conductive trace on the laminated substrate, the conductive trace being connected in series between the integrated capacitor and ground potential, the conductive trace and the integrated capacitor being configured together to provide a frequency notch at a harmonic of the amplified radio frequency signal; and (iv) a second conductive trace on the laminated substrate, the second conductive trace being connected in series with the second integrated capacitor; Antenna, configured to receive a processed version of an amplified radio frequency signal from an integrated passive device chip; and The battery is configured to supply power voltage to the multi-chip module. 21. The mobile device of claim 20, wherein the mobile device is a cellular phone and the multi-chip module is a multi-band module.