HK1195680B - Flip-chip linear power amplifier with high power added efficiency - Google Patents

Description

Flip chip linear power amplifier with high power added efficiency

Cross Reference to Related Applications

Priority of U.S. provisional application No.61/558,866 entitled "FLIP chip linear POWER amplifier with high POWER added efficiency (FLIP-CHIP LINEAR POWER AMPLIFIERWITH HIGH POWER ADDED EFFICIENCY)" filed 11.2011, which is expressly incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to a flip chip device with a radio frequency power amplifier having high power added efficiency.

Background

Flip chip is a generic term for devices having a semiconductor chip interconnected to mounting pads by, for example, solder bumps. The chip is typically flipped so that the integrated circuit side faces the mounting pads. Such a configuration may provide advantageous features such as compact size and no need for wire bond interconnections.

A Radio Frequency (RF) Power Amplifier (PA) is a wireless component that may be implemented in a flip-chip configuration. Desirable characteristics of such PAs typically include, among others, Power Added Efficiency (PAE) and linearity. A higher PAE may provide, for example, longer battery life in a wireless device, such as a mobile phone. In some cases, enhancing PAE may adversely affect linearity. Similarly, improving linearity can cause PAE to decrease.

Disclosure of Invention

In some implementations, the present disclosure relates to a flip chip device that includes a Radio Frequency (RF) signal path having a node driven by at least one circuit element formed on a flip chip wafer. The apparatus also includes a first termination circuit configured to match an impedance of a fundamental frequency of a signal at the node. The apparatus also includes a second termination circuit separate from the first termination circuit. The second termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of a signal at the node.

In some embodiments, the at least one circuit element may comprise a power amplifier. The node may be connected to either or both of the output of the power amplifier and the input of the power amplifier. In some embodiments, the harmonic frequency may comprise a second harmonic frequency of the signal. In some embodiments, the apparatus further comprises a base load line comprising the first termination circuit.

In some embodiments, at least a portion of the first termination circuit and at least a portion of the second termination circuit may be implemented on a flip chip package substrate. The signal path may be implemented on a flip chip die in communication with the flip chip package substrate. The signal path may be coupled to at least one of the first termination circuit and the second termination circuit via one or more conductor traces formed on the flip chip package substrate. The signal path may be coupled to the first termination circuit via at least one conductor trace and to the second termination circuit via at least one conductor trace. The number of conductor traces coupling the signal path to the first termination circuit may be different than the number of conductor traces coupling the signal path to the second termination circuit.

In some embodiments, the package substrate may comprise a laminate substrate. In some embodiments, the first termination circuit may include a capacitor implemented on the package substrate.

In some embodiments, the apparatus may further comprise a third termination circuit separate from both the first termination circuit and the second termination circuit. The third termination circuit may be configured to terminate at a phase corresponding to another harmonic frequency of the signal at the node.

In some embodiments, the at least one circuit element may comprise a gallium arsenide bipolar transistor. The collector of the gallium arsenide bipolar transistor may be configured to drive the node.

In some embodiments, the first termination circuit may include a first inductive circuit element and a first capacitive circuit element. The second termination circuit may include a second inductive circuit element and a second capacitive circuit element. The first capacitive circuit element may have a capacitance different from a capacitance of the second capacitive circuit element. The first inductive circuit element may have an inductance different from an inductance of the second inductive circuit element. The inductance of the first inductive circuit element may be different than the inductance of the second inductive circuit element because the number of conductor traces coupling the node to the first termination circuit is different than the number of conductor traces coupling the node to the second termination circuit. The conductor traces may couple the nodes to the first termination circuit in parallel.

In some embodiments, the node may be included in a path between the first power amplifier stage and the second power amplifier stage.

According to many implementations, the present disclosure is directed to a multi-chip module including a flip-chip power amplifier die having one or more power amplifiers configured to amplify an input signal and generate an amplified output signal. The multi-chip module also includes an output matching network having a first termination circuit configured to match an impedance of a fundamental frequency of the amplified output signal and a second termination circuit separate from the first termination circuit, wherein the second termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the amplified output signal.

In some embodiments, the flip chip power amplifier die may include GaAs devices and at least a portion of the output matching network may be implemented on a flip chip package substrate separately from the flip chip power amplifier die. In some embodiments, the multi-chip module may be configured to be mounted on a mobile phone board. In some embodiments, the output matching network may be configured to extend the amount of time that a battery of the mobile device is discharged. In some embodiments, the output matching network may be configured to increase the signal strength of the amplified output signal. In some embodiments, the output matching network may be configured to reduce heat dissipation in the multi-chip module. In some embodiments, the output matching network may be configured to reduce an amount by which energy of the amplified output signal is converted to energy corresponding to harmonic frequency components of the amplified output signal. In some embodiments, the output matching network may be configured to convert energy corresponding to harmonic frequency components of the amplified output to energy corresponding to fundamental frequency components of the amplified output signal.

In many implementations, the present disclosure is directed to a mobile device including a battery configured to power the mobile device, a flip chip power amplifier die configured to amplify a Radio Frequency (RF) input signal and generate an amplified RF signal, and an antenna configured to transmit the amplified RF signal. The mobile device also includes an output matching network having a first termination circuit configured to match an impedance of a fundamental frequency of the amplified RF signal and a second termination circuit separate from the first termination circuit, wherein the second termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the amplified RF signal in order to extend an amount of time that the battery discharges.

In some embodiments, the mobile device may be configured to communicate using at least one of a 3G communication standard and a 4G communication standard. In some embodiments, the mobile device may be configured as a smartphone. In some embodiments, the mobile device may be configured as a tablet computer.

In some embodiments, the first termination circuit may comprise a conductor trace in a path between the output of the power amplifier and the antenna. In some embodiments, the second termination circuit may include a conductor trace in a path between the output of the power amplifier and a ground reference voltage. In some embodiments, the at least one circuit element of the first termination circuit may include a first capacitor mounted on the flip-chip package substrate.

According to some embodiments, the present disclosure relates to an electronic system including a power amplifier configured to amplify a Radio Frequency (RF) input signal and generate an amplified RF output signal. The system also includes an antenna configured to transmit the amplified RF signal. The system also includes an output matching network having a first termination circuit configured to match an impedance of a fundamental frequency of the amplified RF output signal and a second termination circuit separate from the first termination circuit, wherein the second termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the amplified RF output signal.

In some embodiments, at least a portion of the first termination circuit may be implemented on a flip chip package substrate. In some embodiments, the system may be configured as a base station. In some embodiments, the system may be configured as a femtocell.

For purposes of summarizing the disclosure, certain aspects, advantages, and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

Drawings

Fig. 1A is a schematic block diagram of an illustrative wireless device.

Fig. 1B is a schematic block diagram of an illustrative multi-chip module.

FIG. 1C is a schematic block diagram of an illustrative electronic system.

Fig. 2 is a circuit diagram illustrating a power amplifier system having an example termination circuit, according to an embodiment.

Fig. 3 is a block diagram illustrating an example termination circuit implemented in a wire bonding configuration.

Fig. 4 is a block diagram illustrating an example termination circuit implemented in a flip-chip configuration.

Fig. 5A-5G illustrate a comparison of various performance parameters associated with the wire bond and flip chip configurations of fig. 3 and 4.

Fig. 6 illustrates that in some embodiments, the termination circuit of fig. 3 may be separated to better handle termination of the fundamental frequency and one or more harmonic frequencies.

Fig. 7 illustrates that in some embodiments, the termination circuit of fig. 4 may be separated to better handle termination of the fundamental frequency and one or more harmonic frequencies.

Fig. 8 illustrates that in some embodiments, the termination circuit of fig. 7 may be separated into N separate circuits.

Fig. 9 illustrates a process that may be implemented to fabricate the termination circuit of fig. 7.

Detailed Description

In some implementations, the present disclosure relates to a circuit, such as a termination circuit, configured to prevent or reduce signal reflections. More particularly, some implementations relate to a separate termination circuit configured to prevent or reduce reflected portions of power of different frequency components of a signal. Using the systems, apparatus, and methods described herein, an electronic system, such as a system including a power amplifier and/or a system configured to transmit Radio Frequency (RF) signals, may operate more efficiently and/or consume less power. For example, less energy may be converted to harmonic frequencies of the RF signal and/or energy from harmonic frequency components of the RF signal may be converted to energy at a fundamental frequency of the RF signal.

Power Added Efficiency (PAE) is a metric used to rank power amplifiers. Furthermore, linearity is another metric used to rank power amplifiers. PAE and/or linearity may be a metric that a customer determines which power amplifier to purchase. For example, a power amplifier with a PAE below a certain level may not be purchased by a customer due to the impact of the PAE on the customer's product. A lower PAE may, for example, reduce the battery life of an electronic device such as a mobile phone. However, enhancing PAE may come at the cost of reduced linearity. Similarly, increasing linearity can cause PAE to decrease.

The load line at the output of the power amplifier may affect PAE and linearity. The load line at the output of the power amplifier may be configured to increase and/or optimize linearity and/or PAE. This may include matching fundamental frequency components and/or harmonic frequency components of the power amplifier output. This matching may be achieved by a termination circuit.

A signal at a node in a power amplifier system may include a fundamental frequency component and one or more harmonic frequency components. Some conventional power amplifier systems have an impedance for matching the fundamental frequency of the signal at the node and a single termination circuit, e.g., a load line, for termination at a phase corresponding to the harmonic frequency of the signal at the node. However, it may be difficult to tune the single termination circuit in a manner that optimizes both PAE and linearity to both match the impedance of the fundamental frequency of the amplified power amplifier output signal and terminate at the phase of the harmonic frequency of the amplified power amplifier output signal. As a result, PAE degradation may result from optimizing the impedance matching the fundamental frequency of the amplified power amplifier output or terminating the amplified power amplifier output at the phase of the harmonic frequency.

As described herein, an electronic system may include two or more separate termination circuits, each coupled to a node in a signal path. The first termination circuit may be configured to match an impedance of a fundamental frequency of a signal at the node. In some implementations, the first termination circuit may be included in a base load line. A second termination circuit, separate from the first termination circuit, may be configured to terminate at a phase corresponding to a harmonic frequency of the signal at the node. The circuit elements of the first termination circuit and the second termination circuit may be selected so as to increase PAE and/or linearity in the power amplifier system.

In some implementations, at least a portion of the first termination circuit and/or the second termination circuit can be implemented separately from the power amplifier die. For example, in the context of a wirebond connection implementation, the first termination circuit can include one or more wirebonds electrically connected to one or more pins of the power amplifier die and one or more capacitors (e.g., capacitors) separate from the power amplifier die and mounted on the package substrate. Alternatively or additionally, the second termination circuit may include one or more wire bonds electrically connected to one or more pins of the power amplifier die and one or more capacitors (e.g., capacitors) separate from the power amplifier die and mounted on the package substrate. One or more wire bonds may be used as inductive circuit elements in at least one of the first and second termination circuits and coupled in series with one or more capacitors mounted on the package substrate. By using two or more separate termination circuits, each termination circuit can be tuned to prevent reflection of the signal at the desired frequency. For example, the inductance and/or capacitance of each termination circuit may be selected such that each termination circuit prevents reflection of a desired frequency component of the signal.

In another example, in the context of a flip-chip implementation, the first termination circuit may include one or more conductor traces formed on a package substrate, such as a laminate board. Such conductor traces may be electrically connected to one or more connection bumps of the flip-chip power amplifier die and one or more capacitors (e.g., capacitors) separate from the power amplifier die and mounted on the package substrate. Alternatively or additionally, the second termination circuit may include one or more conductor traces formed on the package substrate. Similarly, such conductor traces may be electrically connected to one or more connection bumps of the power amplifier die and one or more capacitors (e.g., capacitors) separate from the power amplifier die and mounted on the package substrate. In at least one of the first and second termination circuits, one or more conductor traces may function as inductive circuit elements and be coupled in series with one or more capacitors mounted on the package substrate. By using two or more separate termination circuits, each termination circuit can be tuned to prevent reflection of the signal at the desired frequency. For example, the inductance and/or capacitance of each termination circuit may be selected such that each termination circuit prevents reflection of a desired frequency component of the signal.

The methods, systems, and apparatus for signal path termination described herein can achieve one or more of the following advantageous features, among others. Advantageously, separate termination circuits configured to prevent reflections of two or more different frequency components of the signal may increase one or more of PAE, linearity of the power amplifier, and baseband performance (e.g., wider frequency response and/or greater bandwidth). In some implementations, both PAE and linearity of the power amplifier may be increased. In addition, the figure of merit (FOM) of the power amplifier may also be increased. Further, battery life may be extended, the amount of heat dissipation may be reduced, the signal quality of the signal that the separate termination circuit prevents from reflecting may be increased, or any combination thereof.

Headings are provided herein for convenience only and do not affect the scope or meaning of the claimed invention.

Wireless device

Any of the systems, methods, apparatuses, and computer-readable media described herein for preventing reflection of two or more frequency components of a signal may be implemented in various electronic devices, such as wireless devices, which may also be referred to as mobile devices. Fig. 1A schematically depicts a wireless device 1. Examples of the wireless device 1 include, but are not limited to, cellular phones (e.g., smart phones), laptop computers, tablet computers, Personal Digital Assistants (PDAs), e-book readers, and portable digital media players. For example, the wireless device 1 may be a multi-band and/or multi-mode device such as a multi-band/multi-mode mobile phone configured to communicate using, for example, global system for mobile communications (GSM), Code Division Multiple Access (CDMA), 3G, 4G, Long Term Evolution (LTE), and the like, or any combination thereof.

In some embodiments, the wireless device 1 may include one or more of an RF front end 2, a transceiver component 3, an antenna 4, a power amplifier 5, a control component 6, a computer readable medium 7, a processor 8, a battery 9, and a power control block 10, or any combination thereof.

The transceiver component 3 may generate RF signals that are transmitted via the antenna 4. In addition, transceiver component 3 may receive and process incoming RF signals from antenna 4.

It will be appreciated that various functions associated with transmitting and receiving RF signals may be carried out by one or more components collectively represented in fig. 1 as transceiver 3. For example, a single component may be configured to provide both transmit and receive functionality. In another example, the transmit and receive functions may be provided by separate components.

Similarly, it will be appreciated that various antenna functions associated with transmitting and receiving RF signals may be implemented by one or more components collectively represented in fig. 1 as antenna 4. For example, a single antenna may be configured to provide both transmit and receive functions. In another example, the transmit and receive functions may be provided by separate antennas. In yet another example, different antennas may be used to provide different frequency bands associated with wireless device 11.

In fig. 1, one or more output signals from transceiver 3 are depicted as being provided to antenna 4 via one or more transmit paths. In the illustrated example, the different transmit paths may represent output paths associated with different frequency bands and/or different power outputs. For example, the two example power amplifiers 5 shown may represent amplification associated with different power output configurations (e.g., low power output and high power output), and/or amplification associated with different frequency bands. In some implementations, one or more termination circuits may be included in one or more of the transmit paths.

In fig. 1, one or more detected signals from antenna 4 are depicted as being provided to transceiver 3 via one or more receive paths. In the illustrated example, the different receive paths may represent paths associated with different frequency bands. For example, the four example paths shown may represent quad-band capabilities that some wireless devices possess.

To assist in switching between receive and transmit paths, the RF front end 2 may be configured to electrically connect the antenna 4 to a selected transmit or receive path. Thus, the RF front end 2 may provide a number of switching functions associated with the operation of the wireless device 1. In some embodiments, the RF front end 2 may include a number of switches configured to provide functionality associated with, for example, switching between different frequency bands, switching between different power modes, switching between transmit and receive modes, or some combination thereof. The RF front-end 2 may also be configured to provide additional functions including filtering the signal. For example, the RF front end 2 may include one or more duplexers. Furthermore, in some implementations, the RF front end 2 may include one or more termination circuits configured to prevent reflection of frequency components of the signal.

The wireless device 1 may comprise one or more power amplifiers 5. RF power amplifiers may be used to boost the power of RF signals having relatively low power. In addition, the elevated RF signal may be used for various purposes, including driving an antenna of a transmitter. The power amplifier 5 may be included in an electronic device, such as a mobile phone, to amplify the RF signal for transmission. For example, in a mobile phone having an architecture for communicating under 3G and/or 4G communication standards, a power amplifier may be used to amplify RF signals. It may be desirable to manage amplification of RF signals because the desired transmit power level may depend on how far away the user is from the base station and/or on the mobile environment. A power amplifier may also be employed to help adjust the power level of the time-varying RF signal to prevent signal interference from transmissions during the assigned receive timeslot. The power amplifier module may include one or more power amplifiers.

Fig. 1 illustrates that in certain embodiments, a control component 6 may be provided, and such component may be configured to provide various control functions associated with the operation of the RF front end 2, the power amplifier 5, the power supply control 10, and/or one or more other operational components. Non-limiting examples of power supply control 10 are described in more detail herein.

In some embodiments, processor 8 may be configured to facilitate the various processes described herein. For purposes of description, embodiments of the present disclosure may also be described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the actions specified in the flowchart and/or block diagram block or blocks.

In certain embodiments, these computer program instructions may also be stored in a computer-readable memory 7 that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the action specified in the flowchart and/or block diagram block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the actions specified in the flowchart and/or block diagram block or blocks.

The illustrated wireless device 1 further comprises a power supply control block 10 which may be used to supply power to one or more of the power amplifiers 5. For example, in some embodiments, the power supply control block 10 may be a DC-to-DC converter. However, in some embodiments the power supply control block 10 may comprise other blocks, such as an envelope tracker configured to vary the supply voltage provided to the power amplifier 5 based on the envelope of the RF signal to be amplified.

The power supply control block 10 may be electrically connected to the battery 9, and the power supply control block 10 may be configured to change the voltage supplied to the power amplifier 5 based on the output voltage of the DC-DC converter. The battery 9 may be any battery used in the wireless device 1, including for example a lithium ion battery. By reducing the reflection of the output signal of the power amplifier 5, the power consumption of the battery 9 can be reduced, thereby improving the performance of the wireless device 1.

Multi-chip module

FIG. 1B is a schematic block diagram of a multi-chip module (MCM) 220. The MCM 220 may be referred to as a power amplifier module. MCM 220 may include a package substrate 22, a power amplifier die 24 implemented as a flip-chip configuration 200 mounted on the package substrate, a matching network 25, one or more other dies 26, and one or more circuit elements 28. One or more other die 26 may include, for example, a controller die that may include a power amplifier bias circuit and/or a direct current to direct current (DC-DC) converter. The one or more example circuit elements 28 mounted on the package substrate 22 may include, for example, one or more inductors, one or more capacitors, one or more impedance matching networks, and the like, or any combination thereof. The multi-chip module 220 may include multiple dies and/or other components mounted on the package substrate 22 of the MCM 220. In some implementations, substrate 22 may be a multi-layer substrate such as a laminate configured to support wafers and/or components and provide electrical connections to external circuitry when MCM 220 is mounted on a circuit board such as a phone board.

The power amplifier die 24 may receive the RF signal at the input pin of the MCM 220. The power amplifier die 24 may include one or more power amplifiers, including, for example, a multi-stage power amplifier configured to amplify an RF signal. The amplified RF signal may be provided to the output bumps of the power amplifier die 24. A matching network 25 may be provided on the MCM 220 to help reduce signal reflections and/or other signal distortions. Matching network 25 may include one or more termination circuits implementing any combination of the features described herein. The power amplifier die 24 may be any suitable die. In some implementations, the power amplifier wafer is a gallium arsenide (GaAs) wafer. In some of these implementations, the GaAs wafer has transistors formed using a Heterojunction Bipolar Transistor (HBT) process.

MCM 220 may also include Vcc pins that may be electrically connected to, for example, power amplifier die 24. MCM 220 may include one or more circuit elements 28 such as one or more inductors that may be formed, for example, by traces on a multi-chip module. The one or more inductors may operate as choke inductors and may be disposed between the supply voltage and the power amplifier die. In some implementations, one or more inductors may be surface mounted. Further, one or more circuit elements 28 may include one or more capacitors electrically connected IN parallel with the one or more inductors and configured to resonate at a frequency near the frequency of the signal received on pin RF _ IN. In some implementations, the one or more capacitors can include surface mount capacitors.

In an example MCM 220 implemented in a flip-chip configuration, the matching network 25 may include one or more termination circuits. In some implementations, the matching network 25 may include conductor traces configured for electrically connecting input and/or output connection bumps of the power amplifier die 24 to the package substrate 22. The conductor tracks may be used as inductors. The inductance can be increased by adding additional conductor traces in parallel. Similarly, inductance may be reduced by removing parallel conductor traces and/or adding conductor traces in series. Matching network 25 may also include one or more capacitors mounted on package substrate 22. Each termination circuit may include one or more capacitors in series with one or more conductor traces electrically connected to one or more bumps of the power amplifier die 24. The capacitance and/or inductance values may be selected to prevent certain frequency components from reflecting (e.g., from the antenna) due to impedance mismatches. This may advantageously increase one or more of PAE, power amplifier linearity, bandwidth over which the power amplifier operates within specification, FOM, etc., or any combination thereof. The termination circuit that may be included in the matching network 25 will be described in more detail herein.

MCM 220 may be modified to include more or fewer components, including, for example, additional power amplifier dies, capacitors, and/or inductors. For example, the MCM 220 may include one or more additional matching networks 25. IN particular, there may be another matching network between RF _ IN and the input of the power amplifier die 24 and/or additional matching networks between the power amplifier stages. As another example, the MCM 220 may include an additional power amplifier die and additional capacitors and inductors configured to operate as parallel LC circuits disposed between the additional power amplifier die and the Vcc pin of the module. The MCM 220 may be configured with additional pins, for example, in implementations in which separate power supplies are provided to input stages disposed on a power amplifier die and/or in implementations in which a multi-chip module operates over multiple frequency bands.

Electronic system

Fig. 1C is a schematic block diagram of another illustrative wireless system 30 in which one or more features of the present disclosure may be implemented. In some embodiments, the illustrative wireless system 30 of FIG. 1C may be implemented in a mobile telephone. Any combination of the features of the termination circuit described herein may be implemented in connection with, for example, a power amplifier in a 2.5G module and/or a 3G/4G Front End Module (FEM) of the wireless system 30.

The illustrated wireless system 30 includes a main antenna 31, a switch module 32, a 2.5G module 33, a 3G/4G front end module 34, an LNA module 35, a diversity antenna 36, a diversity front end module 37, a transceiver 38, a Global Positioning System (GPS) antenna 39, a power management controller 40, a baseband application processor 41, a memory 42, a user interface 43, an accelerometer 44, a camera 45, a WLAN/FM bluetooth system on a chip (SOC)46, a WLAN bluetooth antenna 47, and an FM antenna 48. It will be understood that wireless system 30 may include more or fewer components than shown in fig. 1C.

The transceiver 38 may be a multi-module transceiver. Transceiver 38 may be used to generate and process RF signals using various communication standards including, for example, global system for mobile communications (GSM), Code Division Multiple Access (CDMA), wideband CDMA (W-CDMA), enhanced data rates for GSM evolution (EDGE), other proprietary and non-proprietary communication standards, or any combination thereof. As shown, transceiver 38 is electrically coupled to 2.5G module 33 and 3G/4G front end module 34. The power amplifiers in the 2.5G module 33 and the 3G/4G front-end module 34 may boost the power of RF signals having relatively low power. The boosted RF signal may then be used to drive the main antenna 31. Such a power amplifier may include any of the termination circuits described herein to reduce reflections and/or noise at the input and/or output. The switch module 32 may selectively electrically couple the power amplifiers in the 2.5G module 33 and the 3G/4G front end module 34 to the main antenna 31. The switching module 32 may electrically connect the main antenna 31 to a desired transmission path.

In some implementations, the diversity front-end module 37 and the diversity antenna 36 may help improve the quality and/or reliability of the wireless link by reducing line-of-sight (line-of-sight) losses and/or mitigating the effects of phase shifts, time delays, and/or distortions associated with signal interference of the main antenna 31. In some embodiments, multiple diversity front end modules and diversity antennas may be provided to further improve diversity.

The wireless system 30 may include a WLAN/FM Bluetooth SOC module 46 that may generate and process received WLAN Bluetooth and/or FM signals. For example, the WLAN/FM Bluetooth SOC module 46 may be used to connect to Bluetooth devices such as wireless headsets and/or communicate over the Internet via a WLAN Bluetooth antenna 47 and/or an FM antenna 48 using a wireless access point or hotspot.

The wireless system 30 may also include a baseband application processor 41 to process baseband signals. A camera 43, accelerometer 44, user interface 45, etc., or any combination thereof, may be in communication with the baseband application processor 41. Data processed by the baseband application processor may be stored in memory 42.

Although the termination circuit is shown and described in the context of two examples of wireless devices, the termination circuit described herein may be used in other wireless devices and electronics.

Termination circuit

As used herein, a termination circuit may refer to a circuit configured to prevent a portion of the power of a signal, such as an RF signal, from being reflected. The termination circuit may be configured to reduce and/or minimize reflection of the signal by matching impedances. This may increase PAE and/or power amplifier gain.

Referring to fig. 2, a circuit diagram of a power amplifier system 60 will be described using an exemplary termination circuit. The power amplifier system 60 may include: one or more of power amplifier stages 62 and/or 64, e.g., GaAs bipolar transistors, a supply voltage, e.g., battery 66, inductors 68 and/or 70, and matching networks 25a, 25b, and/or 25 c. The RF input signal RF _ IN may be provided to the first stage power amplifier 62 via the input matching network 25 c. The first stage amplified RF signal may be generated by a first stage power amplifier 62. The first stage amplified RF signal may be provided to second stage power amplifier 64 via interstage power amplifier matching network 25a 1. The second stage amplified RF signal may be generated by a second stage power amplifier 64. The second stage amplified RF signal may be provided to an output load via output matching network 25b 1. In some implementations, the RF signal RF _ OUT provided to the output load may be provided to the output of the power amplifier die.

The first stage power amplifier 62 may be coupled to a supply voltage, such as a battery 66, via a choke inductor 68. Similarly, the second stage amplifier 64 may be coupled to a supply voltage, such as a battery 66, via a choke inductor 70. The first power amplifier stage 62 may consume less power from the supply voltage when the corresponding termination circuit is tuned to prevent reflection of the fundamental frequency component of the first stage amplified RF signal and one or more harmonic components of the first stage amplified RF signal. Similarly, the second power amplifier stage 64 may consume less power from the supply voltage when the corresponding termination circuit is tuned to prevent reflection of the fundamental frequency component of the second stage amplified RF signal and one or more harmonic components of the second stage amplified RF signal.

As shown in fig. 2, the power amplifier system 60 may include a first matching network 25a and a second matching network 25 b. First matching network 25a may include an inter-stage base termination circuit 25a1 and an inter-stage harmonic termination circuit 25a 2. The second matching network 25b may include an output fundamental termination circuit 25b1 and an output harmonic termination circuit 25b 2. Any combination of features of the second matching network 25b may be applied to the first matching network 25a, as applicable.

For purposes of illustration, the second matching network 25b will be described in more detail. The output base termination circuit 25b1 may be a base load line. The output base termination circuit 25b1 may be configured to prevent a portion of the power of the fundamental frequency component of the second stage amplified RF signal from being reflected from the output load. The output harmonic termination circuit 25b2 may be configured to prevent a portion of the power of one or more harmonic frequency components of the second stage amplified RF signal from being reflected from the load. More specifically, output harmonic termination circuit 25b2 may include a termination circuit configured to prevent a portion of the power of the second order harmonic frequency component of the second stage amplified RF signal from being reflected from the load. In some implementations, the output harmonic termination circuit 25b2 may alternatively or additionally include a termination circuit configured to prevent a portion of the power of the third harmonic frequency component of the second stage amplified RF signal from being reflected from the load. The principles and advantages of a separate termination circuit configured to prevent reflection of portions of the power of the harmonic frequency components of the second stage amplified RF may be applied to any desired harmonic frequency components and/or any number of harmonic frequency components.

The termination circuit corresponding to the desired frequency component of the second stage amplified RF signal may include one or more inductive circuit elements in series with one or more capacitive circuit elements. The series circuit elements of the termination circuit may be coupled to, for example, the input node of the base load line of the output base termination circuit 25b1 and a ground reference voltage. The effective inductance of the one or more inductive circuit elements and/or the effective capacitance of the one or more capacitive circuit components may be selected to tune the termination circuit to prevent reflection of desired frequency components of the second stage amplified RF signal.

The above example of the termination circuit described with reference to fig. 2 may produce desirable performance results. Additional details regarding the implementation of such TERMINATION circuits and improved performance can be found in U.S. patent application nos. 13, 543,472 entitled "signal path TERMINATION (SIGNAL PATH TERMINATION"), which is hereby incorporated by reference in its entirety.

In some embodiments, a Power Amplifier (PA) module implementing flip-chip (FC) may produce significantly better PA performance than a comparative wire-bond (WB) based module, even though the termination circuit is not separated into a base termination circuit and one or more harmonic termination circuits. To compare such wire bond and flip chip module performance characteristics, fig. 3 illustrates an exemplary wire bond-based power amplifier system configuration 160, and fig. 4 illustrates an exemplary flip chip-based power amplifier system configuration 260.

Referring to fig. 3, the power amplifier system 160 may include a power amplifier die 124 mounted on a package substrate 122. Power amplifier die 124 may include pins such as output pins 182a and 182 b. The output of the power amplifier on die 124 may be provided to output pins 182a and 182 b. Output pins 182a and 182b may correspond to a node coupled to the collector of, for example, a GaAs bipolar transistor. Output pins 182a and 182b may correspond to inputs to matching network 125n via wire bonds 184a and 184 b. Matching network 125n is depicted as having an output matching network portion 125b1 and a harmonic termination portion 125b 2.

In the example power amplifier system 160 of fig. 3, output base termination portion 125b1 is electrically coupled to harmonic termination portion 125b 2. The base termination portion 125b1 may include one or more wire bonds 184b that couple one or more output pins 182b to wire traces of the package substrate 122. Harmonic termination portion 125b2 may include one or more wire bonds 184a that couple one or more output pins 182a to wire traces of package substrate 122 that are connected to wire traces associated with base termination portion 125b 1.

In the example power amplifier system 160 of fig. 3, the base termination portion 125b1 is depicted as being connected to an RF output pin of the PA system 160. Similarly, harmonic termination 125b2 is depicted as being connected to a DC power pin of PA system 160.

Referring to fig. 4, the power amplifier system 260 may include a power amplifier die 224 mounted on a package substrate 222. The power amplifier die 224 may include bump connections, such as output bumps 282a and 282 b. The output of the power amplifier on die 224 may be provided to output bumps 282a and 282 b. The output bumps 282a and 282b may correspond to nodes coupled to the collector of the GaAs bipolar transistor. The output bumps 282a and 282b may correspond to inputs to the matching network 225b via the conductor traces 284a and 284 b. Matching network 225b is depicted as having an output matching network portion 225b1 and a harmonic termination portion 225b 2.

In the example power amplifier system 260 of fig. 4, output base termination circuit 225b1 is electrically connected to harmonic termination section 225b 2. The base termination portion 225b1 may include one or more conductor traces 284b that couple one or more output bumps 282b to conductor traces of the package substrate 222. Harmonic termination portion 225b2 may include one or more conductor traces 284a that couple one or more output bumps 282a to conductor traces of package substrate 222 that are connected to conductor traces associated with base termination portion 225b 1.

In the example power amplifier system 260 of fig. 4, the base termination section 225b1 is depicted as being connected to an RF output pin of the PA system 260. Similarly, harmonic termination 225b2 is depicted as being connected to a DC power pin of PA system 260.

Fig. 5A-5G illustrate a comparison of some example performance parameters for a power amplifier when implemented in a Wire Bond (WB) configuration (e.g., fig. 3) and a flip chip configuration (e.g., fig. 4). For the flip-chip configuration, the two examples (FC1 and FC2) differ in their inter-stage termination circuits.

Fig. 5A shows a graph of power added efficiency (PAE, in%) as a function of power output (Pout) of an example power amplifier in dBm (measured power versus power ratio in dB of 1 milliwatt). The graph shows that the FC1 and WB cases produce similar performance, while FC2 produces consistently higher PAE performance over the entire power output range shown.

Fig. 5B shows a plot of gain (in dB) as a function of power output (Pout) (in dBm) of an example power amplifier. The graph shows that both the FC1 and FC2 cases produce higher gain than the WB case.

Fig. 5C shows a graph of ACP (adjacent channel power) (in dBc, power ratio of the signal relative to the carrier signal) as a function of the power output (Pout) (in dBm) of an exemplary power amplifier. The graph shows that the FC1 case has higher ACP than the WB case when Pout is between 17 and 23dBm, but merges into similar performance at higher Pout values. Except that Pout is in the range of 26dBm to 27dBm, the FC2 case is shown to produce ACP that is generally higher than the WB case.

Fig. 5D shows a graph of FOM (figure of merit) as a function of power output (Pout) (in dBm) of an example power amplifier. The graph shows that the FC1 case has a lower FOM than the WB case when Pout is between 17 and 23dBm, merging to similar performance at higher Pout values. The FC2 case is also shown to be lower than the WB case when Pout is between 17 and 23dBm, and between 28 and 30 dBm; but higher in other ranges (23 to 28dBm and 30 to 31 dBm).

Fig. 5E shows a plot of the second harmonic response (in dBc) as a function of the power output (Pout) (in dBm) of an example power amplifier. The graph shows that both the FC1 and FC2 cases have significantly lower second harmonic amplitudes than the WB case over the entire Pout range.

Fig. 5F shows a plot of the third harmonic response (in dBc) as a function of the power output (Pout) (in dBm) of an exemplary power amplifier. The graph shows that both the FC1 and FC2 cases have significantly lower third harmonic amplitudes than the WB case over the entire Pout range.

Fig. 5G shows a graph of insertion loss (in dB) as a function of frequency for signals processed by an example power amplifier. The graph shows that both FC and FC' have lower insertion loss at the second and third harmonics than the WB case. For the third harmonic, the insertion loss for FC and FC' is significantly lower than for WB case.

Fig. 6 illustrates an example wire bonding configuration 360 in which matching network 125b may include an output matching network portion 125b1 that is separate from harmonic termination portion 125b 2. Other components (e.g., input matching network 125c and PA die 124) may be similar to those described with reference to fig. 3.

In implementations having more than one output pin 182a, wire bonds 184a that electrically connect the pins 182a to wire traces on the substrate 122 may be coupled in parallel. The number of wire bonds 184a included in output harmonic termination circuit 125b2 may be configured separately from the number of wire bonds 184b of output base termination circuit 125b 1. In this manner, the inductance of the different termination circuits may be tuned to increase the linearity and/or PAE of the power amplifier system 360. This may include: impedance matching the fundamental frequency of the signal at the node in the output fundamental termination circuit 125b1, and termination at a phase corresponding to the harmonic frequency of the signal at the node in the output harmonic termination circuit 125b 2. Alternatively or additionally, the effective capacitances of the different termination circuits may also be configured separately or independently of each other. For example, in the output matching network shown in fig. 6, the wire traces may be coupled with wire bonds in series with one or more capacitive circuit elements, such as capacitors. The effective capacitance of the termination circuit may be selected to prevent or reduce reflection of desired frequency components of signals on the signal path at the one or more output pins 182a that are different from the desired frequency components of signals for which the output base termination circuit 125b1 is configured to prevent or reduce reflection. The effective inductance and the effective capacitance of the termination circuit may be configured in combination with each other so as to increase the active and/or PAE of the power amplifier system 360.

Fig. 7 illustrates an example flip-chip configuration 460 in which matching network 225b may include an output matching network portion 225b1 separate from harmonic termination portion 225b 2. Other components (e.g., input matching network 225c and PA die 224) may be similar to those described with reference to fig. 4.

In implementations having more than one output bump 282a, the conductor traces 284a that electrically connect the bumps 282a to the lead traces on the substrate 222 may be coupled in parallel. The number of wire bonds 284a included in output harmonic termination circuit 225b2 may be configured separately from the number of conductor traces 284b of output base termination circuit 125b 1. In this manner, the inductance of the different termination circuits may be tuned to increase the linearity and/or PAE of the power amplifier system 460. This may include: impedance matching the fundamental frequency of the signal at the node in the output fundamental termination circuit 225b1, and termination at a phase corresponding to the harmonic frequency of the signal at the node in the output harmonic termination circuit 225b 2. Alternatively or additionally, the effective capacitances of the different termination circuits may also be configured separately or independently of each other. For example, in the output matching network shown in fig. 7, the lead traces may be coupled with conductive traces in series with one or more capacitive circuit elements, such as capacitors. The effective capacitance of the termination circuit may be selected to prevent or reduce reflection of desired frequency components of signals on signal paths at the one or more output bumps 282a that are different from the desired frequency components of signals for which the output base termination circuit 225b1 is configured to prevent or reduce reflection. The effective inductance and the effective capacitance of the termination circuit may be configured in combination with each other to increase the linearity and/or PAE of the power amplifier system 460.

Fig. 8 illustrates that, in some embodiments, any suitable number of separate termination circuits may be implemented based on the desired application. Further, fig. 8 illustrates that multiple separate termination circuits may be implemented at various nodes within an electronic system, such as inputs to a die and/or outputs from a die. Although fig. 8 shows a plurality of separate termination circuits at input and output locations on a wafer, any combination of features of the separate termination circuits described herein may be applied to signals at other nodes of an electronic system, including, for example, within a wafer such as a power amplifier wafer. Further, according to some implementations, one or more of the separate termination circuits coupled to the node may be implemented within the wafer and one or more of the separate termination circuits coupled to the node may be implemented off-wafer.

As shown in fig. 8, electronic system 490 may include a flip-chip die 492 and a plurality of termination circuits. Electronic system 490 may be included, for example, in the wireless device of fig. 1A, the multi-chip module of fig. 1B, the electronic system of fig. 1C, etc., or any combination thereof. In some implementations, the wafer 492 may be a flip chip power amplifier wafer as described herein. In other implementations, the wafer 492 may include a frequency multiplier and/or a mixer, for example.

Wafer 492 can include a plurality of input bumps 494a-494n and/or output bumps 496a-496 n. Separate termination circuits including any combination of the features described herein may be coupled to different bumps. For example, input termination circuits 498a-498n may each be configured to prevent or reduce reflection of different frequency components of a signal at a node coupled to one or more input bumps of wafer 492. Input termination circuits 498a-498n may be coupled to input bumps 494a-494n of wafer 492 via bump pads 493a-493n and conductor traces 491a-491n, respectively, formed on the package substrate. In some implementations, the input termination circuit can be coupled to two or more input bumps of the wafer 492. Alternatively or additionally, two or more input termination circuits may be coupled to a single bump of the wafer 492.

Similarly, output termination circuits 499a-499n may each be configured to prevent or reduce reflections of different frequency components of a signal at a node including one or more output bumps. Output termination circuits 499a-499n may be coupled to output bumps 496a-496n of wafer 492 via bump pads 495a-495n and conductor traces 497a-497n, respectively, formed on the package substrate. In some implementations, the output termination circuits can be coupled to two or more output bumps of the wafer 492. Alternatively or additionally, two or more output termination circuits may be coupled to a single bump of the wafer 492.

Any suitable number of input bumps 494a-494n and/or output bumps 496a-496n may be included in wafer 492. In addition, any suitable number of input termination circuits 498a-498n and/or output termination circuits 499a-499n may be included in electronic system 490. In some implementations, the number of separate input terminal circuits 498a-498n and/or separate output terminal circuits 499a-499n may be selected based on a desired number of harmonic frequency components to be reduced or substantially removed.

Fig. 9 illustrates a process 500 that may be implemented to fabricate a termination circuit device having one or more of the features described herein. In block 502, a substrate may be provided. Such substrates may include laminates such as multi-chip module (MCM) laminates. In block 504, connections for receiving a flip chip may be formed on a substrate. Such a flip chip may include an Integrated Circuit (IC) and a node driven by the IC. In block 506, a first termination circuit may be formed in and/or on the substrate and configured to substantially match an impedance of a fundamental frequency of a signal at the node. In block 508, a second termination circuit may be formed in and/or on the substrate and configured to be separate from the first termination circuit. The second termination circuit may be further configured to substantially terminate at a phase corresponding to a harmonic frequency of the signal at the node.

In some embodiments, the formation of the first and second termination circuits described above may be accomplished during fabrication of the laminate, after such fabrication, and any combination thereof. For example, electrical connections may be formed during the laminate fabrication process, such as for termination circuits or interlayer connections associated with termination circuits. In another example, at least some of the conductor traces that are part of the termination circuit can be formed on a surface of the laminate proximate to the flip-chip mounting location.

Applications of

Some of the embodiments described above provide examples relating to electronic devices including power amplifiers, such as mobile phones and base stations. However, the principles and advantages of the embodiments may be applied to any other system or apparatus that requires two or more separate termination circuits configured to prevent reflection of two or more different frequency components of a signal. For example, separate termination circuits may be implemented in connection with multipliers and/or mixers, e.g., frequency multipliers, rather than power amplifiers. As another example, separate termination circuits may be implemented at any point on a signal path where it is desirable to separate the termination circuits for two or more different frequency components, e.g., fundamental frequency components and harmonic frequency components.

Systems implementing one or more aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, portions of consumer electronics, electronic test equipment, and the like. More specifically, examples of electronic devices configured to implement one or more aspects of the present disclosure may include, but are not limited to, RF transmitting devices, any portable device with a power amplifier, a mobile phone (e.g., a smartphone), a telephone, a base station, a femtocell, radar, a device configured to communicate according to a WiFi standard, a television, a computer monitor, a computer, a handheld computer, a tablet computer, a laptop computer, a Personal Digital Assistant (PDA), a microwave oven, a refrigerator, an automobile, a stereo, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washing machine, a dryer, a washing/drying machine, a copier, a facsimile machine, a scanner, a multifunction peripheral, a wristwatch, a clock, and the like. Portions of consumer electronics products may include multi-chip modules, power amplifier modules, integrated circuits including one or more termination circuits, package substrates including one or more circuit elements, and the like. Further, other examples of electronic devices may also include, but are not limited to, memory chips, memory modules, circuitry for optical networks or other communication networks, and disk drive circuitry. Further, the electronic device may include unfinished products.

Conclusion

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is to be interpreted in the meaning of "including, but not limited to". As generally used herein, the term "coupled" means that two or more elements may be connected directly or through one or more intermediate elements. Moreover, as used in this application, the words "herein," "above," "below," and words of similar import shall refer to this application as a whole and not to any particular portions of this application. Words in the above detailed description using the singular or plural number may also include the plural or singular number, respectively, as the context permits. When the word "or" refers to a list of two or more items, the word covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

Furthermore, conditional language, e.g., "can," "etc," "e.g.," and "such as," as used herein are generally intended to mean, unless specifically stated otherwise, or as used within the context otherwise: some embodiments include but do not include certain features, elements, and/or states. Thus, such conditional language is not generally intended to imply that features, elements, and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding whether such features, elements, and/or states are included or are to be performed in any particular embodiment, whether or not author input or prompting is present.

The above detailed description of embodiments is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Further, while processes or blocks are sometimes shown as occurring in series, these processes or blocks may alternatively occur in parallel, or may occur at different times.

The teachings provided herein may be applied to other systems, not necessarily the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.

While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel methods and systems described herein may be embodied in various other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

Claims (20)

1. A flip chip device comprising:

a radio frequency signal path having a node driven by at least one circuit element formed on a flip chip wafer;

a first termination circuit electrically coupled to the radio frequency signal path and configured to match an impedance of a fundamental frequency of a signal at the node, the first termination circuit including a first circuit element external to the flip chip die; and

a second termination circuit electrically coupled to the radio frequency signal path and separate from the first termination circuit, the second termination circuit configured to terminate at a phase corresponding to a harmonic frequency of the signal at the node, the second termination circuit including a second circuit element external to the flip chip die, the second circuit element and the first circuit element being electrically connected to the flip chip die by different bumps.

2. The apparatus of claim 1, wherein the at least one circuit element comprises a power amplifier.

3. The apparatus of claim 2, wherein the node is connected to an output of the power amplifier.

4. The apparatus of claim 2, wherein the node is connected to an input of the power amplifier.

5. The apparatus of claim 1, wherein the harmonic frequency comprises a second harmonic frequency of the signal.

6. The apparatus of claim 1, further comprising a base load line including the first termination circuit.

7. The apparatus of claim 1, wherein at least a portion of the first termination circuit and at least a portion of the second termination circuit are implemented on a flip chip package substrate.

8. The apparatus of claim 7, wherein the signal path is implemented on a flip chip die in communication with the flip chip package substrate.

9. The device of claim 7, wherein the package substrate comprises a laminate substrate.

10. The apparatus of claim 7, wherein the first termination circuit comprises a capacitor implemented on the package substrate.

11. The apparatus of claim 1, further comprising a third termination circuit separate from the first and second termination circuits, the third termination circuit configured to terminate at a phase corresponding to another harmonic frequency of the signal at the node.

12. The apparatus of claim 1, wherein the at least one circuit element comprises a gallium arsenide bipolar transistor, a collector of the gallium arsenide bipolar transistor configured to drive the node.

13. The apparatus of claim 1, wherein the first termination circuit includes a first inductive circuit element and a first capacitive circuit element, the first circuit element being either the first inductive circuit element or the first capacitive circuit element.

14. The apparatus of claim 13, wherein the second termination circuit includes a second inductive circuit element and a second capacitive circuit element, the second circuit element being either the second inductive circuit element or the second capacitive circuit element.

15. The apparatus of claim 1, wherein the node is included in a path between a first power amplifier stage and a second power amplifier stage.

16. A multi-chip module, comprising:

a flip-chip power amplifier die comprising one or more power amplifiers configured to amplify an input signal and generate an amplified output signal; and

an output matching network electrically coupled to the one or more power amplifiers, the output matching network comprising a first termination circuit configured to match an impedance of a fundamental frequency of the amplified output signal and a second termination circuit separate from the first termination circuit, the first termination circuit comprising a first circuit element external to the flip chip power amplifier die, the second termination circuit comprising a second circuit element external to the flip chip power amplifier die, the second circuit element and first circuit element being electrically connected to the flip chip die by different bumps, and wherein the second termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the amplified output signal.

17. The multi-chip module of claim 16 wherein the flip-chip power amplifier die comprises GaAs devices and at least a portion of the output matching network is implemented on a flip-chip package substrate separately from the flip-chip power amplifier die.

18. The multi-chip module of claim 16 wherein the output matching network is configured to reduce an amount by which energy of the amplified output signal is converted to energy corresponding to harmonic frequency components of the amplified output signal.

19. A mobile device, comprising:

a battery configured to supply power to the mobile device;

a flip-chip power amplifier die comprising one or more power amplifiers configured to amplify a radio frequency input signal and generate an amplified radio frequency signal;

an antenna configured to transmit the amplified radio frequency signal; and

an output matching network electrically coupled to the one or more power amplifiers, the output matching network comprising a first termination circuit configured to match an impedance of a fundamental frequency of the amplified radio frequency signal and a second termination circuit separate from the first termination circuit, the first termination circuit comprising a first circuit element external to the flip chip power amplifier die, the second termination circuit comprising a second circuit element external to the flip chip power amplifier die, the second circuit element and first circuit element being electrically connected to the flip chip die by different bumps, and wherein the second termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the amplified radio frequency signal so as to extend an amount of time that the battery discharges.

20. The mobile device of claim 19, configured to communicate using at least one of a 3G communication standard and a 4G communication standard.