HK1212816B - Image sensor pixel having storage gate implant with gradient profile - Google Patents

Abstract

The present application relates to an image sensor pixel having storage gate implant with gradient profile. A pixel cell includes a storage transistor disposed in a semiconductor substrate. The storage transistor includes a storage gate disposed over the semiconductor substrate, and a storage gate implant that is annealed and has a gradient profile in the semiconductor substrate under the storage transistor gate. A transfer transistor is disposed in the semiconductor substrate and is coupled between the photodiode and an input of the storage transistor. The transfer transistor includes a transfer gate disposed over the semiconductor substrate. An output transistor is coupled to an output of the storage transistor. The output transistor includes an output gate disposed over the semiconductor substrate.

Description

Image sensor pixel with storage gate implant having gradient profile

Technical Field

The present invention relates generally to semiconductor processing. More specifically, examples of the invention relate to semiconductor processing of image sensor pixel cell storage gates.

Background

For high speed image sensors, a global shutter may be used to capture fast moving objects. A global shutter typically enables all pixel cells in an image sensor to capture an image simultaneously. For slower moving objects, a more common rolling shutter is used. Rolling shutters typically capture images in sequence. For example, each row within a two-dimensional ("2D") array of pixel cells may be sequentially enabled such that each pixel cell within a single row captures an image simultaneously, but each row is enabled in a rolling order. As such, each row of pixel cells captures an image during a different image acquisition window. For slowly moving objects, the time difference between each row produces image distortion. For fast moving objects, a rolling shutter causes a perceptible elongation distortion along the axis of movement of the object.

To implement a global shutter, a storage capacitor or storage transistor (which may also be referred to herein as a storage gate) may be used to temporarily store image charge acquired by each pixel cell in the array while it waits for a readout from the array of pixel cells. When a global shutter is used, image charge is typically transferred from the photodiode to a storage transistor using a transfer transistor, and then the stored image charge is transferred from the storage transistor to a readout node of the pixel cell using an output transistor.

Factors that affect the performance of an image sensor pixel cell with a global shutter include shutter efficiency, dark current, white pixels, and image lag. One tradeoff faced by designers when designing pixel cells is that when the structures of adjacent transistors (e.g., transfer, storage, and output transistors) overlap to reduce hysteresis, some of the electrons are trapped in deep implanted regions between adjacent transistors, which results in a "pinched-down" channel that prevents some of the electrons from flowing to the output floating diffusion during transfer.

Disclosure of Invention

In one aspect, the present invention provides a pixel cell comprising: a storage transistor disposed in a semiconductor substrate, the storage transistor comprising: a storage gate disposed over the semiconductor substrate; and a storage gate implant annealed and having a gradient profile in the semiconductor substrate below the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate; a transfer transistor disposed in the semiconductor substrate and coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor, the transfer transistor including a transfer gate disposed over the semiconductor substrate; and an output transistor disposed in the semiconductor substrate and coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a readout node, the output transistor including an output gate disposed over the semiconductor substrate.

In another aspect, the present invention provides an imaging system comprising: a pixel array of pixel cells, wherein each of the pixel cells includes: a storage transistor disposed in a semiconductor substrate, the storage transistor comprising: a storage gate disposed over the semiconductor substrate; and a storage gate implant annealed and having a gradient profile in the semiconductor substrate below the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate; a transfer transistor disposed in the semiconductor substrate and coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor, the transfer transistor including a transfer gate disposed over the semiconductor substrate; and an output transistor disposed in the semiconductor substrate and coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a readout node, the output transistor including an output gate disposed over the semiconductor substrate; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to readout image data from a plurality of pixels.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Figure 1 is a schematic diagram illustrating one example of a pixel cell having a storage gate implant with a gradient profile according to the teachings of this disclosure.

Figure 2 is a cross-sectional view illustrating one example of a pixel cell having a storage gate implant with a gradient profile according to the teachings of this disclosure.

Figure 3A is a top view illustrating one example of a pixel cell storage gate implant with an effective gradient profile according to the teachings of this disclosure.

Figure 3B is a top view illustrating another example of a pixel cell storage gate implant with an effective gradient profile according to the teachings of this disclosure.

Figure 3C is a top view illustrating yet another example of a pixel cell storage gate implant with an effective gradient profile according to the teachings of this disclosure.

Figure 4 is a diagram illustrating one example of an imaging system having a pixel array including pixel cells with storage gate implants having a gradient profile according to the teachings of this disclosure.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention. Additionally, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Detailed Description

As will be shown, the present disclosure is directed to methods and apparatus for image sensor pixels having storage gate implants with gradient profiles. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to "one embodiment," "an embodiment," "one example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. Thus, appearances of the phrases such as "in one embodiment" or "in one example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The following is a detailed description of terms and elements used in the description of examples of the invention, with reference to the accompanying drawings.

In a typical image sensor pixel cell, most of the electrons trapped in the pixel cell with the overlapping deep implant regions are trapped between the transfer transistor and the memory transistor structure due to the deep memory transistor implant. The reduction in overlap between the transfer transistor and the storage transistor can help reduce the number of trapped electrons, but at the cost of increased photodiode-to-storage gate lag. Reducing the storage gate implant energy may also help to reduce storage gate lag, but the risk of dark current and/or white pixels is increased as a result. Reducing the storage gate dose can help reduce storage gate lag, but at the cost of reduced full well capacity.

As will be shown, an imaging system having a pixel array including pixel cells with storage gate implants having gradient profiles in accordance with the teachings of the present invention enables an image sensor pixel cell array with a global shutter having reduced photodiode and storage gate transfer hysteresis. Furthermore, as will be discussed, with pixel cells having a storage gate implant with a gradient profile according to the teachings of the present invention, the risk of electrons being trapped on the transfer gate side of the pixel cell is also reduced.

To illustrate, FIG. 1 is a schematic diagram illustrating one example of a pixel cell 100 having a storage gate implant 145 with a gradient profile according to the teachings of the present disclosure. For example, in the depicted example, pixel cell 100 includes a global shutter transistor 110, a photodiode 120, a transfer transistor 130, a storage transistor 140, an output transistor 150, a floating diffusion 170, a reset transistor 160, an amplifier transistor 180, and a row select transistor 190 coupled to a column bit line, as shown. As illustrated in the examples, the storage gate implant 145 under the gate of the storage transistor 140 has a graded doping profile according to the teachings of the present disclosure. In particular, in one example, the effective doping level at the transfer gate side of the memory gate implant 145 is less than the effective doping level at the output gate side of the memory gate implant 145 in accordance with the teachings of this disclosure. With a graded doping profile of the storage gate implant 145 as shown, a corresponding graded potential profile is formed. The resulting potential ramp in the storage gate implant 145 effectively pushes electrons in the storage gate toward the output gate side according to the teachings of this disclosure. Thus, according to the teachings of this disclosure, the gradient profile in the storage gate implant 145 reduces the storage gate electron density near the transfer gate side of the storage gate implant 145 relative to the output gate side of the storage gate implant 145 and reduces storage gate transfer lag.

Figure 2 is a cross-sectional view illustrating one example of a pixel cell 200 having a storage gate implant 245 with a gradient profile according to the teachings of this disclosure. Note that in one example, pixel cell 200 of fig. 2 is a cross-sectional view of pixel cell 100 of fig. 1, and similarly named and numbered elements mentioned below are coupled and function similarly as described above. As shown in the example depicted in fig. 2, pixel cell 200 is a Front Side Illuminated (FSI) pixel cell that includes a photodiode 220 disposed in a semiconductor substrate 202 to accumulate image charge from light 206 directed thereto. In another example, it should be appreciated that pixel cell 200 may alternatively be implemented as a backside illuminated (BSI) pixel cell in accordance with the teachings of this disclosure. Referring back to the example illustrated in fig. 2, the image charge accumulated in the photodiode 220 is electrons. In other examples, it should be appreciated that the image charge accumulated in the photodiode 220 may be holes. In one example, light 206 represents a portion of an image directed to pixel cell 200 by a lens. In one example, a global shutter transistor including a shutter gate 210 disposed over a gate oxide 204 and a semiconductor substrate 202 is included in the pixel cell 200, which can be utilized to selectively deplete charge (photovoltaically generated) in the photodiode 220. A storage transistor including a storage gate 240 disposed over a gate oxide 204 and a semiconductor substrate 202 is disposed in the semiconductor substrate 202 to store image charge. A transfer transistor including a transfer gate 230 disposed over the gate oxide 204 and the semiconductor substrate 202 is disposed between the photodiode 220 and the storage transistor to selectively transfer image charge from the photodiode 220 to the storage transistor to store the image charge accumulated by the photodiode 220 therein. An output transistor including an output gate 250 disposed over a gate oxide 204 and a semiconductor substrate 202 is disposed in the semiconductor substrate 202 and coupled to an output of the storage transistor to selectively transfer image charge from the storage transistor to a readout node, which in one example includes a floating diffusion 270 disposed in the semiconductor substrate 202. In one example, the shutter gate 210, transfer gate 230, storage gate 240, and output gate 250 comprise polysilicon.

Continuing with the example depicted in fig. 2, the storage gate implant 245 is implanted in the semiconductor substrate 202 with a gradient profile as shown. In particular, in one example, the effective doping level at the transfer gate 230 side of the storage gate implant 245 is less than the effective doping level at the output gate 250 side of the storage gate implant 245 in accordance with the teachings of the present disclosure. Thus, with a graded doping profile of the storage gate implant 245 as shown, a corresponding graded potential profile is formed. As shown in fig. 2, the electron potential 242 in the storage gate implant 245 decreases from the transfer gate 230 side to the output gate 250 side, which creates a potential ramp in the storage gate implant 245 that effectively pushes electrons in the storage gate toward the output gate 250 side, according to the teachings of this disclosure. Thus, according to the teachings of this disclosure, the gradient profile in the storage gate implant 245 reduces the storage gate electron density proximate the transfer gate 230 side of the storage gate implant 245 and reduces the storage gate transfer lag.

Figure 3A is a top view illustrating one example of a pixel cell storage gate implant 345A with an effective gradient profile in a semiconductor substrate under a storage gate transistor according to the teachings of this disclosure. Note that in one example, the storage gate implant 345A of fig. 3A is a top view of the storage gate implant 145 of fig. 1 or the storage gate implant 245 of fig. 2, and similarly named and numbered elements mentioned below are coupled and function similarly as described above. As shown in the example depicted in fig. 3A, the storage gate implant 345A includes a plurality of regions 346A and 348A, where each region 346A and 348A has a different effective doping concentration that increases from the transfer gate side 330 to the output gate side 350, in accordance with the teachings of the present disclosure.

In the particular example depicted in fig. 3A, in a region 346A near the output gate side 350 of the storage gate implant 345A, there is a storage gate implant of dopants into the semiconductor substrate. In one example, the dopant in the storage gate implant 345A is an N-type dopant. However, according to the teachings of this disclosure, in a region 348A near the transfer gate side 330 of the storage gate implant 345A, no dopant is implanted, which defines no gaps of implanted dopant between the plurality of "fingers" 347A and "fingers" 347A of implanted dopant on the transfer gate side 330 of the storage gate implant 345A.

In one example, after the region 346A having the "fingers" 347A has been implanted into the semiconductor substrate as shown, the semiconductor substrate is then annealed, which allows some of the implanted dopants to move around in the semiconductor substrate from a region of higher doping concentration to a region of lower doping concentration. With a dopant gradient between the region 346A with the "fingers" 347A of higher doping concentration and the region 348A of lower doping concentration, some of the implanted dopant will thus move from the region 346A and the "fingers" 347A into the region 348A across the boundary between the regions 346A and 348A due to the anneal. In other words, in the example depicted in figure 3A, some of the implanted dopants will move from the region 346A with "fingers" 347A into the region 348A, and the net result will be a dopant gradient between the OG side 350 and TX side 330 of the storage gate implant 345A, in accordance with the teachings of this disclosure.

In the example depicted in fig. 3A, note that the mask used to implant dopants into region 346A is illustrated as having a gap-to- "finger" 347A width ratio that is fixed at 1: 1. It should be appreciated that the gap-to- "finger" 347A width ratio may vary, for example, from 0.5:1 to 1.5:1, which allows for further adjustment of the gradient in the storage gate implant 345A, in accordance with the teachings of this disclosure. It should be appreciated that the example 0.5:1 to 1.5:1 ratios are provided for purposes of explanation, and in other examples, other varying gap-to- "finger" 347A width ratios may be utilized in accordance with the teachings of this disclosure.

Thus, according to the teachings of this disclosure, an effective gradient profile of the storage gate implant 345A is provided with a plurality of "fingers" 347A defined by regions 346A, 347A and 348A with and without implanted dopants as shown in the example of fig. 3A, and with annealing as described. Thus, according to the teachings of this disclosure, the effective doping level at the transfer gate side 330 of the storage gate implant 345A is less than the effective doping level at the output gate side 350 of the storage gate implant 345A. Thus, with a gradient doping profile of the storage gate implant 345A as shown, a corresponding gradient potential profile is formed. As shown in fig. 3A, the electron potential 342 in the storage gate implant 345A decreases from the transfer gate side 330 to the output gate side 350, which forms a potential ramp in the storage gate implant 345A that prevents electrons from being trapped at the transfer gate side 330 and effectively pushes the electrons in the storage gate toward the output gate side 350 before transferring the electrons to the floating diffusion, according to the teachings of the present invention. Thus, according to the teachings of this disclosure, the gradient profile in the storage gate implant 345A reduces the storage gate electron density near the transfer gate side 330 of the storage gate implant 345A and reduces the storage gate transfer lag. Furthermore, in the example depicted in fig. 3A, it should be appreciated that the gradient profile of the storage gate implant 345A may be achieved with only a single mask, a single implant step, and an anneal step to provide the region 346A with the plurality of "fingers" 347A as discussed above, in accordance with the teachings of this disclosure.

Figure 3B is a top view illustrating another example of a pixel cell storage gate implant 345B with an effective gradient profile according to the teachings of this disclosure. Note that in one example, the storage gate implant 345B of fig. 3B is a top view of the storage gate implant 145 of fig. 1 or the storage gate implant 245 of fig. 2, and similarly named and numbered elements mentioned below are coupled and function similarly as described above. As shown in the example depicted in fig. 3B, the storage gate implant 345B includes a plurality of regions 346B and 348B, where each region 346B and 348B has a different effective doping concentration that increases from the transfer gate side 330 to the output gate side 350, in accordance with the teachings of the present disclosure.

In the particular example depicted in fig. 3B, in region 348B near transfer gate side 330 of storage gate implant 345B, there is a first storage gate implant of dopants into the semiconductor substrate, labeled "SG 1 implant. In one example, the dopant in the storage gate implant 345B is an N-type dopant. However, in region 346B near the output gate side 350 of the storage gate implant 345B, there is an additional second implant of dopants, correspondingly labeled as "SG 1+ SG2 implant".

In one example, after regions 346B and 348B have been implanted into the semiconductor substrate as shown, the semiconductor substrate may then be annealed, which allows some of the implanted dopants to move around in the semiconductor substrate from regions of higher doping concentration to regions of lower doping concentration. With a dopant gradient between region 346B having a higher doping concentration and region 348B having a lower doping concentration, some of the implanted dopant will thus move from region 346B into region 348B across the boundary between regions 346B and 348B due to the anneal. In other words, in the example depicted in figure 3B, some of the implanted dopants will move from region 346B into region 348B, and the net result will be a dopant gradient between the OG side 350 and TX side 330 of the storage gate implant 345B, in accordance with the teachings of this disclosure.

Thus, according to the teachings of this disclosure, an effective gradient profile of the storage gate implant 345B is provided with a corresponding number of implants of dopants from the transfer gate side 330 toward the output gate side 350 into the storage gate implant 345B as shown in the example of fig. 3B. Thus, according to the teachings of this disclosure, the effective doping level at the transfer gate side 330 of the storage gate implant 345B is less than the effective doping level at the output gate side 350 of the storage gate implant 345B. Thus, with a gradient doping profile of the storage gate implant 345B as shown, a corresponding gradient potential profile is formed. As shown in fig. 3B, the electron potential 342 in the storage gate implant 345B decreases from the transfer gate side 330 to the output gate side 350, which forms a potential ramp in the storage gate implant 345B that prevents electrons from being trapped at the transfer gate side 330 and effectively pushing electrons in the storage gate toward the output gate side 350 before being transferred to the floating diffusion, in accordance with the teachings of the present invention. Thus, according to the teachings of this disclosure, the gradient profile in the storage gate implant 345B reduces the storage gate electron density near the transfer gate side 330 of the storage gate implant 345B and reduces the storage gate transfer lag.

Figure 3C is a top view illustrating yet another example of a pixel cell storage gate implant 345C having an effective gradient profile according to the teachings of this disclosure. Note that in one example, the storage gate implant 345C of fig. 3C is a top view of the storage gate implant 145 of fig. 1 or the storage gate implant 245 of fig. 2, and similarly named and numbered elements mentioned below are coupled and function similarly as described above. It should also be appreciated that the storage gate implant 345C of fig. 3C shares many similarities with the storage gate implant 345B of fig. 3B. One difference between the storage gate implant 345C of fig. 3C and the storage gate implant 345B of fig. 3B, according to the teachings of the present disclosure, is that the storage gate implant 345C of fig. 3C includes an additional region, illustrated therein as a plurality of regions 346C, 348C and 348D, with each region 346C, 348C and 348D having a different effective doping concentration that increases from the transfer gate side 330 to the output gate side 350.

In the particular example depicted in fig. 3C, in region 348D near the transfer gate side 330 of the storage gate implant 345C, there is a first storage gate implant of dopants into the semiconductor substrate, labeled "SG 1 implant. In one example, the dopant in the storage gate implant 345C is an N-type dopant. Moving toward the output gate side 350, in the example, there is another region 348C of additional storage gate implants (correspondingly labeled "SG 1+ SG2 implants") with dopants therein. Continuing toward the output gate side 350, there is yet another region 346C of yet another additional storage gate implant having dopants therein (correspondingly labeled "SG 1+ SG2+ SG3 implant").

In one example, after regions 346C, 348C and 348D have been implanted into the semiconductor substrate as shown, the semiconductor substrate is then annealed, which allows some of the implanted dopants to move around in the semiconductor substrate from regions of higher doping concentration to regions of lower doping concentration. With a dopant gradient between region 346C having a higher doping concentration, region 348C having a lower doping concentration, and region 348D having an even lower doping concentration than region 348C, some of the implanted dopant will thus move from region 346C into region 348C and from region 348C into 348D across the boundaries between regions 346C and 348D due to the anneal. In other words, in the example depicted in figure 3C, some of the implanted dopants will move from region 346C into region 348C and from 348C into region 348D, and the net result will be a dopant gradient between the OG side 350 and TX side 330 of the storage gate implant 345C, in accordance with the teachings of this disclosure.

Thus, according to the teachings of this disclosure, with an increasing number of implants of dopants from the transfer gate side 330 toward the output gate side 350 into the storage gate implant 345C as shown in the example of fig. 3C, an effective gradient profile of the storage gate implant 345C is provided. Thus, according to the teachings of this disclosure, the effective doping level at the transfer gate side 330 of the storage gate implant 345C is less than the effective doping level at the output gate side 350 of the storage gate implant 345C. Thus, with a gradient doping profile of the storage gate implant 345C as shown, a corresponding gradient potential profile is formed. As shown in fig. 3C, the electron potential 342 in the storage gate implant 345C decreases from the transfer gate side 330 to the output gate side 350, which forms a potential ramp in the storage gate implant 345C that prevents electrons from being trapped at the transfer gate side 330 and effectively pushing electrons in the storage gate toward the output gate side 350 before being transferred to the floating diffusion, according to the teachings of the present invention. Thus, according to the teachings of this disclosure, the gradient profile in the storage gate implant 345C reduces the storage gate electron density near the transfer gate side 330 of the storage gate implant 345C and reduces the storage gate transfer lag.

Figure 4 is a diagram illustrating one example of an imaging system 491 that includes a pixel array with pixel cells that include storage gate implants having gradient profiles, according to the teachings of this disclosure. As shown in the depicted example, the imaging system 491 includes a pixel array 492 coupled to a control circuit 498 and readout circuitry 494, the readout circuitry 494 being coupled to functional logic 496.

In one example, the pixel array 492 is a two-dimensional (2D) array of image sensor pixels (e.g., pixels P1, P2, P3, …, Pn). Note that pixel cells P1, P2, … Pn in pixel array 492 may be examples of pixel cell 100 of fig. 1 and/or pixel cell 200 of fig. 2, and that similarly named and numbered elements mentioned below are coupled and function similarly as described above. As illustrated, each pixel cell is arranged into one row (e.g., row R1-Ry) and one column (e.g., column C1-Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc.

In one example, after each pixel cell P1, P2, P3, …, Pn has acquired its image data or image charge, the image data is readout by readout circuitry 494 and then transferred to function logic 496. In various examples, readout circuitry 494 can include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or others. Function logic 496 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry 494 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a serial readout or a simultaneous full parallel readout of all pixels.

In one example, the control circuit 498 is coupled to the pixel array 492 to control an operating characteristic of the pixel array 492. In one example, control circuit 498 may generate a shutter signal for controlling image acquisition for each pixel cell. In the example, the global shutter signal simultaneously enables all of the pixel cells P1, P2, P3, … Pn within the pixel array 492 to simultaneously enable all of the pixel cells in the pixel array 492 to simultaneously transfer image charge from each respective photodiode during a single acquisition window.

The above description of illustrated examples of the invention, including what is described in the summary, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications can be made without departing from the broader spirit and scope of the invention. Indeed, it should be understood that specific example voltages, currents, frequencies, power range values, times, etc., are provided for purposes of explanation, and that other values may also be employed in other embodiments and examples in accordance with the teachings of this disclosure.

These modifications can be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (27)

1. A pixel cell, comprising:

a storage transistor disposed in a semiconductor substrate, the storage transistor comprising: a storage gate disposed over the semiconductor substrate; and a storage gate implant annealed and having a gradient profile in the semiconductor substrate below the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate;

a transfer transistor disposed in the semiconductor substrate and coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor, the transfer transistor including a transfer gate disposed over the semiconductor substrate; and

an output transistor disposed in the semiconductor substrate and coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a readout node, the output transistor including an output gate disposed over the semiconductor substrate.

2. The pixel cell of claim 1, wherein the storage gate implant has a plurality of fingers defined on a transfer gate side of the storage gate implant, wherein gaps are defined between the plurality of fingers.

3. The pixel cell of claim 2, wherein a ratio of a width of the gap to a width of the plurality of fingers varies.

4. The pixel cell of claim 2, wherein a ratio of a width of the gap to a width of the plurality of fingers is fixed.

5. The pixel cell of claim 1, wherein the storage gate implant has a graded dopant profile such that a doping concentration of the storage gate implant on a transfer gate side of the storage gate implant is less than a doping concentration of the storage gate implant on an output gate side of the storage gate implant.

6. The pixel cell of claim 1, wherein the storage gate implant has a gradient potential profile such that a potential ramp in the storage gate implant pushes electrons in the storage gate implant toward an output gate side of the storage gate implant.

7. The pixel cell of claim 1, wherein a transfer gate side of the storage gate implant proximate the storage gate implant has a reduced storage gate electron density relative to an output gate side of the storage gate implant.

8. The pixel cell of claim 1, wherein the storage gate implant comprises a plurality of regions, wherein each of the plurality of regions of the storage gate implant has a different doping concentration, wherein the doping concentration of each of the plurality of regions of the storage gate implant increases from a transfer gate side of the storage gate implant to an output gate side of the storage gate implant.

9. The pixel cell of claim 1, wherein the transfer gate, the storage gate, and the output gate comprise polysilicon.

10. The pixel cell of claim 1, further comprising a gate oxide disposed between the semiconductor substrate and the transfer gate, the storage gate, and the output gate.

11. The pixel cell of claim 1, wherein said readout node comprises a floating diffusion disposed in said semiconductor substrate.

12. The pixel cell of claim 1, wherein said image charge comprises electrons.

13. The pixel cell of claim 1, wherein the storage gate implant comprises an N-type dopant.

14. The pixel cell of claim 1, further comprising:

a reset transistor disposed in the semiconductor substrate and coupled to the readout node;

an amplifier transistor disposed in the semiconductor substrate having an amplifier gate coupled to the sense node; and

a row select transistor disposed in the semiconductor substrate, coupled between a bit line and the amplifier transistor.

15. The pixel cell of claim 1, further comprising a shutter gate transistor disposed in the semiconductor substrate and coupled to the photodiode to selectively deplete the image charge from the photodiode.

16. An imaging system, comprising:

a pixel array of pixel cells, wherein each of the pixel cells includes:

a storage transistor disposed in a semiconductor substrate, the storage transistor comprising: a storage gate disposed over the semiconductor substrate; and a storage gate implant annealed and having a gradient profile in the semiconductor substrate below the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate;

a transfer transistor disposed in the semiconductor substrate and coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor, the transfer transistor including a transfer gate disposed over the semiconductor substrate; and

an output transistor disposed in the semiconductor substrate and coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a readout node, the output transistor including an output gate disposed over the semiconductor substrate;

control circuitry coupled to the pixel array to control operation of the pixel array; and

readout circuitry coupled to the pixel array to readout image data from a plurality of pixels.

17. The imaging system of claim 16, wherein the control circuitry is coupled to selectively send a global shutter signal to the pixel array to simultaneously enable all of the pixel cells in a pixel array to simultaneously transfer the image charge from each respective photodiode during a single acquisition window.

18. The imaging system of claim 16, wherein the storage gate implant has a plurality of fingers defined on a transfer gate side of the storage gate implant, wherein gaps are defined between the plurality of fingers.

19. The imaging system of claim 18, wherein a ratio of a width of the gap to a width of the plurality of fingers is varied.

20. The imaging system of claim 18, wherein a ratio of a width of the gap to a width of the plurality of fingers is fixed.

21. The imaging system of claim 16, wherein the storage gate implant has a graded dopant profile such that a doping concentration of the storage gate implant on a transfer gate side of the storage gate implant is less than a doping concentration of the storage gate implant on an output gate side of the storage gate implant.

22. The imaging system of claim 16, wherein the storage gate implant has a gradient potential profile such that a potential ramp in the storage gate implant pushes electrons in the storage gate implant toward an output gate side of the storage gate implant.

23. The imaging system of claim 16, wherein a transfer gate side of the storage gate implant proximate the storage gate implant has a reduced storage gate electron density relative to an output gate side of the storage gate implant.

24. The imaging system of claim 16, wherein the storage gate implant comprises a plurality of regions, wherein each of the plurality of regions of the storage gate implant has a different doping concentration, wherein the doping concentration of each of the plurality of regions of the storage gate implant increases from a transfer gate side of the storage gate implant to an output gate side of the storage gate implant.

25. The imaging system of claim 16, wherein the readout node comprises a floating diffusion disposed in the semiconductor substrate.

26. The imaging system of claim 16, wherein each of the pixel cells further comprises:

a reset transistor disposed in the semiconductor substrate and coupled to the readout node;

an amplifier transistor disposed in the semiconductor substrate having an amplifier gate coupled to the sense node; and

a row select transistor disposed in the semiconductor substrate, coupled between a bit line and the amplifier transistor.

27. The imaging system of claim 16, wherein each of the pixel cells further comprises a shutter gate transistor disposed in the semiconductor substrate and coupled to the photodiode to selectively deplete the image charge from the photodiode.