HK1218349B - Photosensor with channel region having center contact - Google Patents

Description

Light sensor having a channel region with a center contact

Technical Field

The present invention relates generally to semiconductor devices, and more particularly, the present invention is directed to image sensors implemented in semiconductor devices.

Background Art

Image sensors have become ubiquitous. They are widely used in digital cameras, cellular phones, security cameras, as well as in medicine, automobiles, and many other applications. The technology used to manufacture image sensors, and more specifically, the technology used to manufacture complementary metal oxide semiconductor (CMOS) image sensors (CIS), has continued to advance rapidly. For example, demands for higher resolution and lower power consumption have driven further miniaturization and integration of these image sensors.

A typical CMOS image sensor pixel cell is implemented using a three-transistor (3T) or four-transistor (4T) design. For example, a 4T pixel cell design typically includes a transfer transistor for transferring image charge to a floating diffusion region, a transistor for amplifying the signal on the floating diffusion region into an output signal, a transistor for resetting the charge in the floating diffusion region, and a transistor for selecting the pixel for readout. A challenge faced by pixel cells with transfer transistors is that dark current can be generated under the gate of the transfer transistor during the transfer of charge to the floating diffusion region. In addition, a certain amount of charge may be left behind when the charge is transferred to the floating diffusion region, which can increase image lag and reduce image quality. Furthermore, the inclusion of an additional transfer transistor takes up valuable chip real estate and reduces the fill factor of the image sensor.

Summary of the Invention

In one aspect, the present application relates to a pixel cell. The pixel cell includes: a semiconductor substrate having a first doping polarity; a charge accumulation region having a second doping polarity completely buried in the semiconductor substrate below a first side surface of the semiconductor substrate, wherein the second doping polarity is opposite to the first doping polarity, wherein the charge accumulation region is coupled to accumulate image charges in response to light directed through a second side surface of the semiconductor substrate, wherein the second side surface is opposite to the first side surface; a channel region disposed in the semiconductor substrate between the first side surface and the charge accumulation region, wherein a variable resistance of the channel region is responsive to the image charges accumulated in the charge accumulation region; and a center contact coupled to a center portion of the channel region through the first side surface to provide a radial current path through the channel region between the center portion of the channel region and a periphery of the channel region surrounding the charge accumulation region to the semiconductor substrate, wherein a readout signal responsive to the image charges accumulated in the charge accumulation region is coupled to be provided at the center contact.

In another aspect, the present application relates to an imaging sensor system comprising: a pixel array having a plurality of pixel cells disposed in a semiconductor substrate having a first doping polarity; a control circuit coupled to the pixel array to control operation of the pixel array; and a readout circuit coupled to the pixel array to read out a readout signal from each of the plurality of pixel cells. Each of the plurality of pixel cells includes: a charge accumulation region having a second doping polarity completely buried in the semiconductor substrate below a first side surface of the semiconductor substrate, wherein the second doping polarity is opposite to the first doping polarity, wherein the charge accumulation region is coupled to accumulate image charges in response to light directed through a second side surface of the semiconductor substrate, wherein the second side surface is opposite to the first side surface; a channel region disposed in the semiconductor substrate between the first side surface and the charge accumulation region, wherein a variable resistance of the channel region is responsive to the image charges accumulated in the charge accumulation region; and a center contact coupled to a center portion of the channel region through the first side surface to provide a radial current path through the channel region between the center portion of the channel region and a periphery of the channel region around the charge accumulation region to the semiconductor substrate, wherein a readout signal responsive to the image charges accumulated in the charge accumulation region is coupled to be provided at the center contact.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the different views unless otherwise specified.

1 is a diagram illustrating one example of an imaging system including an example image sensor having an example pixel array with pixel cells having a radial channel region with a fully buried depletion region in accordance with the teachings of the present invention.

2 is a schematic diagram illustrating one example of a pixel cell having a radial channel region with a fully buried depletion region in accordance with the teachings of the present invention.

3A is a cross-sectional diagram illustrating an example pixel cell having a variable resistance in a radial channel region with a fully buried depletion region in accordance with the teachings of the present invention.

3B is a cross-sectional diagram illustrating another example pixel cell having a variable resistance in a radial channel region with a fully buried depletion region in accordance with the teachings of the present invention.

4 is a top view illustrating one example of a radial channel region of a pixel cell according to the teachings of the present invention.

Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will appreciate that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present invention. Furthermore, to facilitate an understanding of these various embodiments of the present invention, common but well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention can be practiced without employing these specific details. In other cases, well-known materials or methods have not been described in detail to avoid obscuring the present invention.

References throughout this specification to "one embodiment," "an embodiment," "an instance," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "an instance," or "an example" in multiple places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, in one or more embodiments or examples, the particular features, structures, or characteristics may be combined in any suitable combinations and/or subcombinations. The particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it should be understood that the figures provided herein are for explanation purposes to persons of ordinary skill in the art and are not necessarily drawn to scale.

As will be discussed, an example image sensor according to the teachings of the present invention eliminates the need for a transfer transistor with a pixel cell structure that includes a semiconductor substrate characterized by a completely buried charge accumulation region that generates and modulates a completely buried depletion region below the surface of the semiconductor substrate in response to incident light. The buried depletion region overlaps with a radial channel region to change the resistance of the radial channel region, which is used to output a readout signal of the pixel cell in response to the incident light in accordance with the teachings of the present invention. Because a transfer transistor is not included in the example pixel cell, dark current is reduced because there is no longer a transfer transistor gate (beneath which charge is transferred to a floating diffusion region). Furthermore, in accordance with the teachings of the present invention, because the depletion region of the example pixel cell is completely buried and does not contact the surface of the semiconductor substrate, dark current resulting from the depletion region contacting the surface of the semiconductor substrate is further reduced.

For illustration, FIG1 is a diagram illustrating an example of an imaging system 100 including an example image sensor in accordance with the teachings of the present invention. As shown in the depicted example, imaging system 100 includes a pixel array 102, readout circuitry 104, function logic 106, and control circuitry 108. Pixel array 102 is a two-dimensional (2D) array of imaging sensors or pixel cells (e.g., pixels P1, P2, ..., Pn). In one example, each pixel cell is a complementary metal oxide semiconductor (CMOS) imaging pixel. As illustrated, each pixel cell is arranged into rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to capture image data of a person, location, object, etc., which can then be used to reproduce a 2D image of the person, location, object, etc. As will be discussed in further detail below, in one example, each pixel cell is implemented in accordance with the teachings of the present invention in a semiconductor substrate without transfer transistors but having a radial channel region with a fully buried depletion region.

In one example, after each pixel cell has accumulated its image data or image charge, the image data is read out by readout circuitry 104 via column bit lines 110 and then transferred to function logic 106. In various examples, readout circuitry 104 may also include additional amplification circuitry, additional analog-to-digital (ADC) conversion circuitry, or other circuitry. Function logic 106 may simply store the image data or even manipulate the image data by applying image post-processing effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or other). In one example, readout circuitry 104 may read out image data one row at a time along readout column bit lines 110 (illustrated), or may use a variety of other techniques (not illustrated), such as serial readout or fully parallel readout of all pixel cells simultaneously.

In one example, control circuitry 108 is coupled to pixel array 102 to control operational characteristics of pixel array 102. For example, control circuitry 108 can generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal that simultaneously enables all pixel cells within pixel array 102 to simultaneously capture image data corresponding to all pixel cells during a single acquisition window. In another example, the shutter signal is a rolling shutter signal that sequentially enables each row, column, or group of pixels during successive acquisition windows.

FIG2 is a schematic diagram illustrating an example of a pixel cell 212 of pixel array 202 in accordance with the teachings of the present invention. It should be understood that pixel cell 212 and the pixel array of FIG2 can be one of the pixel cells (e.g., pixels P1, P2, ..., Pn) of FIG1 and an example implementation of pixel array 102, and that similarly named and numerically labeled elements mentioned below couple and function similarly as described above. As shown in the example depicted in FIG2 , pixel cell 212 includes a photodiode PD 214 for accumulating image charge, a junction field effect transistor (JFET) 222, a reset transistor 218, a row select transistor 224, and a constant current source 226 coupled to bit line 210 and row select transistor 224, as shown. As will be discussed, photodiode PD 214, in conjunction with JFET 222, forms an active pixel structure in accordance with the teachings of the present invention. During operation, photodiode PD 214 accumulates image charge in response to incident light 216 during an integration time. The accumulated image charge is coupled as an input signal to the gate of JFET 222. The drain of JFET 222 is coupled to a fixed potential (which is ground terminal 252 in the depicted example) such that JFET 222 is coupled in a common drain configuration or as a source follower transistor, where the readout signal is thus output at the source of JFET 222. As will be discussed in further detail below, in accordance with the teachings of the present invention, JFET 222 is implemented with a radial channel region having a fully buried depletion region, which reduces dark current generation.

As shown in the illustrated example, reset transistor 218 is coupled between a reset voltage _VREST and the source terminal of JFET 222 to reset pixel cell 212 (e.g., discharge/charge photodiode PD214 to a preset voltage _VREST ) in response to a reset signal RST before integration. Row select transistor 224 selectively couples the output of pixel cell 212 to readout column bit line 210 in response to a row select signal RS. In one example, the RST signal and the RS signal may be generated by a control circuit, such as, for example, control circuit 108 discussed above in FIG1 . It should be appreciated that, in accordance with the teachings of the present invention, pixel cell 212 is implemented without a transfer transistor, which reduces the overall transistor count and improves fill factor.

FIG3A is a cross-sectional diagram illustrating an example pixel cell 312A having a variable resistance in a radial channel region with a fully buried depletion region in accordance with the teachings of the present invention. It should be understood that pixel cell 312A as shown in FIG3A can be an example implementation of one of the pixel cells (e.g., pixels P1, P2, ..., Pn) of FIG1 and/or pixel cell 212 of FIG2, and that similarly named and similarly numbered elements mentioned below couple and function similarly as described above.

As shown in the example depicted in FIG3A , pixel cell 312A includes a semiconductor substrate 328 having a first doping polarity. For example, in the depicted example, semiconductor substrate 328 has a P-doping polarity. A charge accumulation region 330 is completely buried in semiconductor substrate 328 and is located below a first side surface 332 of semiconductor substrate 328. In the illustrated example, first side surface 332 is a front side surface of semiconductor substrate 328.

In the example, the charge accumulation region 330 is doped with a dopant having a polarity opposite to that of the dopant of the semiconductor substrate 328. Thus, in the example where the semiconductor substrate 328 has a P-doping, the charge accumulation region 330 has an N-doping. The charge accumulation region 330 is coupled to accumulate image charge in response to incident light 316 directed through a second side surface 334, which is a surface opposite the first side surface 332. For example, in the depicted example, the second side surface 334 is the backside surface of the semiconductor substrate 328. The amount of image charge generated in the charge accumulation region 330 is a function of the photogenerated current generated in the charge accumulation region 330 in response to the incident light 316 and the integration time.

In this example, the buried depletion region 350 is generated near the charge accumulation region 330 in response to image charges generated in the charge accumulation region 330. The buried depletion region 350 is completely buried below the first side surface 332 of the semiconductor substrate 328. The size of the buried depletion region 350 in the semiconductor substrate 328 changes in response to the amount of image charges generated in the charge accumulation region 330.

The channel region 336 is disposed in the semiconductor substrate 328 between the first side surface 332 and the charge accumulation region 330. In one example, the channel region 336 is doped with a dopant having the same polarity as the dopant of the semiconductor substrate 328, but at a higher doping concentration. Thus, in an example where the semiconductor substrate 328 has a P- doping, the channel region 336 has a P+ doping. As the size of the buried depletion region 350 in the semiconductor substrate 328 increases, the amount of overlap between the buried depletion region 350 and the channel region 336 increases. As the size of the buried depletion region 350 decreases, the amount of overlap between the buried depletion region 350 and the channel region 336 decreases.

As illustrated in the depicted example, the center contact 340 is coupled to a central portion 342 of the channel region 336 via the first side surface 332. Thus, a current path for a radial current I _RADIAL 346 is provided through the channel region 336 between the central portion 342 of the channel region 336 and a periphery 344 of the channel region 336 surrounding the charge accumulation region 330 to the semiconductor substrate 328, as shown. In accordance with the teachings of the present invention, the resistance of the radial current path through the channel region 336 changes in response to the amount of overlap of the buried depletion region 350 in response to the amount of image charge in the charge accumulation region 330. This variable resistance of the radial current path through the channel region 336 is represented in FIG. 3A as a variable resistance R _VAR 338 between the central portion 342 of the channel region 336 and the periphery 344 of the channel region 336.

In this example, as the amount of overlap between buried depletion region 350 and channel region 336 increases, the resistance of variable resistor R _VAR 338 increases until the overlap between buried depletion region 350 and channel region 336 completely "pinches off" channel region 336, at which point channel region 336 is depleted of charge carriers and the conductance in channel region 336 is very low. Consequently, variable resistor R _VAR 338 is very high and radial current I _RADIAL 346 drops to substantially zero. It should be appreciated that, in accordance with the teachings of the present invention, channel region 336 can be completely "pinched off" by buried depletion region 350 without ever reaching first side surface 332, which can reduce dark current. As the amount of overlap between buried depletion region 350 and channel region 336 decreases, the resistance of variable resistor R _VAR 338 correspondingly decreases.

In one example, the amount of overlap between buried depletion region 350 and channel region 336 is a function of the amount of image charge in charge accumulation region 330. Accordingly, in accordance with the teachings of the present invention, the magnitude of radial current I _RADIAL 346 is a function of the amount of image charge in charge accumulation region 330. Thus, as the amount of image charge in charge accumulation region 330 increases, radial current I _RADIAL 346 increases. As the amount of image charge in charge accumulation region 330 decreases, radial current I _RADIAL 346 decreases until channel region 336 is completely "pinched off," at which point radial current I _RADIAL 346 drops to substantially zero.

Because variable resistance R _VAR 338 and radial current I _RADIAL 346 are responsive to image charge in charge accumulation region 330 as described above, a readout signal 348 responsive to the image charge accumulated in charge accumulation region 330 is coupled and provided at center contact 340 through row select transistor 324 in accordance with the teachings of the present invention. In one example, row select transistor 324 is coupled between a bit line output of the pixel cell (e.g., bit line 210 of FIG. 2 ) and center contact 340. As shown in the example of FIG. 3A , row select transistor 324 is coupled to output readout signal 348 from center contact 340 to the bit line output in response to a row select signal RS coupled to row select transistor 324. In one example, a constant current source 326 may be coupled to the output of pixel cell 312A at row select transistor 324, as shown.

The example depicted in FIG3A also shows reset transistor 318 coupled between center contact 340 and reset voltage V _RESET . In operation, reset transistor 318 is coupled to reset the image charge accumulated in accumulation region 330 in response to a reset signal RST coupled to reset transistor 318 . For example, reset signal RST can be used to reset pixel cell 312A prior to integration of light 316 . Thus, in accordance with the teachings of the present invention, reset transistor 318 is turned on during a reset operation, coupling center contact 340 to reset voltage V _RESET and extracting substantially all of the accumulated image charge in charge accumulation region 330 through center contact 340 . In accordance with the teachings of the present invention, at this point, the image charge in charge accumulation region 330 is completely depleted, causing buried depletion region 350 to grow larger to "pinch off" channel region 336 , thereby depleting channel region 336 of charge carriers and increasing the resistance of variable resistor R _VAR 338 after reset and prior to integration.

FIG3B is a cross-sectional view illustrating another example of a pixel cell 312B having a JFET with a variable resistance in a radial channel region and a fully buried depletion region in accordance with the teachings of the present invention. It should be understood that the pixel cell 312B shown in FIG3B can be an example implementation of one of the pixel cells of FIG1 (e.g., pixels P1, P2 ... Pn) and/or the pixel cell 212 of FIG2 and/or the pixel cell 312A of FIG3A, and that the similarly named and similarly numbered elements mentioned below are coupled and function similarly as described above. Therefore, for the sake of brevity, the similarly named and similarly numbered elements do not need to be described in detail again.

One difference between pixel cell 312B of FIG3B and pixel cell 312A of FIG3A is that variable resistance R _VAR 338 of channel region 336 illustrated in FIG3A is represented by JFET 322 in channel region 336 as shown in pixel cell 312B of FIG3B . As shown in the example depicted in FIG3B , a central portion 342 of channel region 336 is represented by or coupled to the source terminal of JFET 322, and a periphery 344 of channel region 336 is represented by or coupled to the drain terminal of JFET 322. Therefore, it should be understood that the channel region 336 between central portion 342 of channel region 336 and periphery 344 of channel region 336 is therefore the channel of JFET 322. Thus, in accordance with the teachings of the present invention, the gate of JFET 322 is responsive to or coupled to charge accumulation region 330, such that the variable resistance of the channel of JFET 322 is responsive to the image charge accumulated in accumulation region 330. As shown in the example depicted in FIG3B , the semiconductor substrate is coupled to a fixed potential (which is ground terminal 352 in the depicted example), such that the drain of JFET 322 is coupled to ground terminal 352 through semiconductor substrate 328. Thus, in accordance with the teachings of the present invention, JFET 322 is coupled in a common-drain configuration or is a source-follower transistor, wherein a readout signal 348 is output at the source of JFET 322 through center contact 340 and row select transistor 324.

It should be noted that the operation of pixel cell 312B is similar to that of pixel cell 312A in accordance with the teachings of the present invention. For example, reset transistor 318 is coupled to reset the image charge in charge accumulation region 330 prior to integration. Furthermore, the value of the variable resistance in channel region 336 and/or the channel of JFET 322 is responsive to the amount of image charge in charge accumulation region 330, which changes the amount of overlap between buried depletion region 350 and channel region 336 and/or the channel of JFET 322. Thus, in accordance with the teachings of the present invention, readout signal 348 is output by pixel cell 312B in response to the amount of image charge generated in charge accumulation region 330 in response to incident light 316.

FIG4 is a top view illustrating an example of a pixel cell 412, showing radial current flow in a radial channel region 436, in accordance with the teachings of the present invention. It should be understood that the pixel cell 412 of FIG4 can be an example implementation of one of the pixel cells of FIG1 (e.g., pixels P1, P2, ..., Pn) and/or the pixel cell 212 of FIG2 and/or the pixel cell 312A of FIG3A and/or the pixel cell 312B of FIG3B, and that similarly named and similarly numbered elements mentioned below are coupled and function similarly as described above. As shown, the periphery 444 of the channel region 436 shown in FIG4 surrounds the central portion 442 of the channel region 436. Thus, in accordance with the teachings of the present invention, the channel region 436 through which the radial current I _RADIAL 446 flows is a radial channel region having a radial current path disposed in the channel region 436 between the central portion 442 of the channel region 436 and extending outward to the periphery 444 of the channel region 436. In one example, the central portion 442 corresponds to or is coupled to a source terminal of a JFET (eg, JFET 322 of FIG. 3B ), and the periphery 444 corresponds to or is coupled to a drain terminal of the JFET (eg, JFET 322 of FIG. 3B ).

The above description of the illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific embodiments and examples of the invention are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the invention.

These modifications may be made to examples of the present invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope is to be determined entirely by the appended claims, which are to be construed in accordance with recognized principles of claim interpretation. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims (26)

1. A pixel unit, comprising: A semiconductor substrate having a first doping polarity; A charge accumulation region having a second doping polarity is completely buried in the semiconductor substrate below a first side surface of the semiconductor substrate, wherein the second doping polarity is opposite to the first doping polarity, wherein the charge accumulation region is coupled to accumulate image charge in response to light directed through a second side surface of the semiconductor substrate, wherein the second side surface is opposite to the first side surface; A channel region disposed in the semiconductor substrate between the first side surface and the charge accumulation region, wherein the variable resistance of the channel region is responsive to the image charge accumulated in the charge accumulation region; and A central contact, coupled to a central portion of the channel region via the first side surface, provides a radial current path from the channel region to the semiconductor substrate between the central portion of the channel region and the periphery of the channel region surrounding the charge accumulation region, wherein a readout signal in response to image charge accumulated in the charge accumulation region is coupled to be provided at the central contact, wherein the central contact is the only contact in the pixel unit disposed on the first side surface of the semiconductor substrate, and wherein the radial current path extends from the central portion toward the periphery of the channel region in different directions. 2. The pixel unit of claim 1, further comprising a buried depletion region responsive to the image charge, wherein the buried depletion region is entirely generated below the first side surface and overlaps with the channel region adjacent to the charge accumulation region to adjust the variable resistance of the channel region in response to the image charge accumulated in the charge accumulation region. 3. The pixel unit of claim 1, wherein the periphery of the channel region surrounds the central portion of the channel region such that the channel region is a radial channel region having the radial current path extending 360° from the central portion toward the periphery of the channel region. 4. The pixel unit of claim 1, wherein the central portion of the channel region is a first terminal of a junction field-effect transistor (JFET), wherein the periphery of the channel region is a second terminal of the JFET, wherein the channel region between the central portion of the channel region and the periphery of the channel region is the channel of the JFET, and wherein the gate of the JFET is coupled to the charge accumulation region such that the variable resistance of the channel of the JFET responds to the image charge accumulated in the accumulation region. 5. The pixel unit according to claim 4, wherein the first and second terminals of the JFET include the source and drain of the JFET. 6. The pixel unit of claim 5, wherein the drain of the JFET is coupled to a first potential through the semiconductor substrate, such that the JFET is a JFET coupled to a source follower. 7. The pixel unit of claim 1, further comprising a reset transistor coupled between the central contact and a reset voltage, wherein the reset transistor is coupled to reset the image charge accumulated in the accumulation region in response to a reset signal coupled to the reset transistor. 8. The pixel unit of claim 1, further comprising a row selection transistor coupled between a bit line output of the pixel unit and the center contact, wherein the row selection transistor is coupled to output the readout signal from the center contact to the bit line output in response to a row selection signal coupled to the row selection transistor. 9. The pixel unit of claim 8, further comprising a constant current source coupled to the bit line output of the pixel unit. 10. The pixel unit of claim 1, wherein the semiconductor substrate has the first doping polarity of a first doping concentration, and wherein the channel region has the first doping polarity of a second doping concentration, wherein the second doping concentration is greater than the first doping concentration. 11. The pixel unit according to claim 1, wherein the first doping polarity is p-type doping polarity, and wherein the second doping polarity is n-type doping polarity. 12. The pixel unit of claim 1, wherein the first side is the front side of the semiconductor substrate, and wherein the second side is the rear side of the semiconductor substrate. 13. The pixel unit of claim 3, wherein the radial current path extends from the periphery of the channel region toward the second side surface. 14. An imaging sensor system comprising: A pixel array having a plurality of pixel units disposed in a semiconductor substrate having a first doping polarity, wherein each of the plurality of pixel units comprises: A charge accumulation region having a second doping polarity is completely buried in the semiconductor substrate below a first side surface of the semiconductor substrate, wherein the second doping polarity is opposite to the first doping polarity, wherein the charge accumulation region is coupled to accumulate image charge in response to light directed through a second side surface of the semiconductor substrate, wherein the second side surface is opposite to the first side surface; A channel region disposed in the semiconductor substrate between the first side surface and the charge accumulation region, wherein the variable resistance of the channel region is responsive to the image charge accumulated in the charge accumulation region; and A central contact, coupled to a central portion of the channel region via a first side surface, provides a radial current path from the channel region to the semiconductor substrate between the central portion of the channel region and the periphery of the channel region surrounding the charge accumulation region, wherein a readout signal in response to image charge accumulated in the charge accumulation region is coupled to be provided at the central contact, wherein the central contact is the only contact in an individual pixel unit disposed on the first side surface of the semiconductor substrate, and wherein the radial current path extends from the central portion toward the periphery of the channel region in different directions; Control circuitry coupled to the pixel array to control the operation of the pixel array; and A readout circuit coupled to the pixel array to read out the readout signal from each of the plurality of pixel units. 15. The imaging sensor system of claim 14, further comprising functional logic coupled to the readout circuitry to store the readout signal from each of the plurality of pixel units. 16. The imaging sensor system of claim 14, wherein each of the plurality of pixel units further includes a buried depletion region responsive to the image charge, wherein the buried depletion region is entirely generated below the first side surface and overlaps with the channel region adjacent to the charge accumulation region to adjust the variable resistance of the channel region in response to the image charge accumulated in the charge accumulation region. 17. The imaging sensor system of claim 14, wherein the periphery of the channel region surrounds the central portion of the channel region such that the channel region is a radial channel region having the radial current path disposed in the channel region between the central portion of the channel region and the periphery of the channel region. 18. The imaging sensor system of claim 14, wherein the central portion of the channel region is a first terminal of a junction field-effect transistor (JFET), wherein the periphery of the channel region is a second terminal of the JFET, wherein the channel region between the central portion of the channel region and the periphery of the channel region is the channel of the JFET, and wherein the gate of the JFET is coupled to the charge accumulation region such that the variable resistance of the channel of the JFET responds to the image charge accumulated in the accumulation region. 19. The imaging sensor system of claim 18, wherein the first and second terminals of the JFET include the source and drain of the JFET. 20. The imaging sensor system of claim 19, wherein the drain of the JFET is coupled to a first potential through the semiconductor substrate such that the JFET is a JFET coupled to a source follower. 21. The imaging sensor system of claim 14, wherein each of the plurality of pixel units further comprises a reset transistor coupled between the central contact and a reset voltage, wherein the reset transistor is coupled to reset the image charge accumulated in the accumulation region in response to a reset signal coupled to the reset transistor. 22. The imaging sensor system of claim 14, wherein each of the plurality of pixel units further comprises a row selection transistor coupled between a bit line output of the pixel unit and the center contact, wherein the row selection transistor is coupled to output the readout signal from the center contact to the bit line output in response to a row selection signal coupled to the row selection transistor. 23. The imaging sensor system of claim 22, wherein each of the plurality of pixel units further comprises a constant current source coupled to the bit line output of the pixel unit. 24. The imaging sensor system of claim 14, wherein the semiconductor substrate has a first doping polarity of a first doping concentration, and wherein the channel region of each of the plurality of pixel units has a first doping polarity of a second doping concentration, wherein the second doping concentration is greater than the first doping concentration. 25. The imaging sensor system of claim 14, wherein the first doping polarity is p-type doping polarity, and wherein the second doping polarity is n-type doping polarity. 26. The imaging sensor system of claim 14, wherein the first side is the front side of the semiconductor substrate, and wherein the second side is the rear side of the semiconductor substrate.