HK1210557B - Methods and apparatuses for processing video data - Google Patents

Description

Method and apparatus for processing video data

This application claims U.S. provisional application No. 61/749,866, filed on 7/1/2013, the entire contents of which are incorporated herein by reference.

Technical Field

This disclosure relates to video coding and video processing, and more specifically to techniques for signaling timing information in video information.

Background

Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, Personal Digital Assistants (PDAs), laptop or desktop computers, tablet computers, electronic book readers, digital cameras, digital recording devices, digital media players, video gaming devices, video gaming consoles, cellular or satellite radio telephones, so-called "smart phones," video teleconferencing devices, video streaming devices, and the like. Digital video devices implement video compression techniques such as those described in the standards defined by MPEG-2, MPEG-4, ITU-T H.263, or ITU-T H.264/MPEG-4 part 10 Advanced Video Coding (AVC), the High Efficiency Video Coding (HEVC) standard, and extensions of these standards. Video devices may transmit, receive, encode, decode, and/or store digital video information more efficiently by implementing such video compression techniques.

Video compression techniques perform spatial (intra-picture) prediction and/or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video frame or a portion of a video frame) may be partitioned into video blocks, which may also be referred to as treeblocks, Coding Units (CUs), and/or coding nodes. Video blocks in an intra-coded (I) slice of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in inter-coded (P or B) slices of a picture may use spatial prediction with respect to reference samples in neighboring blocks in the same picture or temporal prediction with respect to reference samples in other reference pictures. A picture may be referred to as a frame and a reference picture may refer to a reference frame.

Spatial or temporal prediction utilizes prediction blocks. The residual data represents the pixel differences between the original block to be coded and the prediction block. An inter-coded block is encoded according to a motion vector that points to a block of reference samples that form a prediction block and residual data that indicates the difference between the coded block and the prediction block. An intra-coded block is encoded according to an intra-coding mode and residual data. To achieve further compression, the residual data may be transformed from the pixel domain to a transform domain, thereby generating residual transform coefficients, which may then be quantized. The quantized transform coefficients, initially arranged as a two-dimensional array, may be scanned in order to generate a one-dimensional vector of transform coefficients, and entropy coding may be applied to achieve more compression.

A given coded video sequence encoded into a bitstream includes an ordered sequence of coded pictures. In the h.264/AVC and HEVC standards, the decoding order for coded pictures of a bitstream is equivalent to the ordered sequence. However, the standards also support output orders of decoded pictures that are different than the decoding order, and in such cases, coded pictures are associated with Picture Order Count (POC) values that specify the output order of the pictures in the video sequence.

Video timing information for a video sequence may be signaled in one or more syntax elements of a syntax structure (alternatively referred to as a "parameter set structure" or simply a "parameter set"). The syntax structure may include a Sequence Parameter Set (SPS) that includes coding information that applies to all slices of a coded video sequence. The SPS itself may contain parameters known as Video Usability Information (VUI) which contains Hypothetical Reference Decoder (HRD) information as well as information for enhancing the use of corresponding video sequences for various purposes. The HRD information itself may be signaled using HRD syntax structures that may be included within other syntax structures, such as VUI syntax structures. The syntax structure may also include Video Parameter Sets (VPS) that describe characteristics of the corresponding video sequence, e.g., common syntax elements shared by multiple layers or operation points, and other operation point information that may be common to multiple sequence parameter sets, e.g., HRD information for various layers or sub-layers.

Disclosure of Invention

In general, this disclosure describes techniques for video coding, and more specifically techniques for signaling video information, e.g., to specify picture output timing and/or to define a buffering model, such as a Hypothetical Reference Decoder (HRD). In some examples, the techniques may include: one or more syntax elements defining conditions for the following are signaled directly in a Video Parameter Set (VPS) syntax structure for a coded video sequence or in a Video Usability Information (VUI) part of a Sequence Parameter Set (SPS) syntax structure: signaling a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1.

In one example of this disclosure, a method for coding video data comprises: encoding pictures of a video sequence to generate a coded video sequence comprising the encoded pictures; and signaling timing parameters for the coded video sequence by directly signaling conditions for: signaling, in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1.

In another example of this disclosure, a method for processing video data comprises: receiving a coded video sequence comprising encoded pictures of the video sequence; and receiving timing parameters for the coded video sequence including conditions for: signaling, directly in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1.

In another example, this disclosure describes a device for coding video data, the device comprising a processor configured to: encoding pictures of a video sequence to generate a coded video sequence comprising the encoded pictures; and signaling timing parameters for the coded video sequence by directly signaling conditions for: signaling, in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1.

In another example, this disclosure describes a device for processing video data, the device comprising a processor configured to: receiving a coded video sequence comprising encoded pictures of the video sequence; and receiving timing parameters for the coded video sequence including conditions for: signaling, directly in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1.

In another example, this disclosure describes a device for processing video data, the device comprising: means for receiving a coded video sequence comprising encoded pictures of the video sequence; and means for receiving timing parameters for the coded video sequence including conditions for: signaling, directly in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1.

In another example, this disclosure describes a computer-readable storage medium. The computer-readable storage medium has instructions stored thereon that, when executed, cause one or more processors to: receiving a coded video sequence comprising encoded pictures of the video sequence; and receiving timing parameters for the coded video sequence including conditions for: signaling, directly in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1.

The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

Drawings

FIG. 1 is a block diagram illustrating an example video encoding and decoding system that may utilize the techniques described in this disclosure.

FIG. 2 is a block diagram illustrating an example video encoder that may implement the techniques described in this disclosure.

FIG. 3 is a block diagram illustrating an example video decoder that may implement the techniques described in this disclosure.

Fig. 4 is a block diagram illustrating timing information for an example coding structure for a reference picture set in accordance with the techniques described herein.

FIG. 5 is a flow diagram illustrating an example method of operation in accordance with the techniques described in this disclosure.

6A-6B are flow diagrams illustrating example methods of operation in accordance with the techniques described in this disclosure.

FIG. 7 is a flow diagram illustrating an example method of operation in accordance with the techniques described in this disclosure.

FIG. 8 is a flow diagram illustrating an example method of operation in accordance with the techniques described in this disclosure.

FIGS. 9A-9B are flow diagrams illustrating an example method of operation in accordance with the techniques described in this disclosure.

FIG. 10 is a flow diagram illustrating an example method of operation in accordance with the techniques described in this disclosure.

Detailed Description

This disclosure describes various techniques for video coding, and more specifically relates to techniques for signaling video information, e.g., to specify picture output timing and/or to define buffering or decoding models, such as Hypothetical Reference Decoders (HRDs). In general, "signaling" is used in this disclosure to refer to signaling that occurs within a coded bitstream. The encoder may generate syntax elements to signal information in the bitstream as part of the video encoding process. A decoding device or other video processing device may receive a coded bitstream and interpret syntax elements in the coded bitstream as part of a video decoding process or other video processing.

For example, to indicate output timing for switching from a given picture in a coded video sequence to a next picture ordered according to output, in some cases, timing information for the coded video sequence may signal a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to one. The difference in POC values is equal to one, which may represent the difference between the POC value of a given picture and the POC value of the next picture according to the output ordering (e.g., the POC value of the 2 nd picture and the POC value of the 3 rd picture according to the output ordering). The video timing information may also include a condition that indicates whether the video timing information signals a number of the clock ticks corresponding to a difference in picture order count values equal to one. In other words, only when the condition is true, video timing information signals the number of clock ticks for which the difference in picture order count values is equal to one. In some cases, the condition is not true, so video timing information does not signal the number of the clock ticks corresponding to a difference in picture order count values equal to one. The number of clock ticks may depend on a time scale (corresponding to, for example, an oscillator frequency, such as 27MHz, that defines a time coordinate system in which information is signaled) and the number of time units of a clock operating at a time scale corresponding to one increment of a clock tick counter (referred to as a "clock tick").

In some examples, the techniques of this disclosure may include directly signaling, in a VPS syntax structure or in a VUI part of an SPS syntax structure of a coded video sequence, all syntax elements that define conditions for: signaling the number of clock ticks corresponding to a difference in POC values equal to 1. That is, in some cases, the condition may have one or more dependencies on additional information (i.e., syntax elements) signaled in the VPS syntax structure or in the VUI part of the SPS syntax structure. These syntax elements may include a timing information present flag, as described below.

Video coding standards include ITU-T H.261, ISO/IEC MPEG-1 video, ITU-T H.262, or ISO/IECMPEG-2 video, ITU-T H.263, ISO/IEC MPEG-4 video, and ITU-T H.264 (also referred to as ISO/IEC MPEG-4AVC), including Scalable Video Coding (SVC) extensions and Multiview Video Coding (MVC) extensions thereof.

In addition, there is a new video coding standard, High Efficiency Video Coding (HEVC), developed by the joint collaborative team of video coding (JCT-VC) of the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). The latest working draft of HEVC (and referred to hereinafter as HEVC WD9 or WD9 only) is the "recommended editing improvements for High Efficiency Video Coding (HEVC) text specification draft 9 (SoDIS)" by bloss (Bross) et al, the Video Coding joint collaboration group (JCT-VC) of ITU-T SG16WP3 and ISO/IEC JTC1/SC29/WG11, the 12 th conference: switzerland Geneva, from 14 days 1/2013 to 23 days 1/2013, and available from http:// phenix. int-evry. fr/jct/doc _ end _ user/documents/12_ Geneva/wg11/JCTVC-L0030-v1.zip by 1/7 days 2013.

A recent draft of the HEVC standard (referred to as "HEVC working draft 10" or "WD 10") is described in document JCTVC-L1003v34 by blos et al entitled "High Efficiency Video Coding (HEVC) text specification draft 10(for FDIS & LastCall)", the video coding joint group (JCT-VC) of ITU-T SG16WP3 and ISO/IEC JTC1/SC29/WG11, conference 12: switzerland Innova, 2013, 1, 14 to 23, the draft may be downloaded from http:// phenix. int-evry. fr/jct/doc _ end _ user/documents/12_ Geneva/wg11/JCTVC-L1003-v34. zip.

Another draft of the HEVC standard (referred to herein as "WD 10 version") is described in "editor's proposed corrections to HEVC version 1 (Editors' proposed corrections to HEVC version 1)" by Blos et al, the video coding Joint group (JCT-VC) of ITU-TSG16WP3 and ISO/IEC JTC1/SC29/WG11, conference 13 (Korea, 4 months 2013), which was downloadable from http:// phenix. int-evry. fr/JCT/doc _ end _ user/documents/13_ Incheon/WG11/JCTVC-M0432-v3.zip by 6 months 7 days 2013

HEVC standardization efforts are based on a model of the video coding device known as the HEVC test model (HM). The HM assumes an improvement in the capabilities of current video decoding devices over video decoding devices available during the development of other previous video decoding standards, such as ITU-T h.264/AVC. For example, although h.264 provides nine intra-prediction coding modes, HEVC provides up to thirty-five intra-prediction coding modes. HEVC WD9 and HEVC WD10 are incorporated herein by reference in their entirety.

Video coding standards typically include specifications for video buffering models. In AVC and HEVC, the buffering model is referred to as a Hypothetical Reference Decoder (HRD), which includes buffering models for both the Coded Picture Buffer (CPB) and the Decoded Picture Buffer (DPB). As defined in HEVC WD9, HRD is a hypothetical decoder model that specifies constraints on the variability of a Network Abstraction Layer (NAL) unit stream or conforms to a byte stream that an encoding process can produce.

CPB and DPB behavior is specified mathematically. HRD imposes constraints on different timing, buffer size, and bit rate directly, and constraints on bit stream characteristics and statistics indirectly. The complete HRD parameter set contains five basic parameters: initial CPB removal delay, CPB size, bit rate, initial DPB output delay, and DPB size.

In AVC and HEVC, bitstream conformance and decoder conformance are specified as part of the HRD specification. Although "hypothetical reference decoder" includes the term "decoder," HRD is typically required on the encoder side to guarantee bitstream conformance, and HRD is typically not required on the decoder side. Two types of bitstream or HRD conformance are specified, namely type I and type II. Also, two types of decoder conformance are specified, namely output sequential decoder conformance and output order decoder conformance.

In HEVC WD9, HRD operations require parameters signaled in an HRD _ parameters () syntax structure, buffering period Supplemental Enhancement Information (SEI) messages, picture timing SEI messages, and sometimes also in decoding unit information SEI messages. The hrd _ parameters () syntax structure may be signaled in a Video Parameter Set (VPS), a Sequence Parameter Set (SPS), or any combination thereof.

In HEVC WD9, the hrd _ parameters () syntax structure includes syntax elements for signaling of video timing information, including time scale and number of units in a clock tick. The Video Usability Information (VUI) part of the SPS includes a flag that indicates whether a Picture Order Count (POC) value of each picture in the coded video sequence (except for a first picture in decoding order in the coded video sequence) is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence; if so, the number of clock ticks corresponds to a difference in picture order count value equal to 1.

The relevant syntax and semantics in HEVC WD9 are as follows. Table 1 shows an example video parameter set Raw Byte Sequence Payload (RBSP) syntax structure in accordance with WD 9.

Table 1: example video parameter set RBSP syntax structure

In table 1 above, the syntax element vps _ num _ hrd _ parameters specifies the number of hrd _ parameters () syntax structures present in the video parameter set Raw Byte Sequence Payload (RBSP). In a bitstream conforming to this version of this specification, the value of vps _ num _ hrd _ parameters should be less than or equal to 1. Although values of vps _ num _ hrd _ parameters are required to be less than or equal to 1 in HEVC WD9, the decoder should allow other values of vps _ num _ hrd _ parameters in the range 0 to 1024 (including 0 and 1024) to appear in the syntax.

The syntax element hrd _ op _ set _ idx [ i ] specifies the index of the operation point set to which the ith hrd _ parameters () syntax structure in the Video Parameter Set (VPS) applies in the list of operation point sets specified by the video parameter set. In a bitstream conforming to this version of the specification, the value of hrd _ op _ set _ idx [ i ] should be equal to 0. Although the value of hrd _ op _ set _ idx [ i ] is required to be less than or equal to 1 in HEVC WD9, the decoder should allow other values of hrd _ op _ set _ idx [ i ] in the range 0 to 1023 to appear in the syntax.

The syntax element cprms _ present _ flag [ i ] equal to 1 specifies that HRD parameters common to all sub-layers are present in the ith HRD _ parameters () syntax structure in the video parameter set. cprms _ present _ flag [ i ] equal to 0 specifies that HRD parameters common to all sub-layers are not present in the ith HRD _ parameters () syntax structure in the video parameter set, and the (i-1) th HRD _ parameters () syntax structure in the derived video parameter set is also the same. The cprms _ present _ flag [0] is inferred to be equal to 1.

Table 2 below shows the VUI parameter syntax structure according to WD 9.

Table 2: VUI parameter syntax structure

In table 2 above, syntax element hrd _ parameters _ present _ flag equal to 1 specifies that syntax structure hrd _ parameters () exists in the vui _ parameters () syntax structure. hrd _ parameters _ present _ flag equal to 0 specifies that syntax structure hrd _ parameters () does not exist in the vui _ parameters () syntax structure.

The syntax element poc _ presentation _ to _ timing _ flag equal to 1 indicates that the picture order count value for each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. poc _ presentation _ to _ timing _ flag equal to 0 indicates that the picture order count value for each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) may or may not be proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence.

The syntax element num _ ticks _ poc _ diff _ one _ minus1 plus 1 specifies the number of clock ticks corresponding to a difference in picture order count value equal to 1.

Table 3 below shows an example HRD parameter syntax structure according to WD 9.

Table 3: example HRD parameter syntax structure

In table 3 above, syntax element timing _ info _ present _ flag equal to 1 specifies that num _ units _ in _ tick and time _ scale are present in the hrd _ parameters () syntax structure. If the timing _ info _ present _ flag is equal to 0, num _ units _ in _ tick and time _ scale are not present in the hrd _ parameters () syntax structure. If not, the value of timing _ info _ present _ flag is inferred to be 0.

The syntax element num units in tick is the number of time units of the clock operating at a frequency time scale Hz corresponding to one increment of the clock tick counter (called clock tick). The value of the syntax element num units in tick should be greater than 0. A clock tick is the minimum interval of time that can be represented with coded data when sub _ pic _ cpb _ params _ present _ flag is equal to 0. For example, when the picture rate of the video signal is 25Hz, time scale may be equal to 27,000,000, and num units in tick may be equal to 1,080,000.

The syntax element time scale is the number of time units elapsed in one second. For example, the time coordinate system for measuring time using a 27MHz frequency has a time scale of 27,000,000. The value of the syntax element time scale should be greater than 0.

Timing signaling as specified in HEVC WD9 and as described above may exhibit a number of problems. First, a condition for signaling a syntax element num _ ticks _ poc _ diff _ one _ minus1 is "if (poc _ presentation _ to _ timing _ flag & & timing _ info _ present _ flag)". This condition includes dependencies on two signaled syntax elements: poc _ presentation _ to _ timing _ flag and timing _ info _ present _ flag. However, it is not clear from the HEVC WD9 specification: the timing _ info _ present _ flag for the condition is either a syntax element timing _ info _ present _ flag referring to the hrd _ parameters () syntax structure (if any) in the VUI part of the SPS or a syntax element timing _ info _ present _ flag referring to the hrd _ parameters () syntax structure in the VPS.

In addition, multiple layers or multiple possible bitstream subsets of a scalable video bitstream may share a common value of the time scale and number of units in a clock tick, which is specified in HEVC WD9 in the syntax elements time scale and num units in tick of the hrd parameters () syntax structure, e.g., which may be repeatedly signaled in the VUI part of the SPS and in the VPS. Such repetition, if present in the bitstream, can result in bit wastage.

Furthermore, if a Picture Order Count (POC) value is proportional to the output time of any of several layers of a scalable video bitstream, the POC value is typically proportional to the output time of all layers of the scalable video bitstream. However, the HEVC WD9 specification does not provide for signaling in a scalable video bitstream an indication that the POC value is proportional to the output time of all layers or all possible bitstream subsets of the scalable video bitstream. For example, a "layer" referring to a scalable video bitstream may refer to a scalable layer, a texture view, and/or a depth view. Additionally, although HEVC WD9 specifies that the flag poc _ reporting _ to _ timing _ flag is always signaled in the VUI syntax structure of the SPS, the flag poc _ reporting _ to _ timing _ flag has no utility if the syntax elements time _ scale and num _ units _ in _ tick are also not signaled in the bitstream.

The techniques of this disclosure may address one or more of the above issues, as well as provide other improvements, enabling efficient signaling of parameters for HRD operation. Various examples of such techniques are described herein with reference to HEVC WD9 and its potential improvements. The solution applies to any video coding standard that includes specifications for a video buffering model (e.g., including AVC and HEVC), but for purposes of illustration, is described specifically for HRD parameter signaling defined in HEVC WD9 and modified in accordance with the techniques of this disclosure.

FIG. 1 is a block diagram illustrating an example video encoding and decoding system 10 that may utilize the techniques described in this disclosure. As shown in fig. 1, system 10 includes a source device 12 that generates encoded video data to be decoded by a destination device 14 at a later time. Source device 12 and destination device 14 may comprise any of a wide range of devices, including desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, telephone handsets (e.g., so-called "smart" phones), so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or the like. In some cases, source device 12 and destination device 14 may be equipped for wireless communication.

Destination device 14 may receive encoded video data to be decoded over link 16. Link 16 may comprise any type of media or device capable of moving encoded video data from source device 12 to destination device 14. In one example, link 16 may comprise a communication medium that enables source device 12 to transmit encoded video data directly to destination device 14 in real-time. The encoded video data may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to destination device 14. The communication medium may comprise any wireless or wired communication medium, such as a Radio Frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network (e.g., a local area network, a wide area network, or a global network such as the internet). The communication medium may include routers, switches, base stations, or any other equipment that may be used to facilitate communication from source device 12 to destination device 14.

Alternatively, the encoded data may be output from output interface 22 to storage 34. Similarly, encoded data may be accessed from storage device 34 through an input interface. Storage device 34 may include any of a variety of distributed or locally accessed data storage media such as a hard drive, blu-ray discs, DVDs, CD-ROMs, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data. In another example, storage device 34 may correspond to a file server or another intermediate storage device that may hold the encoded video generated by source device 12. Destination device 14 may access the stored video data from storage device 34 via streaming or download. The file server may be any type of server capable of storing encoded video data and transmitting the encoded video data to destination device 14. Example file servers include web servers (e.g., for a website), FTP servers, Network Attached Storage (NAS) devices, or local disk drives. Destination device 14 may access the encoded video data over any standard data connection, including an internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., DSL, cable modem, etc.), or a combination of both suitable for accessing encoded video data stored on a file server. The transmission of the encoded video data from the storage device 34 may be a streaming transmission, a download transmission, or a combination of both.

The techniques of this disclosure are not necessarily limited to wireless applications or environments. The techniques may be applied to video coding in support of any of a variety of multimedia applications, such as over-the-air protocol television broadcasting, cable television transmission, satellite television transmission, streaming video transmission (e.g., via the internet), encoding digital video for storage on a data storage medium, decoding digital video stored on a data storage medium, or other applications. In some examples, system 10 may be configured to support one-way or two-way video transmission to support applications such as video streaming, video playback, video broadcasting, and/or video telephony.

In the example of fig. 1, source device 12 includes a video source 18, a video encoder 20, and an output interface 22. In some cases, output interface 22 may include a modulator/demodulator (modem) and/or a transmitter. In source device 12, video source 18 may include sources such as a video capture device (e.g., a video camera), a video archive containing previously captured video, a video feed interface for receiving video from a video content provider, and/or a computer graphics system for generating computer graphics data as the source video, or a combination of such sources. As one example, if video source 18 is a camera, source device 12 and destination device 14 may form so-called camera phones or video phones. However, the techniques described in this disclosure may be applicable to video coding in general, and may be applied to wireless and/or wired applications.

Captured video, pre-captured video, or computer-generated video may be encoded by video encoder 20. Encoded video data may be transmitted directly to destination device 14 via output interface 22 of source device 12. The encoded video data may also (or alternatively) be stored onto storage device 34 for later access by destination device 14 or other devices for decoding and/or playback.

Destination device 14 includes input interface 28, video decoder 30, and display device 32. In some cases, input interface 28 may include a receiver and/or a modem. Input interface 28 of destination device 14 receives the encoded video data over link 16. Encoded video data communicated over link 16 or provided on storage device 34 may include a variety of syntax elements generated by video encoder 20 for use by a video decoder, such as video decoder 30, in decoding the video data. These syntax elements may be included with the encoded video data transmitted over a communication medium, stored on a storage medium, or stored on a file server.

The display device 32 may be integrated with the destination device 14 or external to the destination device 14. In some examples, destination device 14 may include an integrated display device, and also be configured to interface with an external display device. In other examples, destination device 14 may be a display device. In general, display device 32 displays the decoded video data to a user, and may comprise any of a variety of display devices, such as a Liquid Crystal Display (LCD), a plasma display, an Organic Light Emitting Diode (OLED) display, or another type of display device.

Video encoder 20 and video decoder 30 may operate according to a video compression standard, such as the High Efficiency Video Coding (HEVC) standard currently being developed, and may conform to the HEVC test model (HM). Alternatively, video encoder 20 and video decoder 30 may operate in accordance with other proprietary or industry standards, such as the ITU-T h.264 standard (alternatively referred to as MPEG-4 part 10, Advanced Video Coding (AVC)), or an extension of such a standard. However, the techniques of this disclosure are not limited to any particular coding standard. Other examples of video compression standards include MPEG-2 and ITU-T H.263.

Although not shown in fig. 1, in some aspects, video encoder 20 and video decoder 30 may each be integrated with an audio encoder and decoder, and may include appropriate MUX-DEMUX units or other hardware and software to handle encoding of both audio and video in a common data stream or separate data streams. In some examples, the MUX-DEMUX unit may conform to the ITU h.223 multiplexer protocol, or other protocols such as User Datagram Protocol (UDP), if applicable.

Video encoder 20 and video decoder 30 may each be implemented as any of a variety of suitable encoder circuits, such as one or more microprocessors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When the techniques are implemented in part in software, a device may store instructions for the software in a suitable non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Each of video encoder 20 and video decoder 30 may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder/decoder (CODEC) in the respective device.

JCT-VC is working on the development of the HEVC standard. HEVC standardization efforts are based on an evolution model of the video coding device, referred to as the HEVC test model (HM). The HM assumes several additional capabilities of video coding devices relative to existing devices in accordance with, for example, ITU-T h.264/AVC. For example, h.264 provides nine intra-prediction encoding modes, while HM may provide up to thirty-three intra-prediction encoding modes.

In general, the working model for HM describes that a video frame or picture may be divided into a sequence of treeblocks or Largest Coding Units (LCUs) that include both luma and chroma samples. Treeblocks have a similar purpose as macroblocks of the h.264 standard. A slice includes a plurality of consecutive treeblocks in coding order. A video frame or picture may be partitioned into one or more slices. Each treeblock may be split into Coding Units (CUs) according to a quadtree. For example, a treeblock that is the root node of a quadtree may be split into four child nodes, and each child node may in turn be a parent node and split into four other child nodes. The last non-split child node (as a leaf node of the quadtree) comprises a coding node, i.e., a coded video block. Syntax data associated with a coded bitstream may define a maximum number of times a treeblock may be split, and may also define a minimum size of a coding node.

A CU includes a coding node and Prediction Units (PUs) and Transform Units (TUs) associated with the coding node. The size of a CU generally corresponds to the size of the coding node and the shape must typically be square. The size of a CU may range from 8 × 8 pixels up to a size having a maximum treeblock of 64 × 64 pixels or more. Each CU may contain one or more PUs and one or more TUs. For example, syntax data associated with a CU may describe partitioning the CU into one or more PUs. The partition mode may distinguish between a CU being skipped or being direct mode encoded, intra prediction mode encoded, or inter prediction mode encoded. The PU may be segmented into non-square shapes. For example, syntax data associated with a CU may also describe that the CU is partitioned into one or more TUs according to a quadtree. The TU may be square or non-square in shape.

The HEVC standard allows for the transform of TUs, which may be different for different CUs. The size of a TU is typically set based on the size of a PU within a given CU defined for the partitioned LCU, although this may not always be the case. TUs are typically the same size or smaller than a PU. In some examples, the residual samples corresponding to a CU may be subdivided into smaller units using a quadtree structure referred to as a "residual quadtree" (RQT). The leaf nodes of the RQT may be referred to as Transform Units (TUs). Pixel difference values associated with TUs may be transformed to produce transform coefficients, which may be quantized.

In general, a PU includes data related to a prediction process. For example, when the PU is intra-mode encoded, the PU may include data describing an intra-prediction mode of the PU. As another example, when the PU is inter-mode encoded, the PU may include data defining a motion vector for the PU. The data defining the motion vector for the PU may describe, for example, a horizontal component of the motion vector, a vertical component of the motion vector, a resolution of the motion vector (e.g., one-quarter pixel precision or one-eighth pixel precision), a reference frame to which the motion vector points, and/or a reference picture list (e.g., list 0, list 1, or list C) of the motion vector.

In general, TUs are used for the transform process and the quantization process. A given CU with one or more PUs may also include one or more Transform Units (TUs). After prediction, video encoder 20 may calculate residual values from the video blocks identified by the coding node according to the PUs. The coding node is then updated to reference the residual values instead of the original video block. The residual values comprise pixel difference values that may be transformed into transform coefficients, quantized, and scanned using the transform and other transform information specified in the TU to produce serialized transform coefficients for entropy coding. The coding node may again be updated to reference these serialized transform coefficients. This disclosure generally uses the term "video block" to refer to a coding node of a CU. In some particular cases, this disclosure may also use the term "video block" to refer to a treeblock (i.e., an LCU or CU) that includes a coding node and a number of PUs and TUs.

A video sequence typically comprises a series of video frames or pictures. A group of pictures (GOP) generally includes a series of one or more video pictures. The GOP may include syntax data at a header of the GOP, a header of one or more of the pictures, or otherwise, that describes the number of pictures included in the GOP. Each slice of a picture may include slice syntax data that describes an encoding mode for the respective slice. Video encoder 20 typically operates on video blocks within individual video slices in order to encode the video data. The video block may correspond to a coding node within the CU. Video blocks may have fixed or varying sizes, and may have different sizes according to a given coding standard.

As an example, the HM supports prediction of various PU sizes. Assuming that the size of a particular CU is 2 nx 2N, the HM supports intra prediction of PU sizes of 2 nx 2N or N × N, and inter prediction of symmetric PU sizes of 2 nx 2N, 2 nx N, N × 2N, or N × N. The HM also supports asymmetric partitioning for inter prediction for PU sizes of 2 nxnu, 2 nxnd, nlx 2N and nrx 2N. In asymmetric partitioning, one direction of a CU is not partitioned, while the other direction is partitioned into 25% and 75%. The portion of the CU corresponding to the 25% partition is indicated by an indication of "n" followed by "up", "down", "left", or "right". Thus, for example, "2N × nU" refers to a horizontally partitioned 2N × 2N CU, with the top being 2N × 0.5N PU and the bottom being 2N × 1.5N PU.

In this disclosure, "nxn" and "N by N" may be used interchangeably to refer to the pixel size of a video block, such as 16 x 16 pixels or 16 by 16 pixels, in terms of vertical and horizontal dimensions. In general, a 16 × 16 block will have 16 pixels in the vertical direction (y ═ 16) and 16 pixels in the horizontal direction (x ═ 16). Likewise, an nxn block typically has N pixels in the vertical direction and N pixels in the horizontal direction, where N represents a non-negative integer value. The pixels in a block may be arranged in rows and columns. Further, the block does not necessarily need to have the same number of pixels in the horizontal direction and the vertical direction. For example, a block may comprise N × M pixels, where M is not necessarily equal to N.

After intra-predictive or inter-predictive coding using PUs of the CU, video encoder 20 may calculate residual data to which to apply the transforms specified by the TUs of the CU. The residual data may correspond to pixel differences between pixels of the unencoded picture and prediction values corresponding to the CU. Video encoder 20 may form residual data for the CU and then transform the residual data to generate transform coefficients.

After applying any transform to generate transform coefficients, video encoder 20 may perform quantization of the transform coefficients. Quantization generally refers to the process of: transform coefficients are quantized to possibly reduce the amount of data used to represent the coefficients, providing further compression. The quantization process may reduce the bit depth associated with some or all of the coefficients. For example, an n-bit value may be rounded down to an m-bit value during quantization, where n is greater than m.

In some examples, video encoder 20 may utilize a predefined scan order to scan the quantized transform coefficients to generate a serialized vector that may be entropy encoded. In other examples, video encoder 20 may perform adaptive scanning. After scanning the quantized transform coefficients to form a one-dimensional vector, video encoder 20 may entropy encode the one-dimensional vector, e.g., according to Context Adaptive Variable Length Coding (CAVLC), Context Adaptive Binary Arithmetic Coding (CABAC), syntax-based context adaptive binary arithmetic coding (SBAC), Probability Interval Partitioning Entropy (PIPE) coding, or another entropy encoding method. Video encoder 20 may also entropy encode syntax elements associated with the encoded video data for video decoder 30 to decode the video data.

To perform CABAC, video encoder 20 may assign contexts within the context model to symbols to be transmitted. The context may relate to, for example, whether adjacent values of a symbol are non-zero. To perform CAVLC, video encoder 20 may select a variable length code for a symbol to be transmitted. Codewords in VLC may be constructed such that relatively shorter codes correspond to more probable symbols and longer codes correspond to less probable symbols. In this way, using VLC may achieve bit savings (as compared to, for example, using a equal length codeword for each symbol to be transmitted). The probability determination may be based on the context assigned to the symbol.

Source device 12 may generate the encoded bitstream to include syntax elements that conform to a syntax structure in accordance with the techniques described in this disclosure. In some examples, video encoder 20 may generate an encoded bitstream to signal directly in a Video Parameter Set (VPS) syntax structure for a coded video sequence or in a Video Usability Information (VUI) part of a Sequence Parameter Set (SPS) syntax structure all variables that define conditions for: signaling a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1. In other words, rather than signaling syntax elements for the condition for signaling the number of clock ticks for which the difference corresponding to the Picture Order Count (POC) value is equal to 1 in another syntax structure, such as the HRD parameter syntax structure, incorporated in the VUI part of the VPS syntax structure or the SPS syntax structure, video encoder 20 generates an encoded bitstream to signal syntax elements defining the condition in the VPS and/or VUI syntax structures, and does not need to refer to another syntax structure that is potentially incorporated in either or both of the VPS and VUI syntax structures. The syntax elements may include a timing _ info _ present _ flag syntax element, which is specified in HEVC WD9 as a syntax element of the HRD parameter syntax structure. As a result, the techniques may reduce and potentially eliminate ambiguity within the HEVC WD9 by explicitly specifying in the syntax the source of the syntax elements that define the condition.

Video encoder 20 may test the compliance of the encoded bitstream to requirements specified as one or more bitstream compliance tests defined in a video coding specification (e.g., HEVC WD9) or a subsequent specification (e.g., HEVC WD 10). Video encoder 20 may include or otherwise use a hypothetical reference decoder to test the conformance of the encoded bitstream. According to the techniques described herein, video encoder 20 may test the conformance of the encoded bitstream by: decoding the encoded bitstream to determine, from a VPS syntax structure of the coded video sequence or in a VUI part of the SPS syntax structure, syntax elements that define conditions for: signaling the number of clock ticks corresponding to a difference in POC values equal to 1. If the condition is true according to the syntax element value, video encoder 20 may determine a number of clock ticks corresponding to a difference in POC values equal to 1, and use the determined number of clock ticks as input for determining CPB underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

In some cases, at destination device 14, video decoder 30 (or VUT) under test may, in some cases, receive a representation of the encoded bitstream generated by video encoder 20 to signal directly, in the VPS syntax structure of the coded video sequence or in the VUI part of the SPS syntax structure, all syntax elements that define conditions for: signaling a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1. Video decoder 30 may decode the encoded bitstream to determine, from the VPS syntax structure of the coded video sequence or in the VUI part of the SPS syntax structure, syntax elements that define conditions for: signaling the number of clock ticks corresponding to a difference in POC values equal to 1. If the condition is true according to the syntax element value, video decoder 30 may determine a number of clock ticks corresponding to a difference in POC values equal to 1, and use the determined number of clock ticks as input for determining CPB underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

In some examples, video encoder 20 may generate the encoded bitstream to signal the time scale and the number of units in the clock tick at most once in each of the VPS syntax structure and the VUI syntax structure for a given coded video sequence. That is, in a given VPS syntax structure for an encoded bitstream, video encoder 20 may signal the time scale and the number of units in the clock tick syntax elements at most once. Similarly, in a given VUI syntax structure (e.g., the VUI part of the SPS syntax structure) for the encoded bitstream, video encoder 20 may signal the time scale and the number of units in the clock tick syntax elements at most once. As a result, video encoder 20 operating in accordance with the techniques described herein may reduce the number of instances of the time scale syntax element (per time scale of WD9) and the number of units in the clock tick (per num units in tick of WD9) syntax element in the encoded bitstream. Additionally, in some cases, video encoder 20 may generate the encoded bitstream to signal the time scale and the number of units in the clock tick directly in each of the VPS and VUI syntax structures of a given coded video sequence, rather than in the HRD parameter syntax structures incorporated within the VPS and/or VUI syntax structures.

According to the techniques described herein, video encoder 20 may test the conformance of an encoded bitstream (which is generated by video encoder 20 to signal the time scale and the number of units in a clock tick at most once in each of the VPS and VUI syntax structures for a given coded timing) by: the encoded bitstream is decoded to determine a time scale and a number of units in a clock tick from a VPS syntax structure of the encoded bitstream, which encodes the time scale and the number of units in a clock tick syntax element at most once in the VPS syntax structure. In some cases, video encoder 20 may test the encoded bitstream for conformance by: decoding the encoded bitstream to determine a time scale and a number of units in a clock tick from a VUI syntax structure of the encoded bitstream, the encoded bitstream encoding the time scale and the number of units in a clock tick syntax element at most once in the VUI syntax structure. The time scale and number of units in a clock tick may not be signaled in the HRD parameter syntax structure incorporated within the VPS and/or VUI syntax structures. Video encoder 20 may use the determined time scale and the determined number of units in the clock tick as inputs for determining CPB underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

In some cases, at destination device 14, video decoder 30 under test may, in some cases, receive a representation of the encoded bitstream generated by video encoder 20 to signal the time scale and the number of units in the clock tick at most once in each of the VPS and VUI syntax structures of a given coded video sequence. Video decoder 30 may decode the encoded bitstream to determine the time scale and the number of units in the clock tick from a VPS syntax structure of the encoded bitstream that encodes the time scale and the number of units in the clock tick syntax elements at most once in the VPS syntax structure. In some cases, video decoder 30 may test the encoded bitstream for conformance by: decoding the encoded bitstream to determine a time scale and a number of units in a clock tick from a VUI syntax structure of the encoded bitstream, the encoded bitstream encoding the time scale and the number of units in a clock tick syntax element at most once in the VUI syntax structure. The time scale and number of units in a clock tick may not be signaled in the HRD parameter syntax structure incorporated within the VPS and/or VUI syntax structures. Video decoder 30 may use the determined time scale and the determined number of units in the clock tick as inputs for determining CPB underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

In some examples, video encoder 20 may generate the encoded bitstream to signal a flag in a VPS syntax structure of one or more coded video sequences that indicates whether a POC value of each picture (except for a first picture in decoding order in the coded video sequence) in the coded video sequence is proportional to an output time of the first picture in the coded video sequence relative to the output time of the picture. This indication flag may alternatively be referred to as a POC proportional to timing indication flag. As a result, video encoder 20 may reduce the number of instances of the indication in the timing information signaled for multiple layers of the coded video sequence and/or a scalable video bitstream having multiple layers. In some cases, video encoder 20 may include this flag in the VPS syntax structure only if the time scale and number of units in the clock tick syntax elements are also included. Video encoder 20 may in this way avoid signaling this particular timing information (i.e., whether the POC value of each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) is proportional to the output time of the first picture in the coded video sequence relative to the output time of that picture) if POC-proportional-to-timing-indicating that the required clock tick information is not already present).

According to the techniques described herein, video encoder 20 may test the conformance of the encoded bitstream (which was generated by video encoder 20) to signal the POC and timing proportional indication flag in the VPS syntax structure of one or more coded video sequences. Video encoder 20 may test the encoded bitstream for conformance by decoding the encoded bitstream to determine the value of the flag. Video encoder 20 may additionally or alternatively test the encoded bitstream generated by video encoder 20 to signal the flag in the VPS syntax structure only if the time scale and number of units in the clock tick syntax elements are also included. Video encoder 20 may use the determined value of the POC proportional to timing indication flag and the number of units in the time scale and clock tick syntax elements as inputs for determining CPB underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

In some cases, at destination device 14, video decoder 30 under test may, in some cases, receive a representation of the encoded bitstream generated by video encoder 20 to signal the POC to timing proportional indication flag in the VPS syntax structure of the one or more coded video sequences. Video decoder 30 may test the conformance of the encoded bitstream by decoding the encoded bitstream to determine the value of the flag. Video decoder 30 may additionally or alternatively test the encoded bitstream generated by video decoder 30 to signal the flag in the VPS syntax structure only if the time scale and number of units in the clock tick syntax elements are also included. Video decoder 30 may use the determined value of the POC proportional to timing indication flag and the number of units in the time scale and clock tick syntax elements as inputs for determining CPB underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

FIG. 2 is a block diagram illustrating an example video encoder 20 that may implement the techniques described in this disclosure. Video encoder 20 may perform intra-coding and inter-coding of video blocks within a video slice. Intra-coding relies on spatial prediction to reduce or remove spatial redundancy in video within a given video frame or picture. Inter-coding relies on temporal prediction to reduce or remove temporal redundancy in video within contiguous frames or pictures of a video sequence. Intra mode (I-mode) may refer to any of several space-based compression modes. An inter mode, such as unidirectional prediction (P-mode) or bidirectional prediction (B-mode), may refer to any of several time-based compression modes.

In the example of fig. 2, video encoder 20 includes partitioning unit 35, prediction module 41, reference picture memory 64, summer 50, transform module 52, quantization unit 54, and entropy encoding unit 56. Prediction module 41 includes a motion estimation unit 42, a motion compensation unit 44, and an intra-prediction module 46. For video block reconstruction, video encoder 20 also includes an inverse quantization unit 58, an inverse transform module 60, and a summer 62. A deblocking filter (not shown in fig. 2) may also be included to filter block boundaries to remove blockiness artifacts from the reconstructed video. The deblocking filter will typically filter the output of summer 62 if desired. In addition to deblocking filters, additional loop filters (in-loop or post-loop) may be used.

As shown in fig. 2, video encoder 20 receives video data and partition unit 35 partitions the data into video blocks. Such partitioning may also include partitioning into slices, image blocks, or other larger units, as well as video block partitioning, e.g., according to a quadtree structure of LCUs and CUs. Video encoder 20 generally illustrates components that encode video blocks within a video slice to be encoded. The slice may be divided into a plurality of video blocks (and possibly into arrays of video blocks referred to as tiles). Prediction module 41 may select one of a plurality of possible coding modes, e.g., one of a plurality of intra coding modes or one of a plurality of inter coding modes, for the current video block based on the error results (e.g., coding rate and distortion level). Prediction module 41 may provide the resulting intra-coded or inter-coded block to summer 50 to generate residual block data, and to summer 62 to reconstruct the encoded block for use as a reference picture.

Intra-prediction module 46 within prediction module 41 may perform intra-prediction coding of the current video block relative to one or more neighboring blocks in the same frame or slice as the current block to be coded to provide spatial compression. Motion estimation unit 42 and motion compensation unit 44 within prediction module 41 perform inter-prediction coding of the current video block relative to one or more prediction blocks in one or more reference pictures to provide temporal compression.

Motion estimation unit 42 may be configured to determine an inter-prediction mode for a video slice according to a predetermined mode for a video sequence. The predetermined pattern may designate video slices in the sequence as P slices, B slices, or GPB slices. Motion estimation unit 42 and motion compensation unit 44 may be highly integrated, but are illustrated separately for conceptual purposes. Motion estimation performed by motion estimation unit 42 is the process of generating motion vectors, which estimate the motion of video blocks. For example, a motion vector may indicate a displacement of a PU of a video block within a current video frame or picture relative to a prediction block within a reference picture.

A prediction block is a block that is found to closely match a PU of a video block to be coded in terms of pixel differences, which may be determined by Sum of Absolute Differences (SAD), Sum of Squared Differences (SSD), or other difference metrics. In some examples, video encoder 20 may calculate values for sub-integer pixel positions of reference pictures stored in reference picture memory 64. For example, video encoder 20 may interpolate values for a quarter-pixel position, an eighth-pixel position, or other fractional-pixel positions of a reference picture. Thus, motion estimation unit 42 may perform a motion search with respect to the full pixel positions and fractional pixel positions and output motion vectors with fractional pixel precision.

Motion estimation unit 42 calculates motion vectors for PUs of video blocks in inter-coded slices by comparing the locations of the PUs to locations of prediction blocks of reference pictures. The reference picture may be selected from a first reference picture list (list 0) or a second reference picture list (list 1), each of which identifies one or more reference pictures stored in reference picture memory 64. Motion estimation unit 42 sends the calculated motion vectors to entropy encoding unit 56 and motion compensation unit 44.

The motion compensation performed by the motion compensation unit 44 may involve obtaining or generating a prediction block based on a motion vector determined by motion estimation (possibly performing interpolation to sub-pixel precision). Upon receiving the motion vector for the PU of the current video block, motion compensation unit 44 may locate the prediction block to which the motion vector points in one of the reference picture lists. Video encoder 20 forms a residual video block by subtracting the pixel values of the prediction block from the pixel values of the current video block being coded, forming pixel difference values. The pixel difference values form residual data for the block and may include both luma and chroma difference components. Summer 50 represents one or more components that perform this subtraction operation. Motion compensation unit 44 may also generate syntax elements 55 associated with the video blocks and the video slice for use by video decoder 30 in decoding the video blocks of the video slice.

Motion compensation unit 44 may generate syntax elements 55 that conform to a syntax structure in accordance with the techniques described in this disclosure. In some examples, video encoder 20 may generate syntax elements 55 to signal directly in a Video Parameter Set (VPS) syntax structure associated with the video block or in a Video Usability Information (VUI) part of a Sequence Parameter Set (SPS) syntax structure all syntax elements that define conditions for: signaling a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1. In other words, rather than signaling syntax elements for the condition for signaling the number of clock ticks for which the difference corresponding to the Picture Order Count (POC) value is equal to 1 in another syntax structure, such as the HRD parameter syntax structure, incorporated in the VUI part of the VPS syntax structure or the SPS syntax structure, motion compensation unit 44 generates an encoded bitstream to signal syntax elements defining the condition in the VPS and/or VUI syntax structures, and need not refer to another syntax structure potentially incorporated in either or both of the VPS and VUI syntax structures.

In some examples, motion compensation unit 44 may generate syntax elements 55 to signal the time scale and the number of units in a clock tick at most once in each of the VPS and VUI syntax structures of a given coded video sequence. That is, in a given VPS syntax structure for the encoded bitstream, motion compensation unit 44 may generate syntax elements 55 to signal the time scale and the number of units in the clock tick syntax elements at most once. Similarly, in a given VUI syntax structure (e.g., the VUI part of an SPS syntax structure) for an encoded bitstream, motion compensation unit 44 may generate syntax elements 55 to signal the time scale and the number of units in the clock tick syntax elements at most once. Additionally, in some cases, motion compensation unit 44 may generate syntax elements 55 to signal the time scale and the number of units in the clock tick directly in each of the VPS and VUI syntax structures of a given coded video sequence, rather than in the HRD parameter syntax structures incorporated within the VPS and/or VUI syntax structures.

In some examples, motion compensation unit 44 may generate syntax element 55 to signal a flag in the VPS syntax structure of one or more coded video sequences that indicates whether the POC value of each picture (except the first picture in decoding order in the coded video sequence) in the coded video sequence is proportional to the output time of the first picture in the coded video sequence relative to the output time of the picture. This indication flag may alternatively be referred to as a POC proportional to timing indication flag. As a result, motion compensation unit 44 may reduce the number of instances of the indication in the timing information signaled for multiple layers of the coded video sequence and/or a scalable video bitstream having multiple layers. In some cases, motion compensation unit 44 may include this flag in the VPS syntax structure only if the time scale and number of units in the clock tick syntax elements are also included. Motion compensation unit 44 may in this way avoid signaling this particular timing information (i.e., whether the POC value of each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) is proportional to the output time of the first picture in the coded video sequence relative to the output time of the picture) if POC-proportional-to-timing-indicating that the required clock tick information is not already present).

Example changes to HEVC WD9 text to carry out the above-described techniques for generating syntax element 55 are as follows (other non-mentioned portions may be unmodified with respect to HEVC WD 9):

the following are examples of video parameter set RBSP syntax structures modified to address one or more of the above-mentioned problems (underlined syntax is an addition to the video parameter set RBSP syntax structure of HEVC WD 9; other syntax may be invariant with respect to HEVC WD 9):

table 4: example video parameter set RBSP syntax structure

Table 4 defines the newly added syntax elements according to the following Video Parameter Set (VPS) RBSP semantics:

vps _ timing _ info _ present _ flag equal to 1 specifies that vps _ num _ units _ in _ tick, vps _ time _ scale, and vps _ poc _ presentation _ to _ timing _ flag are present in the video parameter set. vps _ timing _ info _ present _ flag equal to 0 specifies that vps _ num _ units _ in _ tick, vps _ time _ scale, and vps _ poc _ presentation _ to _ timing _ flag are not present in the video parameter set.

vps _ num _ units _ in _ tick is the number of time units of the clock operating at a frequency vps _ time _ scale Hz corresponding to one increment of the clock tick counter (called clock tick). The value of vps _ num _ units _ in _ tick should be greater than 0. The clock tick in seconds is equal to the quotient of vps _ num _ units _ in _ tick divided by vps _ time _ scale. For example, when the picture rate of the video signal is 25Hz, vps _ time _ scale may be equal to 27,000,000, and vps _ num _ units _ in _ tick may be equal to 1,080,000, and thus the clock tick may be 0.04 seconds.

vps _ time _ scale is the number of time units elapsed in one second. For example, the time coordinate system for measuring time using a 27MHz frequency has a vps _ time _ scale of 27,000,000. The value of vps _ time _ scale should be greater than 0.

vps _ poc _ probable _ to _ timing _ flag equal to 1 indicates that the picture order count value for each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. vps _ poc _ probable _ to _ timing _ flag equal to 0 indicates that the picture order count value for each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) relative to the output time of the first picture in the coded video sequence may or may not be proportional to the output time of the picture.

vps _ num _ ticks _ poc _ diff _ one _ minus1 plus 1 specifies the number of clock ticks corresponding to a difference in picture order count value equal to 1. The value of vps _ num _ ticks _ poc _ diff _ one _ minus1 should be in the range of 0 to 2^32-1 (including 0 and 2^ 32-1).

The following are examples of VUI parameter syntax structures modified to address one or more of the above-described problems (underlined syntax is the addition to the VUI parameter syntax structure of HEVC WD 9; italicized syntax is removed from the VUI parameter syntax structure of HEVC WD 9; other syntax may be invariant with respect to HEVC WD 9):

table 5: instance modified VUI parameter syntax structure

Table 5 defines the newly added syntax elements according to the following VUI parameter semantics (semantics for removing syntax elements also):

the sps _ timing _ info _ present _ flag equal to 1 specifies that sps _ num _ units _ in _ tick, sps _ time _ scale, and sps _ poc _ presentation _ to _ timing _ flag are present in the vui _ parameters () syntax structure. The sps _ timing _ info _ present _ flag equal to 0 specifies that sps _ num _ units _ in _ tick, sps _ time _ scale, and sps _ poc _ presentation _ to _ timing _ flag are not present in the vui _ parameters () syntax structure.

sps _ num _ units _ in _ tick is the number of time units of the clock operating at a frequency sps _ time _ scale Hz corresponding to one increment of the clock tick counter (called a clock tick). sps _ num _ units _ in _ tick should be greater than 0. The clock tick in seconds is equal to the quotient of sps _ num _ units _ in _ tick divided by sps _ time _ scale. For example, when the picture rate of the video signal is 25Hz, sps _ time _ scale may be equal to 27,000,000, and sps _ num _ units _ in _ tick may be equal to 1,080,000, and thus the clock tick may be equal to 0.04 seconds (see equation (1)). When vps _ num _ units _ in _ tick is present in the video parameter set referred to by the sequence parameter set, sps _ num _ units _ in _ tick (when present) should be equal to vps _ num _ units _ in _ tick.

The formula for deriving the variable ClockTick (also referred to herein as "clock tick") is modified as follows:

the sps _ time _ scale is the number of time units elapsed in one second. For example, the time coordinate system for measuring time using a 27MHz frequency has an sps _ time _ scale of 27,000,000. The value of sps _ time _ scale should be greater than 0. When vps _ time _ scale is present in the video parameter set referenced by the sequence parameter set, sps _ time _ scale (when present) should be equal to vps _ time _ scale.

sps _ poc _ probable _ to _ timing _ flag equal to 1 indicates that the picture order count value for each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. The sps _ poc _ probable _ to _ timing _ flag equal to 0 indicates that the picture order count value for each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) may or may not be proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. When the vps _ poc _ reporting _ to _ timing _ flag is present in the video parameter set referenced by the sequence parameter set, the sps _ poc _ reporting _ to _ timing _ flag (when present) should be equal to the vps _ poc _ reporting _ to _ timing _ flag.

sps _ num _ ticks _ poc _ diff _ one _ minus1 plus 1 specifies the number of clock ticks corresponding to a difference in picture order count value equal to 1. The value of sps _ num _ ticks _ poc _ diff _ one _ minus1 should be in the range of 0 to 2^32-1 (including 0 and 2^ 32-1). When vps _ num _ ticks _ poc _ diff _ one _ minus1 is present in the video parameter set referenced by the sequence parameter set, sps _ num _ ticks _ poc _ diff _ one _ minus1 (when present) should be equal to sps _ num _ ticks _ poc _ diff _ one _ minus 1.

The following are examples of HRD parameter syntax structures modified to address one or more of the above-described problems (syntax with italics removed from the HRD parameter syntax structure of hevwd 9):

table 6: instance modified HRD parameter syntax structure

The semantics of syntax elements removed according to the HRD parameter syntax structure modified by the example of table 6 are also removed.

As an alternative to inter prediction performed by motion estimation unit 42 and motion compensation unit 44 as described above, intra prediction module 46 may intra predict the current block. In particular, intra-prediction module 46 may determine the intra-prediction mode used to encode the current block. In some examples, intra-prediction module 46 may encode the current block using various intra-prediction modes, e.g., during separate encoding passes, and intra-prediction module 46 (or mode select unit 40, in some examples) may select an appropriate intra-prediction mode to use from the tested modes. For example, intra-prediction module 46 may calculate rate-distortion values for various tested intra-prediction modes using rate-distortion analysis and select the intra-prediction mode with the best rate-distortion characteristics from among the tested modes. Rate-distortion analysis generally determines the amount of distortion (or error) between an encoded block and an original, unencoded block that was encoded to produce the encoded block, as well as the bit rate (that is, the number of bits) used to produce the encoded block. Intra-prediction module 46 may calculate ratios from the distortions and rates for various encoded blocks to determine which intra-prediction mode exhibits the best rate-distortion value for the block.

In any case, after selecting the intra-prediction mode for a block, intra-prediction module 46 may provide information to entropy encoding unit 56 indicating the selected intra-prediction mode for the block. Entropy encoding unit 56 may encode information indicative of the selected intra-prediction mode in accordance with the techniques of this disclosure. Video encoder 20 may include configuration data in the transmitted bitstream that may include a plurality of intra-prediction mode index tables and a plurality of modified intra-prediction mode index tables (also referred to as codeword mapping tables), definitions of encoding contexts for the various blocks, and indications of the most probable intra-prediction mode, intra-prediction mode index tables, and modified intra-prediction mode index tables for each of the contexts.

After prediction module 41 generates a prediction block for the current video block via inter prediction or intra prediction, video encoder 20 forms a residual video block by subtracting the prediction block from the current video block. The residual video data in the residual block may be included in one or more TUs and applied to transform module 52. Transform module 52 transforms the residual video data into residual transform coefficients using a transform, such as a Discrete Cosine Transform (DCT) or a conceptually similar transform. The transform module 52 may transform the residual video data from the pixel domain to a transform domain, such as the frequency domain.

Transform module 52 may send the resulting transform coefficients to quantization unit 54. Quantization unit 54 quantizes the transform coefficients to further reduce the bit rate. The quantization process may reduce the bit depth associated with some or all of the coefficients. The quantization level may be modified by adjusting a quantization parameter. In some examples, quantization unit 54 may then perform a scan of a matrix including quantized transform coefficients. Alternatively, entropy encoding unit 56 may perform the scanning.

After quantization, entropy encoding unit 56 entropy encodes the quantized transform coefficients. For example, entropy encoding unit 56 may perform Context Adaptive Variable Length Coding (CAVLC), Context Adaptive Binary Arithmetic Coding (CABAC), syntax-based context adaptive binary arithmetic coding (SBAC), Probability Interval Partition Entropy (PIPE) coding, or another entropy encoding method or technique. Following entropy encoding by entropy encoding unit 56, the encoded bitstream may be transmitted to video decoder 30, or archived for later transmission or retrieval by video decoder 30. Entropy encoding unit 56 may also entropy encode the motion vectors and other syntax elements of the current video slice being encoded.

Inverse quantization unit 58 and inverse transform module 60 apply inverse quantization and inverse transform, respectively, to reconstruct the residual block in the pixel domain, e.g., for later use as a reference block for a reference picture. Motion compensation unit 44 may calculate the reference block by adding the residual block to a prediction block of one of the reference pictures within one of the reference picture lists. Motion compensation unit 44 may also apply one or more interpolation filters to the reconstructed residual block to calculate sub-integer pixel values for motion estimation. Summer 62 adds the reconstructed residual block to the motion compensated prediction block produced by motion compensation unit 44 to produce a reference block for storage in a reference picture memory 64, sometimes referred to as a Decoded Picture Buffer (DPB). The reference block may be used by motion estimation unit 42 and motion compensation unit 44 as a reference block to inter-predict a block in a subsequent video frame or picture.

Video encoder 20 may optionally include a Hypothetical Reference Decoder (HRD)57 (illustrated as optional by using dashed lines) to check the conformance of the encoded bitstream generated by the elements of video encoder 20 to the buffer model defined for HRD 57. The HRD57 may detect HRD conformance of type I and/or type II bitstreams or bitstream subsets. The parameter sets required for operation of the HRD57 are signaled by one of two types of HRD parameter sets (NAL HRD parameters and VCL HRD parameters). As described above, the HRD parameter sets may be incorporated within the SPS syntax structure and/or the VPS syntax structure.

The HRD57 may test the conformance of video blocks and associated syntax elements 55 to requirements specified by one or more bitstream conformance tests as defined in a video coding specification (e.g., HEVC WD9) or a subsequent specification (e.g., HEVC WD 10). For example, the HRD57 may test the encoded bitstream for conformance by: the syntax element 55 is processed to determine, from the VPS syntax structure of the coded video sequence or in the VUI part of the SPS syntax structure, syntax elements that define conditions for: signaling the number of clock ticks corresponding to a difference in POC values equal to 1. If the condition is true according to the syntax element value, the HRD57 may determine a number of clock ticks corresponding to a difference in POC values equal to 1, and use the determined number of clock ticks as input for determining CPB underflow or overflow, e.g., during decoding of an encoded picture included in the encoded bitstream. The term "processing" as used herein with respect to a syntax element may refer to: to obtain the extraction, decoding and extraction, reading, parsing, and any other available operation or combination of operations of the syntax elements in a form usable by the decoder/HRD 57.

As another example, the HRD57 may test the encoded bitstream for conformance by: the encoded bitstream is decoded to determine the time scale and the number of units in the clock tick from the VPS syntax structure of syntax element 55, which syntax element 55 encodes the time scale and the number of units in the clock tick syntax element at most once in the VPS syntax structure. In some cases, the HRD57 may test the encoded bitstream for conformance by: the syntax elements 55 are decoded to determine the time scale and the number of units in the clock tick from the VUI syntax structure of the encoded bitstream, which encodes the time scale and the number of units in the clock tick syntax elements at most once in the VUI syntax structure. The time scale and number of units in a clock tick may not be signaled in the HRD parameter syntax structure incorporated within the VPS and/or VUI syntax structures. The HRD57 may use the determined time scale and the determined number of units in the clock tick as inputs for determining CPB underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

According to the techniques described herein, the HRD57 may test the conformance of the encoded bitstream by decoding the value of the POC and timing proportional indication flag from the VPS syntax structure for the syntax elements 55 of the one or more coded video sequences. The HRD57 may additionally or alternatively test the coded bitstream for conformance by decoding the value of the POC and timing proportional indication flag in the VPS syntax structure only if the time scale and number of units in the clock tick syntax elements are also included. The HRD57 may use the determined value of the POC timing-proportional indication flag and the number of units in the time scale and clock tick syntax elements as inputs for determining CPB underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

FIG. 3 is a block diagram illustrating an example video decoder 76 that may implement the techniques described in this disclosure. In the example of fig. 3, video decoder 76 includes a Coded Picture Buffer (CPB)78, an entropy decoding unit 80, a prediction module 81, an inverse quantization unit 86, an inverse transform unit 88, a summer 90, and a Decoded Picture Buffer (DPB) 92. Prediction module 81 includes motion compensation unit 82 and intra-prediction module 84. In some examples, video decoder 76 may perform a decoding pass that is substantially reciprocal to the encoding pass described with respect to video encoder 20 from fig. 2. Video decoder 76 may represent an example of video decoder 30 of destination device 14 or hypothetical reference decoder 57 of fig. 2.

The CPB 78 stores coded pictures from the encoded picture bitstream. In one example, the CBP 78 is a first-in-first-out buffer containing Access Units (AUs) in decoding order. An AU is a set of Network Abstraction Layer (NAL) units associated with each other according to a specified classification rule, the NAL units being consecutive in decoding order and each containing only one coded picture. The decoding order is the order in which the pictures are decoded, and may be different from the order in which the pictures are displayed (i.e., the display order). The operation of the CPB may be specified by a Hypothetical Reference Decoder (HRD).

During the decoding process, video decoder 76 receives an encoded video bitstream that represents video blocks and associated syntax elements of an encoded video slice from video encoder 20. Entropy decoding unit 80 of video decoder 76 decodes the bitstream to generate quantized coefficients, motion vectors, and other syntax elements 55. Entropy decoding unit 80 forwards the motion vectors and other syntax elements 55 to prediction module 81. Video decoder 76 may receive syntax elements 55 at the video slice level and/or the video block level. The encoded video bitstream may include timing information signaled according to the techniques described below. For example, the encoded video bitstream may include a Video Parameter Set (VPS), a Sequence Parameter Set (SPS), or any combination thereof having syntax structures in accordance with the techniques described herein to signal parameters for HRD operations.

When a video slice is coded as an intra-coded (I) slice, intra-prediction module 84 of prediction module 81 may generate prediction data for the video block of the current video slice based on the signaled intra-prediction mode and data from previously decoded blocks of the current frame or picture. When the video frame is coded as an inter-coded (i.e., B, P or GPB) slice, motion compensation unit 82 of prediction module 81 generates a prediction block for the video block of the current video slice based on the motion vectors and other syntax elements 55 received from entropy decoding unit 80. The prediction block may be generated from one of the reference pictures within one of the reference picture lists. Video decoder 76 may construct the reference frame list using default construction techniques based on the reference pictures stored in DPB 92: list 0 and list 1.

Motion compensation unit 82 determines prediction information for the video blocks of the current video slice by parsing the motion vectors and other syntax elements 55 and uses the prediction information to generate a prediction block for the current video block being decoded. For example, motion compensation unit 82 uses some of the received syntax elements 55 to determine prediction modes (e.g., intra-prediction or inter-prediction) for coding video blocks of the video slice, inter-prediction slice types (e.g., B-slices, P-slices, or GPB slices), construction information for one or more of the reference picture lists of the slices, motion vectors for each inter-coded video block of the slice, inter-prediction states for each inter-coded video block of the slice, and other information used to decode video blocks in the current video slice.

Motion compensation unit 82 may also perform interpolation based on the interpolation filter. Motion compensation unit 82 may use interpolation filters used by video encoder 20 during encoding of video blocks to calculate interpolated values for sub-integer pixels of a reference block. In this case, motion compensation unit 82 may determine the interpolation filter used by video encoder 20 according to received syntax element 55 and use the interpolation filter to generate the prediction block.

Inverse quantization unit 86 inverse quantizes, i.e., dequantizes, the quantized transform coefficients provided in the bitstream and decoded by entropy decoding unit 80. The inverse quantization process may include using video encoder 20 to calculate, for each video block in a video slice, a quantization parameter to determine the degree of quantization that should be applied and the degree of inverse quantization as well. The inverse transform unit 88 applies an inverse transform, such as an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process, to the transform coefficients in order to generate a residual block in the pixel domain.

After motion compensation unit 82 generates the predictive block for the current video block based on the motion vector and other syntax elements 55, video decoder 76 forms a decoded video block by summing the residual block from inverse transform unit 88 with the corresponding predictive block generated by motion compensation unit 82. Summer 90 represents the component(s) that perform this summation operation. If desired, a deblocking filter may also be applied to filter the decoded blocks in order to remove blocking artifacts. Other loop filters (in or after the coding loop) may also be used to smooth pixel transitions, or otherwise improve video quality. The decoded video blocks in a given frame or picture are then stored in DPB 92, DPB 92 storing reference pictures for subsequent motion compensation. DPB 92 also stores the decoded video for later presentation on a display device, such as display device 32 of fig. 1. Similar to the CPB 78, in one example, the operation of the DPB 92 may be specified by a Hypothetical Reference Decoder (HRD).

As described in this disclosure, encoder 20 and decoder 76 represent techniques configured to perform for signaling timing in a video coding process as described in this disclosure. Thus, the operations described in this disclosure for signaling time may be performed by the encoder 20, the decoder 76, or both. In some cases, encoder 20 may signal timing information, and decoder 76 may receive such timing information, for example, for defining one or more HRD features, characteristics, parameters, or conditions.

In some cases, video decoder 76 may be a video decoder 76 under test (or VUT). Video decoder 76 may receive a representation of the encoded bitstream generated by video encoder 20 to signal directly, in the VPS syntax structure of syntax elements 55 for the coded video sequence or in the VUI part of the SPS syntax structure, all syntax elements that define the conditions for: signaling a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1. Video decoder 76 may decode the encoded bitstream to determine, from the VPS syntax structure of the coded video sequence or in the VUI part of the SPS syntax structure, syntax elements that define conditions for: signaling the number of clock ticks corresponding to a difference in POC values equal to 1. If the condition is true according to the syntax element value, video decoder 76 may determine a number of clock ticks corresponding to a difference in POC values equal to 1, and use the determined number of clock ticks as input for determining CPB 78 underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

In another example, video encoder 20 may receive a representation of the encoded bitstream generated by video encoder 20 to signal the time scale and the number of units in the clock tick at most once in each of the VPS and VUI syntax structures for syntax elements 55 of a given coded video sequence. The video decoder 76 may decode the encoded bitstream to determine the time scale and the number of units in the clock tick from a VPS syntax structure of the encoded bitstream that encodes the time scale and the number of units in the clock tick syntax elements at most once in the VPS syntax structure. In some cases, video decoder 76 may test the encoded bitstream for conformance by: decoding the encoded bitstream to determine a time scale and a number of units in a clock tick from a VUI syntax structure of the encoded bitstream, the encoded bitstream encoding the time scale and the number of units in a clock tick syntax element at most once in the VUI syntax structure. The time scale and number of units in a clock tick may not be signaled in the HRD parameter syntax structure incorporated within the VPS and/or VUI syntax structures. Video decoder 76 may use the determined time scale and the determined number of units in the clock tick as inputs for determining CPB 78 underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

In another example, video decoder 76 may receive a representation of the encoded bitstream generated by video encoder 20 to signal the POC-to-timing proportional indication flag in the VPS syntax structure of syntax element 55 of one or more coded video sequences. The video decoder 76 may test the encoded bitstream for conformance by decoding the encoded bitstream to determine the value of the flag. The video decoder 76 may additionally or alternatively test the encoded bitstream generated by the video decoder 76 to signal the flag in the VPS syntax structure only if the time scale and number of units in the clock tick syntax elements are also included. Video decoder 76 may use the determined value of the POC proportional to timing indication flag and the number of units in the time scale and clock tick syntax elements as inputs for determining CPB 78 underflow or overflow, e.g., during decoding of encoded pictures included in the encoded bitstream.

Fig. 4 is a block diagram illustrating an example coding structure 100 for a reference picture set. Coding structure 100 includes slices 102A-102E (collectively, "slices 102"). The picture order count 108 associated with the coding structure 100 represents the output order of the corresponding slice in the reference picture set. For example, I-slice 102A (POC value 0) will be output first, while B-slice 102B (POC value 1) will be output second. The decoding order 110 associated with the coding structure 100 represents the decoding order of the corresponding slices in the reference picture set. For example, I slice 102A will be output first (decoding order 1), and B slice 102B will be output second (decoding order 2).

The arrow 104 indicates the output time of the pictures along the temporal continuation t. Time interval 106 represents a time interval corresponding to a difference in Picture Order Count (POC) values equal to 1. Time interval 106 may include a number of clock ticks, which may depend on a time scale (corresponding to, for example, an oscillator frequency, such as 27MHz, that defines a time coordinate system for the signaled information) and a number of time units of a clock operating at a time scale corresponding to one increment of a clock tick counter (referred to as a "clock tick"). According to the techniques described herein, video encoder 20 may generate a bitstream to signal syntax elements that define conditions for the following directly in a Video Parameter Set (VPS) syntax structure for a coded video sequence or in a Video Usability Information (VUI) part of a Sequence Parameter Set (SPS) syntax structure: signaling a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to 1.

FIG. 5 is a flow diagram illustrating an example method of operation in accordance with the techniques described in this disclosure. Video encoder 20 encodes pictures of a video sequence to generate a coded video sequence (200). Video encoder 20 additionally generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a Sequence Parameter Set (SPS) syntax structure and/or according to a Video Parameter Set (VPS) syntax structure. According to the techniques described herein, video encoder 20 encodes syntax elements for the number of units in a clock tick and the time scale directly to the VPS syntax structure and/or directly to the SPS syntax structure of the coded video sequence (202). The term "directly" indicates that such encoding can be generated without incorporating syntax elements in the VPS syntax structure or the SPS syntax structure (where applicable) for the number of units in a clock tick and the time scale defined for the independent parameter set syntax structure, e.g., corresponding to a Hypothetical Reference Decoder (HRD) parameter set as defined in HEVC WD 9.

In addition, video encoder 20 encodes the conditions for the following cases directly to the VPS syntax structure and/or SPS syntax structure of the coded video sequence: a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to one is signaled (204). The conditions may include one or more syntax elements that represent variables of a Boolean (Boolean) formula, in which case video encoder 20 may encode each such syntax element directly into a VPS syntax structure and/or an SPS syntax structure of a coded video sequence. Video encoder 20 outputs the coded video sequence and the VPS syntax structure and/or the SPS syntax structure for the coded video sequence (206). In some cases, video encoder 20 outputs these structures to the HRD of video encoder 20.

6A-6B are flow diagrams illustrating example methods of operation in accordance with the techniques described in this disclosure. In fig. 6A, video encoder 20 encodes pictures of a video sequence to generate a coded video sequence (300). Video encoder 20 additionally generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a Video Parameter Set (VPS) syntax structure. According to the techniques described herein, video encoder 20 encodes syntax elements for the number of units in a clock tick and the time scale directly, and at most once, to the VPS syntax structure of a coded video sequence (302). In some cases, even where the VPS syntax structure includes multiple instances of HRD parameters, the VPS syntax structure may include a single syntax element for each of the number of units in the clock tick and the time scale by encoding the syntax elements directly to the VPS syntax structure (at most once) rather than to the HRD parameter set (or any other incorporated parameter set syntax structure). Video encoder 20 outputs a coded video sequence and a VPS syntax structure for the coded video sequence (304). In some cases, video encoder 20 outputs these structures to the HRD of video encoder 20.

In fig. 6B, video encoder 20 encodes pictures of a video sequence to generate a coded video sequence (310). Video encoder 20 additionally generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a Sequence Parameter Set (SPS) syntax structure. According to the techniques described herein, video encoder 20 encodes syntax elements for the number of units in a clock tick and the time scale directly, and at most once, to the SPS syntax structure of the coded video sequence (312). In some cases, even where the SPS syntax structure includes multiple instances of HRD parameters, the SPS syntax structure may include a single syntax element for each of the number of units in the clock tick and the time scale by encoding the syntax elements directly to the SPS syntax structure (at most once) rather than to the HRD parameter set (or any other incorporated parameter set syntax structure). Video encoder 20 outputs the coded video sequence and an SPS syntax structure for the coded video sequence (314). In some cases, video encoder 20 outputs these structures to the HRD of video encoder 20. In some cases, video encoder 20 encodes syntax elements for the number of units in a clock tick and the time scale to both the VPS syntax structure and the SPS syntax structure of the coded video sequence.

FIG. 7 is a flow diagram illustrating an example method of operation in accordance with the techniques described in this disclosure. Video encoder 20 encodes pictures of a video sequence to generate a coded video sequence (400). Video encoder 20 additionally generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a Video Parameter Set (VPS) syntax structure. If the inclusion timing information is to be used, for example, to define the HRD buffering model ("yes" branch of 402), video encoder 20 encodes a syntax element having a value directly to the VPS syntax structure of the coded video sequence that specifies whether a Picture Order Count (POC) value for each picture in the coded video sequence (other than the first picture in decoding order in the coded video sequence) is proportional, relative to an output time of the first picture in the coded video sequence, to an output time of the picture (404). The syntax element may be semantically similar to poc _ presentation _ to _ timing _ flag defined by HEVC WD 9. The timing information may represent the number of units in a clock tick and the time scale.

If the value of the syntax element is true ("yes" branch of 406), video encoder 20 also encodes the syntax element for a number of clock ticks corresponding to a difference in picture order count value equal to one (408). Because video encoder 20 encodes the syntax elements to the VPS, the values of the syntax elements may be applied to all layers or all possible bitstream subsets of the scalable video bitstream, since the VPS represents the highest layer parameter set and describes the overall characteristics of the coded picture sequence.

If the timing information is not to be included in the VPS syntax structure (the "no" branch of 402), video encoder 20 encodes neither: a syntax element for indicating that POC is proportional to timing information; and a syntax element for a number of clock ticks corresponding to a difference in picture order count values equal to one. If the POC is not proportional to the timing information (i.e., the value is false) (no branch of 406), video encoder 20 does not encode syntax elements for the number of clock ticks corresponding to a difference in picture order count values equal to one.

Video encoder 20 outputs a coded video sequence and a VPS syntax structure for the coded video sequence (410). In some cases, video encoder 20 outputs these structures to the HRD of video encoder 20.

FIG. 8 is a flow diagram illustrating an example method of operation in accordance with the techniques described in this disclosure. Video decoder device 30 or hypothetical reference decoder 57 (hereinafter "decoder") of video encoder device 20 receives a coded video sequence and a Video Parameter Set (VPS) syntax structure and/or a Sequence Parameter Set (SPS) syntax structure for the coded video sequence (500). Coded video sequences and/or syntax structures may be encoded to a bitstream that includes one or more encoded pictures.

The decoder processes the VPS syntax structure and/or the SPS syntax structure to extract syntax elements that specify conditions directly in the VPS syntax structure and/or the SPS syntax structure for: a number of clock ticks corresponding to a difference in Picture Order Count (POC) values equal to one is signaled (502). The condition may include one or more syntax elements that represent variables of a Boolean (Boolean) formula, in which case the decoder may process each such syntax element directly from the VPS syntax structure and/or the SPS syntax structure of the coded video sequence.

The decoder additionally processes the VPS syntax structure and/or the SPS syntax structure to extract syntax elements for the number of units in the clock tick and the time scale directly from the VPS syntax structure and/or directly from the SPS syntax structure of the coded video sequence (504). The decoder may then verify conformance of the coded video sequence to a video buffering model defined at least in part by the values for the conditions, such as the number of units in the clock tick and the time scale extracted from the VPS syntax structure and/or the SPS syntax structure, and as read from the corresponding syntax elements (506).

FIGS. 9A-9B are flow diagrams illustrating an example method of operation in accordance with the techniques described in this disclosure. In fig. 9A, video decoder device 30 or hypothetical reference decoder 57 (hereinafter "decoder") of video encoder device 20 receives a coded video sequence and a Video Parameter Set (VPS) syntax structure for the coded video sequence (600). Coded video sequences and/or VPS syntax structures may be encoded to a bitstream that includes one or more encoded pictures.

According to the techniques described herein, a decoder processes a VPS syntax structure to extract syntax elements for the number of units in a clock tick and the time scale that occur directly (and at most once) in the VPS syntax structure of a coded video sequence (602). The decoder may then verify conformance of the coded video sequence to a video buffering model defined at least in part by the values of the number of units in the clock tick and the time scale as extracted from the VPS syntax structure and as read from the corresponding syntax elements (604).

In fig. 9B, a decoder receives a coded video sequence and a Sequence Parameter Set (SPS) syntax structure for the coded video sequence (610). A coded video sequence and/or SPS syntax structure may be encoded to a bitstream that includes one or more encoded pictures.

According to the techniques described herein, a decoder processes the SPS syntax structure to extract syntax elements for the number of units in a clock tick and the time scale that occur directly (and at most once) in the SPS syntax structure of a coded video sequence (612). The decoder may then verify conformance of the coded video sequence to a video buffering model defined at least in part by the values of the number of units in the clock tick and the time scale as extracted from the SPS syntax structure and as read from the corresponding syntax elements (614).

FIG. 10 is a flow diagram illustrating an example method of operation in accordance with the techniques described in this disclosure. In fig. 10, video decoder device 30 or hypothetical reference decoder 57 (hereinafter "decoder") of video encoder device 20 receives a coded video sequence and a Video Parameter Set (VPS) syntax structure for the coded video sequence (700). Coded video sequences and/or VPS syntax structures may be encoded to a bitstream that includes one or more encoded pictures.

The decoder processes the VPS syntax structure to extract syntax elements that specify that a picture order count value for each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) is proportional to an output time of the first picture in the coded video sequence relative to the output time of the picture (702). If the value of the syntax element is true, the decoder further processes the VPS syntax structure to extract the syntax element for a number of clock ticks corresponding to a difference in picture order count value equal to one (706). The decoder may then verify conformance of the coded video sequence to a video buffering model defined at least in part by a value for the number of clock ticks for which the difference corresponding to the picture order count value is equal to one, as extracted from the VPS syntax structure and as read from the corresponding syntax element (708).

In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. The computer-readable medium may include a computer-readable storage medium, which corresponds to a tangible medium, such as a data storage medium, or any communication medium that facilitates transfer of a computer program from one place to another (e.g., according to a communication protocol). In this manner, a computer-readable medium may generally correspond to (1) a tangible computer-readable storage medium that is not transitory or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementing the techniques described in this disclosure. The computer program product may include a computer-readable medium.

By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The instructions may be executed by one or more processors, such as one or more Digital Signal Processors (DSPs), general purpose microprocessors, an Application Specific Integrated Circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, the term "processor," as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques may be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including wireless handsets, Integrated Circuits (ICs), or groups of ICs (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Indeed, as described above, the various units may be combined in a codec hardware unit, in conjunction with suitable software and/or firmware, or provided by a collection of interoperative hardware units, including one or more processors as described above.

Various examples have been described. These and other examples are within the scope of the following claims.

Claims (46)

1. A method for processing video data, the method comprising:

receiving a coded video sequence comprising encoded pictures of the video sequence; and

receiving timing parameters for the coded video sequence that include conditions for: signaling, directly in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock beats corresponding to a difference in Picture Order Count (POC) values equal to 1, wherein the condition indicates whether a Picture Order Count (POC) value of each picture in the coded video sequence other than a first picture in decoding order in the coded video sequence is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

2. The method of claim 1, wherein receiving the coded video sequence comprises receiving a coded bitstream comprising a sequence of bits that forms a representation of the encoded pictures, the method further comprising:

verifying conformance of the coded bitstream to a video buffering model of a coded picture buffer and a decoded picture buffer, the video buffering model being defined at least in part by the condition.

3. The method of claim 1, wherein receiving the timing parameters for the coded video sequence further comprises:

a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure are received.

4. The method of claim 1, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.

5. The method of claim 1, wherein the condition does not depend on a syntax element in a Hypothetical Reference Decoder (HRD) parameter syntax structure for the VPS syntax structure or the SPS syntax structure.

6. The method of claim 1, wherein the VPS syntax structure includes the condition.

7. The method of claim 6, wherein the condition is a vps _ poc _ reporting _ to _ timing _ flag syntax element.

8. The method of claim 1, wherein the SPS syntax structure includes the condition.

9. The method of claim 8, wherein the condition is an sps _ poc _ probabilistic _ to _ timing _ flag syntax element.

10. A method for encoding video data, the method comprising:

encoding a picture of a video sequence to generate a coded video sequence comprising the encoded picture; and

signaling timing parameters for the coded video sequence by directly signaling conditions for: signaling, in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock beats corresponding to a difference in Picture Order Count (POC) values equal to 1, wherein the condition indicates whether a Picture Order Count (POC) value of each picture in the coded video sequence, except a first picture in decoding order in the coded video sequence, is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

11. The method of claim 10, wherein the condition does not depend on syntax elements signaled in a Hypothetical Reference Decoder (HRD) parameter syntax structure.

12. The method of claim 10, wherein signaling the timing parameters further comprises:

signaling a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure.

13. The method of claim 10, wherein directly signaling the condition comprises signaling the condition in the VPS syntax structure.

14. The method of claim 13, wherein the condition is a vps _ poc _ reporting _ to _ timing _ flag syntax element.

15. The method of claim 10, wherein directly signaling the condition comprises signaling the condition in the SPS syntax structure.

16. The method of claim 15, wherein the condition is an sps _ poc _ probabilistic _ to _ timing _ flag syntax element.

17. The method of claim 10, further comprising:

generating a coded bitstream comprising a sequence of bits that forms a representation of the encoded pictures,

wherein the timing parameters at least partially define a video buffering model for coded picture buffers and decoded picture buffers used to verify conformance of the coded bitstream.

18. The method of claim 10, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.

19. A device for processing video data, comprising:

a memory configured to store the video data; and

a processor configured to:

receiving a coded video sequence comprising encoded pictures of the video sequence; and

receiving timing parameters for the coded video sequence that include conditions for: signaling, directly in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock beats corresponding to a difference in Picture Order Count (POC) values equal to 1, wherein the condition indicates whether a Picture Order Count (POC) value of each picture in the coded video sequence other than a first picture in decoding order in the coded video sequence is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

20. The apparatus as set forth in claim 19, wherein,

wherein to receive the coded video sequence, the processor is further configured to receive a coded bitstream comprising a sequence of bits that forms a representation of the encoded pictures, and

wherein the processor is further configured to verify conformance of the coded bitstream to a video buffering model of a coded picture buffer and a decoded picture buffer, the video buffering model being defined at least in part by the condition.

21. The device of claim 19, wherein to receive the timing parameters for the coded video sequence, the processors are further configured to receive a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure.

22. The device of claim 19, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.

23. The device of claim 19, wherein the condition does not depend on a syntax element in a Hypothetical Reference Decoder (HRD) parameter syntax structure of the VPS syntax structure or the SPS syntax structure.

24. The device of claim 19, wherein the VPS syntax structure includes the condition.

25. The device of claim 24, wherein the condition is a vps _ poc _ reporting _ to _ timing _ flag syntax element.

26. The device of claim 19, wherein the SPS syntax structure includes the condition.

27. The device of claim 26, wherein the condition is an sps _ poc _ probabilistic _ to _ timing _ flag syntax element.

28. A device for encoding video data, comprising:

a memory configured to store the video data; and

a processor configured to:

encoding a picture of a video sequence to generate a coded video sequence comprising the encoded picture; and

signaling timing parameters for the coded video sequence by directly signaling conditions for: signaling, in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock beats corresponding to a difference in Picture Order Count (POC) values equal to 1, wherein the condition indicates whether a Picture Order Count (POC) value of each picture in the coded video sequence, except a first picture in decoding order in the coded video sequence, is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

29. The device of claim 28, wherein the condition does not depend on dependencies of syntax elements signaled in a Hypothetical Reference Decoder (HRD) parameter syntax structure.

30. The device of claim 28, wherein to signal the timing parameters, the processor is configured to signal a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure.

31. The device of claim 28, wherein to directly signal the condition, the processor is configured to signal the condition in the VPS syntax structure.

32. The device of claim 31, wherein the condition is a vps _ poc _ reporting _ to _ timing _ flag syntax element.

33. The device of claim 28, wherein to directly signal the condition, the processor is configured to signal the condition in the SPS syntax structure.

34. The device of claim 33, wherein the condition is an sps _ poc _ probabilistic _ to _ timing _ flag syntax element.

35. The device of claim 28, wherein the processor is further configured to:

generating a coded bitstream comprising a sequence of bits that forms a representation of the encoded pictures,

wherein the timing parameters at least partially define a video buffering model for coded picture buffers and decoded picture buffers used to verify conformance of the coded bitstream.

36. The device of claim 28, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.

37. A device for processing video data, comprising:

means for receiving a coded video sequence comprising encoded pictures of the video sequence; and

means for receiving timing parameters for the coded video sequence including conditions for: signaling, directly in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock beats corresponding to a difference in Picture Order Count (POC) values equal to 1, wherein the condition indicates whether a Picture Order Count (POC) value of each picture in the coded video sequence other than a first picture in decoding order in the coded video sequence is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

38. The device of claim 37, wherein the means for receiving the coded video sequence comprises means for receiving a coded bitstream comprising a sequence of bits that forms a representation of the encoded pictures, the device further comprising:

means for verifying conformance of the coded bitstream to a video buffering model of a coded picture buffer and a decoded picture buffer, the video buffering model defined at least in part by the condition.

39. The device of claim 37, wherein the means for receiving the timing parameters for the coded video sequence further comprises:

means for receiving a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure.

40. The device of claim 37, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.

41. The device of claim 37, wherein the condition does not depend on a syntax element in a Hypothetical Reference Decoder (HRD) parameter syntax structure of the VPS syntax structure or the SPS syntax structure.

42. A non-transitory computer-readable storage medium storing instructions for processing video data, the instructions, when executed by one or more processors, cause the one or more processors to:

receiving a coded video sequence comprising encoded pictures of the video sequence; and

receiving timing parameters for the coded video sequence that include conditions for: signaling, directly in at least one of a Video Parameter Set (VPS) syntax structure referenced by the coded video sequence and a Sequence Parameter Set (SPS) syntax structure referenced by the coded video sequence, a number of clock beats corresponding to a difference in Picture Order Count (POC) values equal to 1, wherein the condition indicates whether a Picture Order Count (POC) value of each picture in the coded video sequence other than a first picture in decoding order in the coded video sequence is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

43. The non-transitory computer-readable storage medium of claim 42,

wherein to receive the coded video sequence, the instructions further cause the one or more processors to receive a coded bitstream comprising a sequence of bits that forms a representation of the encoded pictures, and

wherein the instructions further cause the one or more processors to verify conformance of the coded bitstream to a video buffering model of a coded picture buffer and a decoded picture buffer, the video buffering model being defined at least in part by the condition.

44. The non-transitory computer-readable storage medium of claim 42, wherein to receive the timing parameters for the coded video sequence, the instructions further cause the one or more processors to receive a time scale and a number of units in a clock tick in at least one of the VPS syntax structure and the SPS syntax structure.

45. The non-transitory computer-readable storage medium of claim 42, wherein the timing parameters comprise timing parameters for hypothetical reference decoding operations.

46. The non-transitory computer-readable storage medium of claim 42, wherein the condition does not depend on a syntax element in a Hypothetical Reference Decoder (HRD) parameter syntax structure of the VPS syntax structure or the SPS syntax structure.