HK1210350B - Signaling of picture order count to timing information relations for video timing in video coding - Google Patents

Description

Signaling the relationship between picture order count and timing information for video decoding

This application claims the benefit of U.S. Provisional Application No. 61/749,866, filed January 7, 2013, the entire contents of which are incorporated herein by reference.

Technical Field

This disclosure relates to video coding and video processing, and more particularly to techniques for signaling timing information in video information.

Background Art

Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital live broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, electronic book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite radio telephones, so-called "smartphones", video teleconferencing devices, video streaming devices, and the like. Digital video devices implement video compression techniques, such as those described in the standards defined by MPEG-2, MPEG-4, ITU-T H.263 or ITU-T H.264/MPEG-4 Part 10 Advanced Video Coding (AVC), the High Efficiency Video Coding (HEVC) standard, and extensions of these standards. By implementing such video compression techniques, video devices can more efficiently transmit, receive, encode, decode, and/or store digital video information.

Video compression techniques perform spatial (intra-picture) prediction and/or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video frame or a portion of a video frame) may be partitioned into video blocks, which may also be referred to as treeblocks, coding units (CUs), and/or coding nodes. Video blocks in an intra-coded (I) slice of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prediction with respect to reference samples in neighboring blocks in the same picture or temporal prediction with respect to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may refer to reference frames.

Spatial or temporal prediction utilizes prediction blocks. Residual data represents the pixel differences between the original block to be coded and the prediction block. Inter-coded blocks are encoded based on a motion vector pointing to a block of reference samples forming the prediction block and residual data indicating the difference between the coded block and the prediction block. Intra-coded blocks are encoded based on an intra-coding mode and the residual data. To achieve further compression, the residual data can be transformed from the pixel domain to the transform domain, thereby producing residual transform coefficients, which can then be quantized. The quantized transform coefficients, initially arranged in a two-dimensional array, can be scanned to produce a one-dimensional vector of transform coefficients, and entropy coding can be applied to achieve even more compression.

A given coded video sequence encoded into a bitstream comprises an ordered sequence of coded pictures. In the H.264/AVC and HEVC standards, the decoding order of the coded pictures for the bitstream is equivalent to the ordered sequence. However, the standards also support an output order of decoded pictures that is different from the decoding order, and in such cases, the coded pictures are associated with a picture order count (POC) value that specifies the output order of the pictures in the video sequence.

Video timing information for a video sequence may be signaled within syntax elements of one or more syntax structures (alternatively referred to as "parameter set structures" or simply "parameter sets"). The syntax structures may include a sequence parameter set (SPS), which contains coding information that applies to all slices of a coded video sequence. The SPS itself may include parameters referred to as video usability information (VUI), which includes hypothetical reference decoder (HRD) information and information used to enhance the use of the corresponding video sequence for various purposes. The HRD information itself may be signaled using an HRD syntax structure, which may be included within other syntax structures, such as the VUI syntax structure. The syntax structures may also include a video parameter set (VPS), which describes characteristics of the corresponding video sequence. For example, a video parameter set (VPS) is a common syntax element shared by multiple layers or operation points, as well as other operation point information that may be common to multiple sequence parameter sets, such as HRD information for various layers or sub-layers.

Summary of the Invention

In general, this disclosure describes techniques for video coding, and more specifically, techniques for signaling video information, for example, to specify picture output timing and/or to define a buffering model, such as a hypothetical reference decoder (HRD). In some examples, the techniques may include generating an encoded bitstream for a coded video sequence to signal a flag in a video parameter set (VPS) syntax structure that indicates whether a picture order count (POC) value for each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. In some cases, the techniques may include generating an encoded bitstream to signal the flag in a VPS syntax structure only when timing information, in the form of a number of units in a time scale and clock tick syntax element, is also included in the VPS syntax structure.

In one example of the present invention, a method of processing video data includes receiving a coded video sequence comprising encoded pictures of a video sequence, and receiving timing parameters for the coded video sequence, the timing parameters including an indication in a video parameter set (VPS) syntax structure referenced by the coded video sequence of whether a picture order count (POC) value for each picture in the coded video sequence that is not a first picture in the coded video sequence in decoding order is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

In another example of the present disclosure, a method of encoding video data includes encoding pictures of a video sequence to generate a coded video sequence including the encoded pictures; and signaling timing parameters for the coded video sequence by signaling, in a video parameter set (VPS) syntax structure referenced by the coded video sequence, an indication of whether a picture order count (POC) value for each picture in the coded video sequence that is not the first picture in the coded video sequence in decoding order is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

In another example of the present disclosure, a device for processing video data includes a processor configured to: receive a coded video sequence comprising encoded pictures of a video sequence; and receive timing parameters for the coded video sequence, the timing parameters including an indication in a video parameter set (VPS) syntax structure referenced by the coded video sequence of whether a picture order count (POC) value for each picture in the coded video sequence that is not the first picture in the coded video sequence according to decoding order is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

In another example of the present disclosure, a device for encoding video data includes a processor configured to: encode pictures of a video sequence to produce a coded video sequence including the encoded pictures; and signal timing parameters for the coded video sequence by signaling, in a video parameter set (VPS) syntax structure referenced by the coded video sequence, an indication of whether a picture order count (POC) value for each picture in the coded video sequence that is not the first picture in the coded video sequence in decoding order is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

In another example of the present disclosure, a device for processing video data includes: means for receiving a coded video sequence comprising encoded pictures of a video sequence; and means for receiving timing parameters for the coded video sequence, the timing parameters including an indication in a video parameter set (VPS) syntax structure referenced by the coded video sequence of whether a picture order count (POC) value for each picture in the coded video sequence that is not the first picture in the coded video sequence in decoding order is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

In another example, the disclosure describes a computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors to: receive a coded video sequence comprising encoded pictures of a video sequence; and receive timing parameters for the coded video sequence, the timing parameters including an indication in a video parameter set (VPS) syntax structure referenced by the coded video sequence of whether a picture order count (POC) value for each picture in the coded video sequence that is not a first picture in the coded video sequence in decoding order is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence.

The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

1 is a block diagram illustrating an example video encoding and decoding system that may utilize the techniques described in this disclosure.

2 is a block diagram illustrating an example video encoder that may implement the techniques described in this disclosure.

3 is a block diagram illustrating an example video decoder that may implement the techniques described in this disclosure.

4 is a block diagram illustrating timing information of an example coding structure for a reference picture set according to the techniques described herein.

5 is a flowchart illustrating an example method of operation according to the techniques described in this disclosure.

6A-6B are flowcharts illustrating example methods of operation according to the techniques described in this disclosure.

7 is a flowchart illustrating an example method of operation according to the techniques described in this disclosure.

8 is a flowchart illustrating an example method of operation according to the techniques described in this disclosure.

9A-9B are flowcharts illustrating example methods of operation according to the techniques described in this disclosure.

10 is a flowchart illustrating an example method of operation according to the techniques described in this disclosure.

DETAILED DESCRIPTION

This disclosure describes various techniques for video coding, and more specifically relates to techniques for signaling video information, for example, to specify picture output timing and/or define buffering or decoding models, such as a hypothetical reference decoder (HRD). Generally, "signaling" is used in this disclosure to refer to signaling that occurs within a coded bitstream. An encoder may generate syntax elements to signal information in a bitstream as part of the video encoding process. A decoding device or other video processing device may receive the coded bitstream and interpret the syntax elements in the coded bitstream as part of the video decoding process or other video processing.

For example, to indicate the output timing for switching from a given picture in a coded video sequence to the next picture in an output order, in some cases, the timing information for the coded video sequence may signal the number of clock ticks corresponding to a difference of one in the picture order count (POC) values. A difference of one in the POC values may represent a difference between the POC value of the given picture in the output order and the POC value of the next picture (e.g., the POC value of the second picture in the output order and the POC value of the third picture in the output order). The video timing information may also include a condition that specifies whether the video timing information signals the number of clock ticks corresponding to a difference of one in the picture order count values. In other words, the video timing information signals the number of clock ticks corresponding to a difference of one in the picture order count values only if the condition is met. In some cases, the condition is not met, and thus the video timing information does not signal the number of clock ticks corresponding to a difference of one in the picture order count values. The number of such clock ticks may depend on a time scale (corresponding to, for example, an oscillator frequency defining a time coordinate system over which information is signaled, such as 27 MHz) and the number of time units of the clock operating at a time scale corresponding to one increment of a clock tick counter, which is referred to as a "clock tick."

In some examples, the techniques may include generating an encoded bitstream for a coded video sequence to signal a flag in a video parameter set (VPS) syntax structure that indicates whether a picture order count (POC) value for each picture in the coded video sequence (except for the first picture in decoding order in the coded video sequence) is proportional to an output time of the picture relative to an output time of the first picture in the coded video sequence. In some cases, the techniques may include generating the encoded bitstream to signal the flag in the VPS syntax structure only when timing information in the form of a number of units in a time scale and clock tick syntax element is also included in the VPS syntax structure.

Video coding standards include ITU-T H.261, ISO/IEC MPEG-1 Video, ITU-T H.262 or ISO/IEC MPEG-2 Video, ITU-T H.263, ISO/IEC MPEG-4 Video, and ITU-T H.264 (also known as ISO/IEC MPEG-4 AVC), including its Scalable Video Coding (SVC) and Multiview Video Coding (MVC) extensions.

Additionally, there is a new video coding standard, High Efficiency Video Coding (HEVC), which is being developed by the Joint Collaboration Team on Video Coding (JCT-VC) of the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). The latest working draft of HEVC (and hereinafter referred to as HEVC WD9 or just WD9) is Bross et al., “Proposed editorial improvements for High Efficiency Video Coding (HEVC) text specification draft 9 (SoDIS)”, Joint Collaboration Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th meeting: Geneva, Switzerland, January 14–23, 2013, available from http://phenix.int-evry.fr/jct/doc_end_user/documents/12_Geneva/wg11/JCTVC-L0030-v1.zip as of January 7, 2013.

A recent draft of the HEVC standard (referred to as “HEVC Working Draft 10” or “WD10”) is described in document JCTVC-L1003v34 by Bloss et al., entitled “High efficiency video coding (HEVC) text specification draft 10 (for FDIS & Last Call)”, Joint Team on Video Coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11, 12th Meeting: Geneva, Switzerland, January 14-23, 2013, which can be downloaded from http://phenix.int-evry.fr/jct/doc_end_user/documents/12_Geneva/wg11/JCTVC-L1003-v34.zip.

Another draft of the HEVC standard (referred to herein as "WD10 version") is described in Bloss et al., "Editors' proposed corrections to HEVC version 1," Joint Team on Video Coding (JCT-VC) of ITU-TSG16 WP3 and ISO/IEC JTC1/SC29/WG11, 13th Meeting (Incheon, South Korea, April 2013), which was available as of June 7, 2013, from http://phenix.int-evry.fr/jct/doc_end_user/documents/13_Incheon/wg11/JCTVC-M0432-v3.zip.

The HEVC standardization effort is based on a model of a video coding device known as the HEVC Test Model (HM). The HM assumes improvements in the capabilities of current video decoding devices relative to those available during the development of other previous video decoding standards, such as ITU-T H.264/AVC. For example, while H.264 provides nine intra-frame prediction coding modes, HEVC provides up to thirty-five intra-frame prediction coding modes. The entire contents of HEVC WD9 and HEVC WD10 are incorporated herein by reference.

Video coding standards typically include specifications for video buffering models. In AVC and HEVC, the buffering model is called a hypothetical reference decoder (HRD), which includes buffering models for both the coded picture buffer (CPB) and the decoded picture buffer (DPB). As defined in HEVC WD9, HRD is a hypothetical decoder model that specifies constraints on the variability of the network abstraction layer (NAL) unit stream or conforms to the byte stream that can be generated by the encoding process. The CPB and DPB behaviors are mathematically specified. HRD directly imposes constraints on different timings, buffer sizes, and bit rates, and indirectly imposes constraints on bitstream characteristics and statistics. The complete HRD parameter set includes five basic parameters: initial CPB removal delay, CPB size, bit rate, initial DPB output delay, and DPB size.

In AVC and HEVC, bitstream and decoder conformance are specified as part of the HRD specification. Although the term "hypothetical reference decoder" includes the term "decoder," HRD is generally required on the encoder side to ensure bitstream conformance, and is generally not required on the decoder side. Two types of bitstream or HRD conformance are specified: Type I and Type II. Furthermore, two types of decoder conformance are specified: output timing decoder conformance and output order decoder conformance.

In HEVC WD9, HRD operation requires parameters that are signaled in the hrd_parameters() syntax structure, the buffering period supplemental enhancement information (SEI) message, the picture timing SEI message, and sometimes also in the decoding unit information SEI message. The hrd_parameters() syntax structure can be signaled in a video parameter set (VPS), a sequence parameter set (SPS), or any combination thereof.

In HEVC WD9, the hrd_parameters() syntax structure contains syntax elements for signaling video timing information, including the time scale and the number of units in clock ticks. The Video Usability Information (VUI) portion of the SPS contains a flag that indicates whether the picture order count (POC) value of each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence; if so, the number of clock ticks corresponds to the difference in the picture order count value being equal to 1.

The relevant syntax and semantics in HEVC WD9 are as follows: Table 1 shows an example video parameter set raw byte sequence payload (RBSP) syntax structure according to WD9.

Table 1: Example video parameter set RBSP syntax structure

In Table 1 above, the syntax element vps_num_hrd_parameters specifies the number of hrd_parameters() syntax structures present in the video parameter set raw byte sequence payload (RBSP). In bitstreams conforming to this version of this specification, the value of vps_num_hrd_parameters shall be less than or equal to 1. Although the value of vps_num_hrd_parameters is required to be less than or equal to 1 in HEVC WD9, decoders shall allow other values of vps_num_hrd_parameters in the range 0 to 1024 (inclusive) to appear in the syntax.

The syntax element hrd_op_set_idx[i] specifies the index in the list of operation point sets specified by the video parameter set (VPS) to which the i-th hrd_parameters() syntax structure in the video parameter set applies. In bitstreams conforming to this version of this specification, the value of hrd_op_set_idx[i] shall be equal to 0. Although HEVC WD9 requires that the value of hrd_op_set_idx[i] be less than or equal to 1, decoders shall allow other values of hrd_op_set_idx[i] in the range 0 to 1023 to appear in the syntax.

The syntax element cprms_present_flag[i] equal to 1 specifies that the HRD parameters common to all sublayers are present in the i-th hrd_parameters() syntax structure in the video parameter set. cprms_present_flag[i] equal to 0 specifies that the HRD parameters common to all sublayers are not present in the i-th hrd_parameters() syntax structure in the video parameter set, and the (i-1)-th hrd_parameters() syntax structure in the derived video parameter set is also the same. cprms_present_flag[0] is inferred to be 1.

Table 2 below shows the VUI parameter syntax structure according to WD9.

Table 2: VUI parameter syntax structure

In Table 2 above, the syntax element hrd_parameters_present_flag equal to 1 specifies that the syntax structure hrd_parameters() is present in the vui_parameters() syntax structure. hrd_parameters_present_flag equal to 0 specifies that the syntax structure hrd_parameters() is not present in the vui_parameters() syntax structure.

The syntax element poc_proportional_to_timing_flag equal to 1 indicates that the picture order count value of each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. The syntax element poc_proportional_to_timing_flag equal to 0 indicates that the picture order count value of each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) may or may not be proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence.

The syntax element num_ticks_poc_diff_one_minus1 plus 1 specifies the number of clock ticks corresponding to the difference in picture order count values being equal to 1.

Table 3 below shows an example HRD parameter syntax structure according to WD9.

Table 3: Example HRD parameter syntax structure

In Table 3 above, the syntax element timing_info_present_flag equal to 1 specifies that num_units_in_tick and time_scale are present in the hrd_parameters() syntax structure. If timing_info_present_flag is equal to 0, then num_units_in_tick and time_scale are not present in the hrd_parameters() syntax structure. If not present, the value of timing_info_present_flag is inferred to be 0.

The syntax element num_units_in_tick is the number of time units of a clock operating at a frequency time_scale Hz corresponding to one increment of a clock tick counter (referred to as a clock tick). The value of the syntax element num_units_in_tick shall be greater than 0. A clock tick is the smallest interval of time that can be represented by coded data when sub_pic_cpb_params_present_flag is equal to 0. For example, when the picture rate of the video signal is 25 Hz, time_scale may be equal to 27,000,000 and num_units_in_tick may be equal to 1,080,000.

The syntax element time_scale is the number of time units that pass in one second. For example, a time coordinate system that uses a 27 MHz frequency to measure time has a time_scale of 27,000,000. The value of the syntax element time_scale should be greater than 0.

Timing signaling as specified in HEVC WD9 and as described above can present a number of problems. First, the condition for signaling the syntax element num_ticks_poc_diff_one_minus1 is "if (poc_proportional_to_timing_flag && timing_info_present_flag)". This condition includes a dependency on two signaled syntax elements: poc_proportional_to_timing_flag and timing_info_present_flag. However, it is not clear from the HEVC WD9 specification whether the timing_info_present_flag used for the condition is the syntax element timing_info_present_flag of the hrd_parameters() syntax structure (if present) in the VUI part of the reference SPS or the syntax element timing_info_present_flag of the hrd_parameters() syntax structure in the VPS.

In addition, multiple layers or multiple possible bitstream subsets of a scalable video bitstream may share common values for the time scale and the number of units in the tick, which are specified in HEVC WD9 in the syntax elements time_scale and num_units_in_tick of the hrd_parameters() syntax structure. For example, the common values may be signaled repeatedly in the VUI portion of the SPS and in the VPS. Such repetition, if present in the bitstream, may result in wasted bits.

Furthermore, if a picture order count (POC) value is proportional to the output time of any one of several layers of a scalable video bitstream, the POC value is typically proportional to the output time of all layers of the scalable video bitstream. However, the HEVC WD9 specification does not provide for signaling in a scalable video bitstream that POC values are proportional to the output time of all layers of the scalable video bitstream, or all possible bitstream subsets. For example, a reference to a "layer" of a scalable video bitstream may refer to a scalable layer, a texture view, and/or a depth view. Additionally, although HEVC WD9 specifies that the flag poc_proportional_to_timing_flag is always signaled in the VUI syntax structure of an SPS, the flag poc_proportional_to_timing_flag has no effect if the syntax elements time_scale and num_units_in_tick are also not signaled in the bitstream.

The techniques of this disclosure may address one or more of the above-mentioned issues and provide other improvements, thereby enabling efficient signaling of parameters for HRD operation. Various examples of the techniques are described herein with reference to HEVC WD9 and potential improvements thereof. The solutions are applicable to any video coding standard that includes a specification of a video buffering model, such as AVC and HEVC, but for illustrative purposes, the description is specific to HRD parameter signaling defined in HEVC WD9 and modified according to the techniques of this disclosure.

FIG1 is a block diagram illustrating an example video encoding and decoding system 10 that may utilize the techniques described in this disclosure. As shown in FIG1 , system 10 includes a source device 12 that generates encoded video data to be decoded at a later time by a destination device 14. Source device 12 and destination device 14 may comprise any of a wide range of devices, including desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, telephone handsets (e.g., so-called "smart" phones), so-called "smart" tablet computers, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or the like. In some cases, source device 12 and destination device 14 may be equipped for wireless communication.

Destination device 14 may receive the encoded video data to be decoded via link 16. Link 16 may comprise any type of medium or device capable of moving the encoded video data from source device 12 to destination device 14. In one example, link 16 may comprise a communication medium that enables source device 12 to transmit the encoded video data directly to destination device 14 in real time. The encoded video data may be modulated according to a communication standard, such as a wireless communication protocol, and transmitted to destination device 14. The communication medium may comprise any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide area network, or a global network, such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that can be used to facilitate communication from source device 12 to destination device 14.

Alternatively, the encoded data may be output from output interface 22 to storage device 34. Similarly, the encoded data may be accessed from storage device 34 via input interface. Storage device 34 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, Blu-ray disc, DVD, CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data. In another example, storage device 34 may correspond to a file server or another intermediate storage device that can hold the encoded video generated by source device 12. Destination device 14 may access the stored video data from storage device 34 via streaming or downloading. A file server may be any type of server capable of storing encoded video data and transmitting the encoded video data to destination device 14. Example file servers include a network server (e.g., for a website), an FTP server, a network attached storage (NAS) device, or a local disk drive. Destination device 14 may access the encoded video data via any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., DSL, cable modem, etc.), or a combination of both suitable for accessing encoded video data stored on a file server. The transmission of the encoded video data from storage device 34 may be a streaming transmission, a download transmission, or a combination of both.

The techniques of this disclosure are not necessarily limited to wireless applications or environments. The techniques may be applied to video decoding to support any of a variety of multimedia applications, such as over-the-air protocol television broadcasting, cable television transmission, satellite television transmission, streaming video transmission (e.g., via the Internet), encoding digital video for storage on a data storage medium, decoding digital video stored on a data storage medium, or other applications. In some examples, system 10 may be configured to support one-way or two-way video transmission to support applications such as video streaming, video playback, video broadcasting, and/or video telephony.

1 , source device 12 includes a video source 18, a video encoder 20, and an output interface 22. In some cases, output interface 22 may include a modulator/demodulator (modem) and/or a transmitter. In source device 12, video source 18 may include a source such as a video capture device (e.g., a video camera), a video archive containing previously captured video, a video feed interface for receiving video from a video content provider, and/or a computer graphics system for generating computer graphics data as source video, or a combination of such sources. As an example, if video source 18 is a video camera, source device 12 and destination device 14 may form so-called camera phones or video phones. However, the techniques described in this disclosure may be applicable to video coding generally and may be applied to wireless and/or wired applications.

The captured video, pre-captured video, or computer-generated video may be encoded by video encoder 20. The encoded video data may be transmitted directly to destination device 14 via output interface 22 of source device 12. The encoded video data may also (or instead) be stored on storage device 34 for later access by destination device 14 or other devices for decoding and/or playback.

Destination device 14 includes an input interface 28, a video decoder 30, and a display device 32. In some cases, input interface 28 may include a receiver and/or a modem. Input interface 28 of destination device 14 receives encoded video data via link 16. The encoded video data communicated via link 16 or provided on storage device 34 may include a variety of syntax elements generated by video encoder 20 for use by a video decoder, such as video decoder 30, in decoding the video data. These syntax elements may be included with the encoded video data transmitted over a communication medium, stored on a storage medium, or stored on a file server.

Display device 32 may be integrated with destination device 14 or external to destination device 14. In some examples, destination device 14 may include an integrated display device and also be configured to interface with an external display device. In other examples, destination device 14 may be a display device. Generally, display device 32 displays decoded video data to a user and may include any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

Video encoder 20 and video decoder 30 may operate according to a video compression standard, such as the High Efficiency Video Coding (HEVC) standard currently under development, and may conform to the HEVC Test Model (HM). Alternatively, video encoder 20 and video decoder 30 may operate according to other proprietary or industry standards, such as the ITU-T H.264 standard (alternatively known as MPEG-4 Part 10, Advanced Video Coding (AVC)), or extensions of such standards. However, the techniques of this disclosure are not limited to any particular coding standard. Other examples of video compression standards include MPEG-2 and ITU-T H.263.

Although not shown in FIG1 , in some aspects, video encoder 20 and video decoder 30 may each be integrated with an audio encoder and decoder and may include appropriate MUX-DEMUX units or other hardware and software to handle the encoding of both audio and video in a common data stream or in separate data streams. In some examples, the MUX-DEMUX units may conform to the ITU H.223 multiplexer protocol, or other protocols such as the User Datagram Protocol (UDP), if applicable.

Video encoder 20 and video decoder 30 may each be implemented as any of a variety of suitable encoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When the techniques are implemented partially in software, the device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Each of video encoder 20 and video decoder 30 may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder/decoder (CODEC) in the respective device.

The JCT-VC is working on the development of the HEVC standard. The HEVC standardization effort is based on an evolving model of a video coding device, referred to as the HEVC Test Model (HM). The HM assumes several additional capabilities of video coding devices relative to existing devices based on, for example, ITU-T H.264/AVC. For example, while H.264 provides nine intra-frame prediction coding modes, the HM can provide up to 33 intra-frame prediction coding modes.

In general, the working model of the HM describes that a video frame or picture can be divided into a sequence of tree blocks or largest coding units (LCUs) that include both luma and chroma samples. Tree blocks have a similar purpose to macroblocks of the H.264 standard. A slice includes multiple consecutive tree blocks in coding order. A video frame or picture can be partitioned into one or more slices. Each tree block can be split into coding units (CUs) according to a quadtree. For example, a tree block that is the root node of a quadtree can be split into four child nodes, and each child node can be a parent node and split into another four child nodes. The last unsplit child node (which is a leaf node of the quadtree) includes a coding node, i.e., a coded video block. Syntax data associated with the coded bitstream can define the maximum number of times a tree block can be split, and can also define the minimum size of a coding node.

A CU includes a coding node and prediction units (PUs) and transform units (TUs) associated with the coding node. The size of a CU generally corresponds to the size of the coding node and the shape is usually necessarily square. The size of a CU can range from 8×8 pixels up to the size of a treeblock with a maximum of 64×64 pixels or larger. Each CU may contain one or more PUs and one or more TUs. For example, the syntax data associated with a CU may describe the partitioning of the CU into one or more PUs. The partitioning mode may distinguish between whether the CU is skipped or encoded in direct mode, intra-prediction mode, or inter-prediction mode. The PU may be partitioned into a non-square shape. For example, the syntax data associated with a CU may also describe that the CU is partitioned into one or more TUs according to a quadtree. A TU may be square or non-square in shape.

The HEVC standard allows for transforms based on TUs, which can be different for different CUs. The size of a TU is typically set based on the size of the PU within a given CU defined for a partitioned LCU, but this may not always be the case. A TU is typically the same size as or smaller than a PU. In some examples, the residual samples corresponding to a CU can be subdivided into smaller units using a quadtree structure called a "residual quadtree" (RQT). The leaf nodes of the RQT can be called transform units (TUs). Pixel difference values associated with a TU can be transformed to produce transform coefficients, which can be quantized.

In general, a PU includes data related to the prediction process. For example, when the PU is intra-mode encoded, the PU may include data describing the intra-prediction mode of the PU. As another example, when the PU is inter-mode encoded, the PU may include data defining the motion vector of the PU. The data defining the motion vector of the PU may describe, for example, the horizontal component of the motion vector, the vertical component of the motion vector, the resolution of the motion vector (e.g., quarter-pixel precision or eighth-pixel precision), the reference frame to which the motion vector points, and/or the reference picture list of the motion vector (e.g., List 0, List 1, or List C).

In general, TUs are used for the transform and quantization processes. A given CU with one or more PUs may also include one or more transform units (TUs). After prediction, the video encoder 20 may calculate residual values from the video block identified by the coding node based on the PUs. The coding node is then updated to reference the residual values instead of the original video block. The residual values include pixel difference values, which can be transformed into transform coefficients, quantized, and scanned using the transform and other transform information specified in the TU to produce serialized transform coefficients for entropy coding. The coding node can be updated again to reference these serialized transform coefficients. This disclosure generally uses the term "video block" to refer to the coding node of a CU. In some specific cases, this disclosure may also use the term "video block" to refer to a tree block (i.e., LCU or CU) that includes a coding node and several PUs and TUs.

A video sequence typically includes a series of video frames or pictures. A group of pictures (GOP) generally includes a series of one or more video pictures. A GOP may include a header for the GOP, a header for one or more of the pictures, or other syntax data that describes the number of pictures included in the GOP. Each slice of a picture may include slice syntax data that describes the coding mode for the corresponding slice. Video encoder 20 typically operates on video blocks within individual video slices to encode the video data. A video block may correspond to a decoding node within a CU. A video block may have a fixed or variable size and may have different sizes depending on a specified decoding standard.

As an example, the HM supports prediction for various PU sizes. Assuming the size of a particular CU is 2N×2N, the HM supports intra prediction for PU sizes of 2N×2N or N×N, and inter prediction for symmetric PU sizes of 2N×2N, 2N×N, N×2N, or N×N. The HM also supports asymmetric partitioning for inter prediction for PU sizes of 2N×nU, 2N×nD, nL×2N, and nR×2N. In asymmetric partitioning, one direction of the CU is not partitioned, while the other direction is partitioned into 25% and 75%. The portion of the CU corresponding to the 25% partition is indicated by an "n" followed by an indication of "above," "below," "left," or "right." Thus, for example, "2N×nU" refers to a horizontally partitioned 2N×2N CU with a 2N×0.5N PU at the top and a 2N×1.5N PU at the bottom.

In this disclosure, "NxN" and "N by N" may be used interchangeably to refer to the pixel dimensions of a video block in terms of vertical and horizontal dimensions, e.g., 16x16 pixels or 16 by 16 pixels. Generally, a 16x16 block will have 16 pixels in the vertical direction (y=16) and 16 pixels in the horizontal direction (x=16). Similarly, an NxN block generally has N pixels in the vertical direction and N pixels in the horizontal direction, where N represents a non-negative integer value. The pixels in a block may be arranged in rows and columns. Furthermore, a block need not necessarily have the same number of pixels in the horizontal and vertical directions. For example, a block may comprise NxM pixels, where M is not necessarily equal to N.

After performing intra-predictive or inter-predictive coding using the PUs of a CU, video encoder 20 may calculate residual data to which the transform specified by the TUs of the CU is applied. The residual data may correspond to pixel differences between pixels of an unencoded picture and prediction values corresponding to the CU. Video encoder 20 may form the residual data for the CU and then transform the residual data to produce transform coefficients.

After applying any transforms to generate transform coefficients, video encoder 20 may perform quantization of the transform coefficients. Quantization generally refers to the process of quantizing transform coefficients to potentially reduce the amount of data used to represent the coefficients, thereby providing further compression. The quantization process may reduce the bit depth associated with some or all of the coefficients. For example, an n-bit value may be rounded down to an m-bit value during quantization, where n is greater than m.

In some examples, video encoder 20 may utilize a predefined scan order to scan the quantized transform coefficients to generate a serialized vector that can be entropy encoded. In other examples, video encoder 20 may perform adaptive scanning. After scanning the quantized transform coefficients to form a one-dimensional vector, video encoder 20 may entropy encode the one-dimensional vector, for example, according to context-adaptive variable length coding (CAVLC), context-adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or another entropy encoding method. Video encoder 20 may also entropy encode syntax elements associated with the encoded video data for video decoder 30 to decode the video data.

To perform CABAC, video encoder 20 may assign context within a context model to a symbol to be transmitted. The context may relate to, for example, whether neighboring values of the symbol are non-zero. To perform CAVLC, video encoder 20 may select a variable length code for the symbol to be transmitted. Codewords in VLC may be constructed such that relatively shorter codes correspond to more likely symbols, while longer codes correspond to less likely symbols. In this way, using VLC may achieve bit savings (compared to, for example, using equal-length codewords for each symbol to be transmitted). Probability determinations may be based on the context assigned to the symbol.

Source device 12 may generate an encoded bitstream to include syntax elements that conform to syntax structures according to the techniques described in this disclosure. In some examples, video encoder 20 may generate an encoded bitstream to directly signal all variables that define a condition for signaling a number of clock ticks corresponding to a difference in picture order count (POC) values equal to one in a video parameter set (VPS) syntax structure for a coded video sequence or in a video usability information (VUI) portion of a sequence parameter set (SPS) syntax structure. In other words, rather than signaling syntax elements for the condition for signaling a number of clock ticks corresponding to a difference in picture order count (POC) values equal to one in another syntax structure (e.g., an HRD parameter syntax structure) incorporated into the VPS syntax structure or the VUI portion of the SPS syntax structure, video encoder 20 generates an encoded bitstream to signal syntax elements that define the condition in the VPS and/or VUI syntax structures without reference to another syntax structure potentially incorporated into either or both the VPS and VUI syntax structures. The syntax elements may include a timing_info_present_flag syntax element, which is specified as a syntax element of the HRD parameter syntax structure in HEVC WD9. As a result, the techniques may reduce and potentially eliminate ambiguity within HEVC WD9 by clearly specifying in the syntax the source of the syntax elements defining the condition.

Video encoder 20 may test an encoded bitstream for compliance with requirements specified as one or more bitstream conformance tests defined in a video coding specification (e.g., HEVC WD9) or a subsequent specification (e.g., HEVC WD10). Video encoder 20 may include or otherwise use a hypothetical reference decoder to test the conformance of an encoded bitstream. According to the techniques described herein, video encoder 20 may test the conformance of an encoded bitstream by decoding the encoded bitstream to determine, from a VPS syntax structure of a coded video sequence or a VUI portion of an SPS syntax structure, a syntax element that defines a condition for signaling a number of clock ticks corresponding to a difference in POC values equal to 1. If the condition holds true according to the syntax element value, video encoder 20 may determine the number of clock ticks corresponding to a difference in POC values equal to 1 and use the determined number of clock ticks as input for determining CPB underflow or overflow, for example, during decoding of an encoded picture included in the encoded bitstream.

In some cases, at destination device 14, video decoder 30 under test (or VUT) may, in some cases, receive a representation of an encoded bitstream generated by video encoder 20 to directly signal, in a VPS syntax structure for the coded video sequence or in a VUI portion of an SPS syntax structure, all syntax elements that define a condition for signaling a number of clock ticks corresponding to a difference in picture order count (POC) values being equal to 1. Video decoder 30 may decode the encoded bitstream to determine, from the VPS syntax structure for the coded video sequence or in the VUI portion of the SPS syntax structure, the syntax elements that define a condition for signaling a number of clock ticks corresponding to a difference in POC values being equal to 1. If the condition holds true according to the syntax element values, video decoder 30 may determine the number of clock ticks corresponding to a difference in POC values being equal to 1 and use the determined number of clock ticks as input for determining CPB underflow or overflow, for example, during decoding of an encoded picture included in the encoded bitstream.

In some examples, video encoder 20 may generate an encoded bitstream to signal the number of units in the time scale and ticks at most once in each of the VPS syntax structure and the VUI syntax structure for a given coded video sequence. That is, in a given VPS syntax structure for an encoded bitstream, video encoder 20 may signal the number of units in the time scale and ticks syntax element at most once. Similarly, in a given VUI syntax structure for an encoded bitstream (e.g., the VUI portion of an SPS syntax structure), video encoder 20 may signal the number of units in the time scale and ticks syntax element at most once. As a result, video encoder 20 operating according to the techniques described herein may reduce the number of instances of the time scale syntax element (time_scale according to WD9) and the number of units in the ticks (num_units_in_tick according to WD9) syntax element in an encoded bitstream. Additionally, in some cases, video encoder 20 may generate an encoded bitstream to signal the time scale and the number of units in clock ticks directly in each of the VPS and VUI syntax structures for a given coded video sequence, rather than in an HRD parameter syntax structure incorporated within the VPS and/or VUI syntax structures.

According to the techniques described herein, video encoder 20 may test the conformance of an encoded bitstream (generated by video encoder 20 to signal the time scale and the number of units in clock ticks at most once in each of the VPS and VUI syntax structures for a given coded timing) by decoding the encoded bitstream to determine the time scale and the number of units in clock ticks from the VPS syntax structure of the encoded bitstream, in which the encoded bitstream encodes the number of units in the time scale and clock tick syntax element at most once. In some cases, video encoder 20 may test the conformance of the encoded bitstream by decoding the encoded bitstream to determine the time scale and the number of units in clock ticks from the VUI syntax structure of the encoded bitstream, in which the encoded bitstream encodes the number of units in the time scale and clock tick syntax element at most once. The time scale and the number of units in clock ticks may not be signaled in an HRD parameter syntax structure incorporated within the VPS and/or VUI syntax structures. Video encoder 20 may use the determined time scale and the determined number of units in the clock tick as input for determining CPB underflow or overflow, eg, during decoding of an encoded picture included in the encoded bitstream.

In some cases, at destination device 14, video decoder 30 under test may, in some cases, receive a representation of an encoded bitstream generated by video encoder 20 to signal the time scale and the number of units in the ticks at most once in each of the VPS and VUI syntax structures for a given coded video sequence. Video decoder 30 may decode the encoded bitstream to determine the time scale and the number of units in the ticks from the VPS syntax structure of the encoded bitstream, in which the encoded bitstream encodes the number of units in the time scale and ticks syntax element at most once. In some cases, video decoder 30 may test the conformance of the encoded bitstream by decoding the encoded bitstream to determine the time scale and the number of units in the ticks from the VUI syntax structure of the encoded bitstream, in which the encoded bitstream encodes the number of units in the time scale and ticks syntax element at most once. The time scale and the number of units in the ticks may not be signaled in the HRD parameter syntax structure incorporated into the VPS and/or VUI syntax structures. Video decoder 30 may use the determined time scale and the determined number of units in the clock tick as input for determining CPB underflow or overflow, eg, during decoding of an encoded picture included in the encoded bitstream.

In some examples, video encoder 20 may generate an encoded bitstream to signal a flag in a VPS syntax structure for one or more coded video sequences that indicates whether the POC value of each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. This indication flag may alternatively be referred to as a POC proportional to timing indication flag. As a result, video encoder 20 may reduce the number of instances of indication in the timing information signaled for multiple layers of a coded video sequence and/or a scalable video bitstream having multiple layers. In some cases, video encoder 20 may include this flag in the VPS syntax structure only if the number of units in the timescale and clock tick syntax elements are also included. In this way, video encoder 20 can avoid signaling specific timing information (i.e., whether the POC value of each picture in the coded video sequence (except the first picture in the coded video sequence in decoding order) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence) when the clock tick information required to use the POC proportional to timing indication does not already exist).

According to the techniques described herein, video encoder 20 may test an encoded bitstream (generated by video encoder 20) for conformance to a signaled POC proportional to timing indication flag in a VPS syntax structure for one or more coded video sequences. Video encoder 20 may test the conformance of the encoded bitstream by decoding the encoded bitstream to determine the value of the flag. Video encoder 20 may additionally or alternatively test the encoded bitstream generated by video encoder 20 to signal the flag in the VPS syntax structure only if the flag is also included in the time scale and clock tick syntax element. Video encoder 20 may use the determined value of the POC proportional to timing indication flag and the number of units in the time scale and clock tick syntax element as input to determine, for example, CPB underflow or overflow during decoding of an encoded picture included in the encoded bitstream.

In some cases, at destination device 14, video decoder 30 under test may, in some cases, receive a representation of an encoded bitstream generated by video encoder 20 to signal a POC proportional to timing indication flag in a VPS syntax structure for one or more coded video sequences. Video decoder 30 may test the encoded bitstream for compliance by decoding the encoded bitstream to determine the value of the flag. Video decoder 30 may additionally or alternatively test the encoded bitstream generated by video decoder 30 to signal the flag in the VPS syntax structure only if the flag is also included in the time scale and clock tick syntax element. Video decoder 30 may use the determined value of the POC proportional to timing indication flag and the number of units in the time scale and clock tick syntax element as input to, for example, determine CPB underflow or overflow during decoding of an encoded picture included in the encoded bitstream.

FIG2 is a block diagram illustrating an example video encoder 20 that may implement the techniques described in this disclosure. Video encoder 20 may perform intra- and inter-coding of video blocks within a video slice. Intra-coding relies on spatial prediction to reduce or remove spatial redundancy in video within a given video frame or picture. Inter-coding relies on temporal prediction to reduce or remove temporal redundancy in video within adjacent frames or pictures of a video sequence. Intra-mode (I-mode) may refer to any of several spatially-based compression modes. Inter-modes, such as unidirectional prediction (P-mode) or bidirectional prediction (B-mode), may refer to any of several temporally-based compression modes.

2 , video encoder 20 includes a partitioning unit 35, a prediction module 41, a reference picture memory 64, a summer 50, a transform module 52, a quantization unit 54, and an entropy encoding unit 56. Prediction module 41 includes a motion estimation unit 42, a motion compensation unit 44, and an intra-prediction module 46. For video block reconstruction, video encoder 20 also includes an inverse quantization unit 58, an inverse transform module 60, and a summer 62. A deblocking filter (not shown in FIG. 2 ) may also be included to filter block boundaries to remove blockiness artifacts from the reconstructed video. If necessary, the deblocking filter will typically filter the output of summer 62. In addition to the deblocking filter, additional loop filters (in-loop or post-loop) may also be used.

As shown in FIG2 , video encoder 20 receives video data, and partitioning unit 35 partitions the data into video blocks. This partitioning may also include partitioning into slices, tiles, or other larger units, as well as video block partitioning according to a quadtree structure of LCUs and CUs, for example. Video encoder 20 generally illustrates components that encode video blocks within a video slice to be encoded. The slice may be divided into multiple video blocks (and possibly into arrays of video blocks referred to as tiles). Prediction module 41 may select one of multiple possible coding modes for the current video block, such as one of multiple intra-coding modes or one of multiple inter-coding modes, based on error results (e.g., coding rate and distortion level). Prediction module 41 may provide the resulting intra-coded or inter-coded block to summer 50 to generate residual block data, and to summer 62 to reconstruct the encoded block for use as a reference picture.

Intra-prediction module 46 within prediction module 41 may perform intra-predictive coding of the current video block relative to one or more neighboring blocks in the same frame or slice as the current block to be coded to provide spatial compression. Motion estimation unit 42 and motion compensation unit 44 within prediction module 41 may perform inter-predictive coding of the current video block relative to one or more prediction blocks in one or more reference pictures to provide temporal compression.

Motion estimation unit 42 may be configured to determine an inter-prediction mode for a video slice according to a predetermined pattern for a video sequence. The predetermined pattern may designate a video slice in the sequence as a P slice, a B slice, or a GPB slice. Motion estimation unit 42 and motion compensation unit 44 may be highly integrated but are illustrated separately for conceptual purposes. Motion estimation performed by motion estimation unit 42 is the process of generating motion vectors, which estimate the motion of video blocks. For example, a motion vector may indicate the displacement of a PU of a video block within a current video frame or picture relative to a prediction block within a reference picture.

A prediction block is a block that is found to closely match a PU of the video block to be coded in terms of pixel difference, which may be determined by sum of absolute difference (SAD), sum of squared difference (SSD), or other difference metrics. In some examples, video encoder 20 may calculate values for sub-integer pixel positions of a reference picture stored in reference picture memory 64. For example, video encoder 20 may interpolate values for quarter-pixel positions, eighth-pixel positions, or other fractional pixel positions of the reference picture. Thus, motion estimation unit 42 may perform a motion search relative to full-pixel positions and fractional pixel positions and output a motion vector with fractional pixel precision.

Motion estimation unit 42 calculates a motion vector for a PU of a video block in an inter-coded slice by comparing the position of the PU with the position of a prediction block of a reference picture. The reference picture may be selected from a first reference picture list (List 0) or a second reference picture list (List 1), each of which identifies one or more reference pictures stored in reference picture memory 64. Motion estimation unit 42 sends the calculated motion vector to entropy encoding unit 56 and motion compensation unit 44.

Motion compensation performed by motion compensation unit 44 may involve retrieving or generating a prediction block based on a motion vector determined by motion estimation (possibly performing interpolation to sub-pixel precision). Upon receiving the motion vector for the PU of the current video block, motion compensation unit 44 may locate the prediction block to which the motion vector points in one of the reference picture lists. Video encoder 20 forms a residual video block by subtracting the pixel values of the prediction block from the pixel values of the current video block being coded, thereby forming pixel difference values. The pixel difference values form the residual data for the block and may include both luma and chroma difference components. Summer 50 represents the one or more components that perform this subtraction operation. Motion compensation unit 44 may also generate syntax elements 55 associated with the video block and video slice for use by video decoder 30 when decoding the video block of the video slice.

Motion compensation unit 44 may generate syntax elements 55 that conform to a syntax structure according to the techniques described in this disclosure. In some examples, video encoder 20 may generate syntax elements 55 to directly signal, in a video parameter set (VPS) syntax structure associated with the video block, or in a video usability information (VUI) portion of a sequence parameter set (SPS) syntax structure, all syntax elements that define a condition for signaling the number of clock ticks corresponding to a difference in picture order count (POC) values being equal to one. In other words, rather than signaling syntax elements for the condition for signaling the number of clock ticks corresponding to a difference in picture order count (POC) values being equal to one in another syntax structure (e.g., an HRD parameter syntax structure) incorporated into the VPS syntax structure or the VUI portion of the SPS syntax structure, motion compensation unit 44 generates an encoded bitstream to signal the syntax elements defining the condition in the VPS and/or VUI syntax structures, without reference to another syntax structure potentially incorporated into either or both the VPS and VUI syntax structures.

In some examples, motion compensation unit 44 may generate syntax element 55 to signal the time scale and the number of units in the clock tick at most once in each of the VPS and VUI syntax structures for a given coded video sequence. That is, in a given VPS syntax structure for an encoded bitstream, motion compensation unit 44 may generate syntax element 55 to signal the number of units in the time scale and clock tick syntax element at most once. Similarly, in a given VUI syntax structure for an encoded bitstream (e.g., the VUI portion of an SPS syntax structure), motion compensation unit 44 may generate syntax element 55 to signal the number of units in the time scale and clock tick syntax element at most once. In addition, in some cases, motion compensation unit 44 may generate syntax element 55 to signal the time scale and the number of units in the clock tick directly in each of the VPS and VUI syntax structures for a given coded video sequence, rather than in an HRD parameter syntax structure incorporated within the VPS and/or VUI syntax structures.

In some examples, motion compensation unit 44 may generate syntax element 55 to signal a flag in a VPS syntax structure for one or more coded video sequences that indicates whether the POC value for each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. This indication flag may alternatively be referred to as a POC proportional to timing indication flag. As a result, motion compensation unit 44 may reduce the number of instances of indication in the timing information signaled for multiple layers of a coded video sequence and/or a scalable video bitstream having multiple layers. In some cases, motion compensation unit 44 may include this flag in the VPS syntax structure only if the number of units in the timescale and clock tick syntax elements are also included. In this manner, motion compensation unit 44 may avoid signaling specific timing information (i.e., whether the POC value for each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence) if the clock tick information required to use the POC proportional to timing indication does not already exist.

Example changes to the HEVC WD9 text to implement the above-described techniques for generating syntax element 55 are as follows (other unmentioned portions may be unmodified relative to HEVC WD9):

The following is an example of a video parameter set RBSP syntax structure modified to address one or more of the above issues (the underlined syntax is an addition to the video parameter set RBSP syntax structure of HEVC WD9; other syntax may be unchanged relative to HEVC WD9):

Table 4: Example video parameter set RBSP syntax structure

Table 4 defines the newly added syntax elements according to the following video parameter set (VPS) RBSP semantics:

vps_timing_info_present_flag equal to 1 specifies that vps_num_units_in_tick, vps_time_scale, and vps_poc_proportional_to_timing_flag are present in the video parameter set. vps_timing_info_present_flag equal to 0 specifies that vps_num_units_in_tick, vps_time_scale, and vps_poc_proportional_to_timing_flag are not present in the video parameter set.

vps_num_units_in_tick is the number of time units of a clock operating at a frequency vps_time_scale Hz corresponding to one increment of the clock tick counter (called a clock tick). The value of vps_num_units_in_tick should be greater than 0. The clock tick in seconds is equal to the quotient of vps_num_units_in_tick divided by vps_time_scale. For example, when the picture rate of the video signal is 25 Hz, vps_time_scale may be equal to 27,000,000 and vps_num_units_in_tick may be equal to 1,080,000, and thus the clock tick may be 0.04 seconds.

vps_time_scale is the number of time units that pass in one second. For example, a time coordinate system that uses a 27 MHz frequency to measure time has a vps_time_scale of 27,000,000. The value of vps_time_scale should be greater than 0.

vps_poc_proportional_to_timing_flag equal to 1 indicates that the picture order count value of each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. vps_poc_proportional_to_timing_flag equal to 0 indicates that the picture order count value of each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) may or may not be proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence.

vps_num_ticks_poc_diff_one_minus1 plus 1 specifies the number of clock ticks corresponding to the difference in picture order count values equal to 1. The value of vps_num_ticks_poc_diff_one_minus1 should be in the range of 0 to 2^32-1, inclusive.

The following is an example of a VUI parameter syntax structure modified to address one or more of the above issues (underlined syntax is an addition to the VUI parameter syntax structure of HEVC WD9; syntax in italics is removed from the VUI parameter syntax structure of HEVC WD9; other syntax may be unchanged relative to HEVC WD9):

Table 5: VUI parameter syntax structure for instance modification

Table 5 defines the newly added syntax elements according to the following VUI parameter semantics (also removing the semantics for the removed syntax elements):

sps_timing_info_present_flag equal to 1 specifies that sps_num_units_in_tick, sps_time_scale, and sps_poc_proportional_to_timing_flag are present in the vui_parameters() syntax structure. sps_timing_info_present_flag equal to 0 specifies that sps_num_units_in_tick, sps_time_scale, and sps_poc_proportional_to_timing_flag are not present in the vui_parameters() syntax structure.

sps_num_units_in_tick is the number of time units of a clock operating at a frequency of sps_time_scale Hz corresponding to one increment of the clock tick counter (called a clock tick). sps_num_units_in_tick shall be greater than 0. The clock tick in seconds is equal to the quotient of sps_num_units_in_tick divided by sps_time_scale. For example, when the picture rate of the video signal is 25 Hz, sps_time_scale may be equal to 27,000,000 and sps_num_units_in_tick may be equal to 1,080,000, and thus the clock tick may be equal to 0.04 seconds (see equation (1)). When vps_num_units_in_tick is present in the video parameter set referenced by the sequence parameter set, sps_num_units_in_tick (when present) shall be equal to vps_num_units_in_tick.

The formula for deriving the variable ClockTick (also referred to herein as "clock tick") is modified as follows:

Equation (1)

sps_time_scale is the number of time units that pass in one second. For example, a time coordinate system using a 27 MHz frequency to measure time has an sps_time_scale of 27,000,000. The value of sps_time_scale should be greater than 0. When vps_time_scale is present in a video parameter set referenced by a sequence parameter set, sps_time_scale (if present) should be equal to vps_time_scale.

sps_poc_proportional_to_timing_flag equal to 1 indicates that the picture order count value of each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. sps_poc_proportional_to_timing_flag equal to 0 indicates that the picture order count value of each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) may or may not be proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence. When vps_poc_proportional_to_timing_flag is present in the video parameter set referenced by the sequence parameter set, sps_poc_proportional_to_timing_flag (when present) shall be equal to vps_poc_proportional_to_timing_flag.

sps_num_ticks_poc_diff_one_minus1 plus 1 specifies the number of clock ticks corresponding to the difference in picture order count values equal to 1. The value of sps_num_ticks_poc_diff_one_minus1 shall be in the range of 0 to 2^32-1, inclusive. When vps_num_ticks_poc_diff_one_minus1 is present in the video parameter set referenced by the sequence parameter set, sps_num_ticks_poc_diff_one_minus1 (when present) shall be equal to sps_num_ticks_poc_diff_one_minus1.

The following is an example of an HRD parameter syntax structure modified to address one or more of the above issues (with italicized syntax removed from the HRD parameter syntax structure of HEVC WD9):

Table 6: Syntax structure of HRD parameters modified by instance

The semantics of the syntax elements removed according to the modified HRD parameter syntax structure of the example in Table 6 are also removed.

As an alternative to the inter-prediction performed by motion estimation unit 42 and motion compensation unit 44 as described above, intra-prediction module 46 may perform intra-prediction on the current block. Specifically, intra-prediction module 46 may determine an intra-prediction mode to use to encode the current block. In some examples, intra-prediction module 46 may encode the current block using various intra-prediction modes, for example, during separate encoding passes, and intra-prediction module 46 (or mode selection unit 40, in some examples) may select an appropriate intra-prediction mode to use from the tested modes. For example, intra-prediction module 46 may calculate rate-distortion values for various tested intra-prediction modes using rate-distortion analysis and select the intra-prediction mode with the best rate-distortion characteristics from among the tested modes. Rate-distortion analysis generally determines the amount of distortion (or error) between an encoded block and the original, unencoded block that was encoded to produce the encoded block, as well as the bit rate (that is, the number of bits) used to produce the encoded block. Intra-prediction module 46 may calculate ratios from the distortions and rates for the various encoded blocks to determine which intra-prediction mode exhibits the best rate-distortion value for the block.

In any case, after selecting an intra-prediction mode for a block, intra-prediction module 46 may provide information indicating the selected intra-prediction mode for the block to entropy encoding unit 56. Entropy encoding unit 56 may encode the information indicating the selected intra-prediction mode according to the techniques of this disclosure. Video encoder 20 may include configuration data in the transmitted bitstream that may include multiple intra-prediction mode index tables and multiple modified intra-prediction mode index tables (also referred to as codeword mapping tables), definitions of contexts for encoding various blocks, and indications of the most probable intra-prediction mode, intra-prediction mode index tables, and modified intra-prediction mode index tables for each of the contexts.

After prediction module 41 generates a prediction block for the current video block via inter-prediction or intra-prediction, video encoder 20 forms a residual video block by subtracting the prediction block from the current video block. The residual video data in the residual block may be contained in one or more TUs and applied to transform module 52. Transform module 52 transforms the residual video data into residual transform coefficients using a transform, such as a discrete cosine transform (DCT) or a conceptually similar transform. Transform module 52 may transform the residual video data from the pixel domain to a transform domain, such as the frequency domain.

Transform module 52 may send the resulting transform coefficients to quantization unit 54. Quantization unit 54 quantizes the transform coefficients to further reduce the bit rate. The quantization process may reduce the bit depth associated with some or all of the coefficients. The degree of quantization may be modified by adjusting a quantization parameter. In some examples, quantization unit 54 may then perform a scan of the matrix containing the quantized transform coefficients. Alternatively, entropy encoding unit 56 may perform the scan.

After quantization, entropy encoding unit 56 performs entropy encoding on the quantized transform coefficients. For example, entropy encoding unit 56 may perform context adaptive variable length coding (CAVLC), context adaptive binary arithmetic coding (CABAC), syntax-based context adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or another entropy encoding method or technique. Following entropy encoding by entropy encoding unit 56, the encoded bitstream may be transmitted to video decoder 30 or archived for later transmission or retrieval by video decoder 30. Entropy encoding unit 56 may also entropy encode the motion vectors and other syntax elements for the current video slice being encoded.

Inverse quantization unit 58 and inverse transform module 60 apply inverse quantization and inverse transform, respectively, to reconstruct the residual block in the pixel domain, for example, for later use as a reference block of a reference picture. Motion compensation unit 44 may calculate a reference block by adding the residual block to a prediction block of one of the reference pictures in one of the reference picture lists. Motion compensation unit 44 may also apply one or more interpolation filters to the reconstructed residual block to calculate sub-integer pixel values for motion estimation. Summer 62 adds the reconstructed residual block to the motion compensated prediction block produced by motion compensation unit 44 to produce a reference block for storage in reference picture memory 64 (sometimes referred to as a decoded picture buffer (DPB)). The reference block may be used by motion estimation unit 42 and motion compensation unit 44 as a reference block for inter-frame prediction of a block in a subsequent video frame or picture.

Video encoder 20 may optionally include a hypothetical reference decoder (HRD) 57 (illustrated as optional using dashed lines) to check the conformance of the encoded bitstream produced by the elements of video encoder 20 to the buffer model defined for HRD 57. HRD 57 may detect HRD conformance for Type I and/or Type II bitstreams or bitstream subsets. The parameter sets required for the operation of HRD 57 are signaled through one of two types of HRD parameter sets: NAL HRD parameters and VCL HRD parameters. As described above, the HRD parameter sets may be incorporated into the SPS syntax structure and/or the VPS syntax structure.

HRD 57 may test the compliance of video blocks and associated syntax elements 55 with the requirements specified by one or more bitstream conformance tests as defined in a video coding specification (e.g., HEVC WD9) or a subsequent specification (e.g., HEVC WD10). For example, HRD 57 may test the conformance of the encoded bitstream by processing syntax elements 55 to determine, from a VPS syntax structure of the coded video sequence or in a VUI portion of an SPS syntax structure, a syntax element that defines a condition for the case where a number of clock ticks corresponding to a difference in POC values equal to 1 is signaled. If the condition holds true according to the syntax element value, HRD 57 may determine the number of clock ticks corresponding to a difference in POC values equal to 1 and use the determined number of clock ticks as input for determining CPB underflow or overflow, for example, during decoding of an encoded picture included in the encoded bitstream. The term “processing” as used herein with respect to syntax elements may refer to extraction, decoding and extraction, reading, parsing, and any other applicable operation or combination of operations to obtain syntax elements in a form usable by decoder/HRD 57 .

As another example, HRD 57 may test the conformance of the encoded bitstream by decoding the encoded bitstream to determine the time scale and the number of units in the ticks from the VPS syntax structure of syntax element 55, where the time scale and the number of units in the ticks syntax element are encoded at most once in the VPS syntax structure. In some cases, HRD 57 may test the conformance of the encoded bitstream by decoding syntax element 55 to determine the time scale and the number of units in the ticks from the VUI syntax structure of the encoded bitstream, where the time scale and the number of units in the ticks syntax element are encoded at most once in the VUI syntax structure. The time scale and the number of units in the ticks may not be signaled in an HRD parameter syntax structure incorporated into the VPS and/or VUI syntax structures. HRD 57 may use the determined time scale and the determined number of units in the ticks as inputs to, for example, determine CPB underflow or overflow during decoding of an encoded picture included in the encoded bitstream.

According to the techniques described herein, HRD 57 can test the conformance of the encoded bitstream by decoding the value of the POC proportional to timing indication flag from the VPS syntax structure of syntax elements 55 for one or more coded video sequences. HRD 57 can additionally or alternatively test the conformance of the encoded bitstream by decoding the value of the POC proportional to timing indication flag in the VPS syntax structure only if the number of units in the time scale and clock tick syntax element is also included. HRD 57 can use the determined value of the POC proportional to timing indication flag and the number of units in the time scale and clock tick syntax element as input to, for example, determine CPB underflow or overflow during decoding of an encoded picture included in the encoded bitstream.

FIG3 is a block diagram illustrating an example video decoder 76 that may implement the techniques described in this disclosure. In the example of FIG3, video decoder 76 includes a coded picture buffer (CPB) 78, an entropy decoding unit 80, a prediction module 81, an inverse quantization unit 86, an inverse transform unit 88, a summer 90, and a decoded picture buffer (DPB) 92. Prediction module 81 includes a motion compensation unit 82 and an intra-prediction module 84. In some examples, video decoder 76 may perform a decoding pass that is generally reciprocal to the encoding pass described with respect to video encoder 20 from FIG2. Video decoder 76 may represent an example instance of video decoder 30 of destination device 14 or hypothetical reference decoder 57 of FIG2.

CPB 78 stores coded pictures from the coded picture bitstream. In one example, CBP 78 is a first-in, first-out buffer containing access units (AUs) in decoding order. An AU is a set of network abstraction layer (NAL) units associated with each other according to a specified classification rule, the NAL units are consecutive in decoding order, and each contains only one coded picture. Decoding order is the order in which pictures are decoded and may be different from the order in which pictures are displayed (i.e., display order). The operation of the CPB may be specified by a hypothetical reference decoder (HRD).

During the decoding process, video decoder 76 receives an encoded video bitstream representing video blocks and associated syntax elements of an encoded video slice from video encoder 20. Entropy decoding unit 80 of video decoder 76 decodes the bitstream to produce quantized coefficients, motion vectors, and other syntax elements 55. Entropy decoding unit 80 forwards the motion vectors and other syntax elements 55 to prediction module 81. Video decoder 76 may receive syntax elements 55 at the video slice level and/or the video block level. The encoded video bitstream may include timing information signaled according to the techniques described below. For example, the encoded video bitstream may include a video parameter set (VPS), a sequence parameter set (SPS), or any combination thereof having a syntax structure according to the techniques described herein to signal parameters for HRD operations.

When the video slice is coded as an intra-coded (I) slice, intra prediction module 84 of prediction module 81 may generate prediction data for the video block of the current video slice based on the signaled intra prediction mode and data from previously decoded blocks of the current frame or picture. When the video frame is coded as an inter-coded (i.e., B, P, or GPB) slice, motion compensation unit 82 of prediction module 81 generates a prediction block for the video block of the current video slice based on the motion vectors and other syntax elements 55 received from entropy decoding unit 80. The prediction block may be generated from one of the reference pictures within one of the reference picture lists. Video decoder 76 may construct reference frame lists: List 0 and List 1 using a default construction technique based on the reference pictures stored in DPB 92.

Motion compensation unit 82 determines prediction information for a video block of the current video slice by parsing the motion vectors and other syntax elements 55, and uses the prediction information to produce a prediction block for the current video block being decoded. For example, motion compensation unit 82 uses some of the received syntax elements 55 to determine a prediction mode (e.g., intra-prediction or inter-prediction) for coding the video block of the video slice, an inter-prediction slice type (e.g., a B slice, a P slice, or a GPB slice), construction information for one or more of the reference picture lists for the slice, a motion vector for each inter-coded video block of the slice, an inter-prediction state for each inter-coded video block of the slice, and other information used to decode video blocks in the current video slice.

Motion compensation unit 82 may also perform interpolation based on interpolation filters. Motion compensation unit 82 may calculate interpolated values for sub-integer pixels of a reference block using the interpolation filters used by video encoder 20 during encoding of the video block. In this case, motion compensation unit 82 may determine the interpolation filters used by video encoder 20 from the received syntax elements 55 and use the interpolation filters to produce a prediction block.

Inverse quantization unit 86 inverse quantizes, or dequantizes, the quantized transform coefficients provided in the bitstream and decoded by entropy decoding unit 80. The inverse quantization process may include calculating, using video encoder 20, a quantization parameter that determines, for each video block in a video slice, a degree of quantization and, likewise, a degree of inverse quantization that should be applied. Inverse transform unit 88 applies an inverse transform, such as an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process, to the transform coefficients to produce a residual block in the pixel domain.

After motion compensation unit 82 generates a predictive block for the current video block based on the motion vector and other syntax elements 55, video decoder 76 forms a decoded video block by summing the residual block from inverse transform unit 88 with the corresponding predictive block generated by motion compensation unit 82. Summer 90 represents the component(s) that perform this summing operation. If necessary, a deblocking filter may also be applied to filter the decoded block to remove blockiness artifacts. Other loop filters (in the decoding loop or after the decoding loop) may also be used to smooth pixel transitions or otherwise improve video quality. The decoded video blocks in a given frame or picture are then stored in DPB 92, which stores reference pictures used for subsequent motion compensation. DPB 92 also stores the decoded video for later presentation on a display device, such as display device 32 of FIG. 1 . Similar to CPB 78, in one example, the operation of DPB 92 may be specified by a hypothetical reference decoder (HRD).

As described in this disclosure, encoder 20 and decoder 76 represent examples of devices configured to perform the techniques described in this disclosure for signaling timing in a video coding process. Thus, the operations described in this disclosure for signaling time may be performed by encoder 20, decoder 76, or both. In some cases, encoder 20 may signal timing information, and decoder 76 may receive such timing information, e.g., for use in defining one or more HRD features, characteristics, parameters, or conditions.

In some cases, the video decoder 76 may be a video decoder under test 76 (or VUT). The video decoder 76 may receive a representation of the encoded bitstream generated by the video encoder 20 to directly signal all syntax elements defining a condition for the following case: the number of clock ticks corresponding to the difference in picture order count (POC) values being equal to 1 is signaled in the VPS syntax structure of the syntax elements 55 for the coded video sequence or in the VUI portion of the SPS syntax structure. The video decoder 76 may decode the encoded bitstream to determine, from the VPS syntax structure of the coded video sequence or in the VUI portion of the SPS syntax structure, the syntax elements defining the condition for the following case: the number of clock ticks corresponding to the difference in POC values being equal to 1 is signaled in the VPS syntax structure of the coded video sequence or in the VUI portion of the SPS syntax structure. If the condition holds true according to the syntax element value, the video decoder 76 may determine the number of clock ticks corresponding to the difference in POC values being equal to 1 and use the determined number of clock ticks as input for determining, for example, CPB 78 underflow or overflow during decoding of an encoded picture included in the encoded bitstream.

In another example, video encoder 20 may receive a representation of an encoded bitstream generated by video encoder 20 to signal the time scale and the number of units in the clock tick at most once in each of the VPS and VUI syntax structures of syntax elements 55 for a given coded video sequence. Video decoder 76 may decode the encoded bitstream to determine the time scale and the number of units in the clock tick from the VPS syntax structure of the encoded bitstream, where the encoded bitstream encodes the number of units in the time scale and clock tick syntax elements at most once in the VPS syntax structure. In some cases, video decoder 76 may test the conformance of the encoded bitstream by decoding the encoded bitstream to determine the time scale and the number of units in the clock tick from the VUI syntax structure of the encoded bitstream, where the encoded bitstream encodes the number of units in the time scale and clock tick syntax elements at most once in the VUI syntax structure. The time scale and the number of units in the clock tick may not be signaled in the HRD parameter syntax structure incorporated into the VPS and/or VUI syntax structures. Video decoder 76 may use the determined time scale and the determined number of units in the clock tick as input for determining CPB 78 underflow or overflow, eg, during decoding of an encoded picture included in the encoded bitstream.

In another example, the video decoder 76 may receive a representation of an encoded bitstream generated by the video encoder 20 to signal a POC proportional to timing indication flag in a VPS syntax structure of syntax elements 55 of one or more coded video sequences. The video decoder 76 may test the encoded bitstream for compliance by decoding the encoded bitstream to determine the value of the flag. The video decoder 76 may additionally or alternatively test the encoded bitstream generated by the video decoder 76 to signal the flag in the VPS syntax structure only if the flag is also included in the time scale and clock tick syntax element. The video decoder 76 may use the determined value of the POC proportional to timing indication flag and the number of units in the time scale and clock tick syntax element as input to, for example, determine CPB 78 underflow or overflow during decoding of an encoded picture included in the encoded bitstream.

FIG4 is a block diagram illustrating an example coding structure 100 for a reference picture set. Coding structure 100 includes slices 102A-102E (collectively, "slices 102"). A picture order count 108 associated with coding structure 100 represents the output order of corresponding slices in the reference picture set. For example, I slice 102A (POC value 0) will be output first, while b slice 102B (POC value 1) will be output second. A decoding order 110 associated with coding structure 100 represents the decoding order of corresponding slices in the reference picture set. For example, I slice 102A will be output first (decoding order 1), while b slice 102B will be output second (decoding order 2).

Arrow 104 indicates the output time of a picture along a temporal continuum t. Time interval 106 represents a time interval corresponding to a difference in picture order count (POC) values equal to 1. Time interval 106 may include a number of clock ticks, which may depend on a time scale (corresponding to, for example, an oscillator frequency, e.g., 27 MHz, defining a time coordinate system for signaled information) and a number of time units of a clock operating at a time scale corresponding to one increment of a clock tick counter (referred to as a "clock tick"). According to the techniques described herein, video encoder 20 may generate a bitstream to directly signal syntax elements defining a condition for the following case: signaling the number of clock ticks corresponding to a difference in picture order count (POC) values equal to 1, in a video parameter set (VPS) syntax structure for a coded video sequence or in a video usability information (VUI) portion of a sequence parameter set (SPS) syntax structure.

FIG5 is a flowchart illustrating an example method of operation according to the techniques described in the present disclosure. Video encoder 20 encodes pictures of a video sequence to produce a coded video sequence (200). Video encoder 20 further generates parameter sets for the coded video sequence. The parameter sets may include parameters encoded according to a sequence parameter set (SPS) syntax structure and/or according to a video parameter set (VPS) syntax structure. According to the techniques described herein, video encoder 20 encodes syntax elements for the number of units in clock ticks and time scales directly into the VPS syntax structure of the coded video sequence and/or directly into the SPS syntax structure (202). The term "directly" indicates that such encoding can be generated without incorporating syntax elements for the number of units in clock ticks and time scales defined for an independent parameter set syntax structure in the VPS syntax structure or the SPS syntax structure (as applicable), e.g., corresponding to a hypothetical reference decoder (HRD) parameter set as defined in HEVC WD9.

In addition, video encoder 20 encodes a condition for the following case directly into the VPS syntax structure and/or SPS syntax structure of the coded video sequence: the number of clock ticks corresponding to the difference in picture order count (POC) values being equal to one is signaled (204). The condition may include one or more syntax elements representing variables of a Boolean formula, in which case video encoder 20 may encode each such syntax element directly into the VPS syntax structure and/or SPS syntax structure of the coded video sequence. Video encoder 20 outputs the coded video sequence and the VPS syntax structure and/or SPS syntax structure for the coded video sequence (206). In some cases, video encoder 20 outputs these structures to the HRD of video encoder 20.

6A-6B are flowcharts illustrating an example method of operation according to the techniques described in this disclosure. In FIG. 6A , video encoder 20 encodes pictures of a video sequence to produce a coded video sequence ( 300 ). Video encoder 20 also generates a parameter set for the coded video sequence. The parameter set may include parameters encoded according to a video parameter set (VPS) syntax structure. According to the techniques described herein, video encoder 20 encodes syntax elements for the number of units in a clock tick and the time scale directly and at most once into the VPS syntax structure of the coded video sequence ( 302 ). In some cases, even where the VPS syntax structure includes multiple instances of HRD parameters, the VPS syntax structure may include a single syntax element for each of the number of units in a clock tick and the time scale by encoding the syntax elements directly into the VPS syntax structure (at most once) rather than into the HRD parameter set (or any other incorporated parameter set syntax structure). Video encoder 20 outputs the coded video sequence and the VPS syntax structure for the coded video sequence ( 304 ). In some cases, video encoder 20 outputs these structures to the HRD of video encoder 20 .

In FIG6B , video encoder 20 encodes pictures of a video sequence to produce a coded video sequence ( 310 ). Video encoder 20 also generates a parameter set for the coded video sequence. The parameter set may include parameters encoded according to a sequence parameter set (SPS) syntax structure. According to the techniques described herein, video encoder 20 encodes syntax elements for the number of units in a clock tick and the time scale directly, and at most once, into the SPS syntax structure of the coded video sequence ( 312 ). In some cases, even where the SPS syntax structure includes multiple instances of HRD parameters, the SPS syntax structure may include a single syntax element for each of the number of units in a clock tick and the time scale by encoding the syntax elements directly into the SPS syntax structure (at most once) rather than into the HRD parameter set (or any other incorporated parameter set syntax structure). Video encoder 20 outputs the coded video sequence and the SPS syntax structure for the coded video sequence ( 314 ). In some cases, video encoder 20 outputs these structures to the HRD of video encoder 20. In some cases, video encoder 20 encodes syntax elements for the number of units and the time scale in clock ticks into both the VPS syntax structure and the SPS syntax structure of the coded video sequence.

FIG7 is a flowchart illustrating an example method of operation according to the techniques described in this disclosure. Video encoder 20 encodes pictures of a video sequence to produce a coded video sequence (400). Video encoder 20 further generates a parameter set for the coded video sequence. The parameter set may include parameters encoded according to a video parameter set (VPS) syntax structure. If timing information is to be included, e.g., for defining an HRD buffer model (“yes” branch of 402), video encoder 20 encodes a syntax element having a value directly into the VPS syntax structure of the coded video sequence that specifies whether a picture order count (POC) value for each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence (404). The syntax element may be semantically similar to the poc_proportional_to_timing_flag defined by HEVC WD9. The timing information may represent the number of units in clock ticks and the time scale.

If the value of the syntax element is true ("yes" branch of 406), video encoder 20 also encodes a syntax element for the number of clock ticks corresponding to the difference in picture order count values equal to one (408). Because video encoder 20 encodes the syntax element into the VPS, the value of the syntax element may apply to all layers or all possible bitstream subsets of the scalable video bitstream because the VPS represents the highest layer parameter set and describes the overall characteristics of the coded picture sequence.

If timing information is not to be included in the VPS syntax structure (the "NO" branch of 402), video encoder 20 does not encode either: a syntax element indicating that the POC is proportional to the timing information; or a syntax element corresponding to the number of clock ticks for which the difference in picture order count values is equal to one. If the POC is not proportional to the timing information (i.e., the value is false) (the "NO" branch of 406), video encoder 20 does not encode a syntax element corresponding to the number of clock ticks for which the difference in picture order count values is equal to one.

Video encoder 20 outputs the coded video sequence and the VPS syntax structures for the coded video sequence (410). In some cases, video encoder 20 outputs these structures to the HRD of video encoder 20.

FIG8 is a flowchart illustrating an example method of operation according to the techniques described in this disclosure. A hypothetical reference decoder 57 (hereinafter "decoder") of video decoder device 30 or video encoder device 20 receives a coded video sequence and a video parameter set (VPS) syntax structure and/or a sequence parameter set (SPS) syntax structure for the coded video sequence (500). The coded video sequence and/or syntax structure may be encoded into a bitstream including one or more encoded pictures.

The decoder processes the VPS syntax structure and/or the SPS syntax structure to extract syntax elements that specify conditions directly in the VPS syntax structure and/or the SPS syntax structure for the case where a number of clock ticks corresponding to a difference in picture order count (POC) values equal to one is signaled (502). The conditions may include one or more syntax elements representing variables of a Boolean formula, in which case the decoder may process each such syntax element directly from the VPS syntax structure and/or the SPS syntax structure of the coded video sequence.

The decoder additionally processes the VPS syntax structure and/or the SPS syntax structure to extract syntax elements for the number of units in clock ticks and the time scale directly from the VPS syntax structure and/or directly from the SPS syntax structure of the coded video sequence (504). The decoder may then verify conformance of the coded video sequence to a video buffering model defined at least in part by values for the number of units in clock ticks and the time scale for the condition, as extracted from the VPS syntax structure and/or the SPS syntax structure and as read from the corresponding syntax elements (506).

9A-9B are flowcharts illustrating example methods of operation according to the techniques described in this disclosure. In FIG9A , a hypothetical reference decoder 57 (hereinafter “decoder”) of a video decoder device 30 or a video encoder device 20 receives a coded video sequence and a video parameter set (VPS) syntax structure for the coded video sequence (600). The coded video sequence and/or the VPS syntax structure may be encoded into a bitstream including one or more encoded pictures.

According to the techniques described herein, a decoder processes a VPS syntax structure to extract syntax elements for the number of units and time scale in clock ticks that appear directly (and at most once) in the VPS syntax structure for a coded video sequence (602). The decoder can then verify the conformance of the coded video sequence to a video buffering model defined at least in part by the values for the number of units and time scale in clock ticks as extracted from the VPS syntax structure and as read from the corresponding syntax elements (604).

9B , a decoder receives a coded video sequence and a sequence parameter set (SPS) syntax structure for the coded video sequence ( 610 ).The coded video sequence and/or the SPS syntax structure may be encoded into a bitstream that includes one or more encoded pictures.

According to the techniques described herein, the decoder processes the SPS syntax structure to extract syntax elements for the number of units and time scale in clock ticks that appear directly (and at most once) in the SPS syntax structure for the coded video sequence (612). The decoder can then verify the conformance of the coded video sequence to a video buffering model defined at least in part by the values of the number of units and time scale in clock ticks as extracted from the SPS syntax structure and as read from the corresponding syntax elements (614).

FIG10 is a flowchart illustrating an example method of operation according to the techniques described in this disclosure. In FIG10 , a hypothetical reference decoder 57 (hereinafter “decoder”) of a video decoder device 30 or a video encoder device 20 receives a coded video sequence and a video parameter set (VPS) syntax structure for the coded video sequence (700). The coded video sequence and/or the VPS syntax structure may be encoded into a bitstream including one or more encoded pictures.

The decoder processes the VPS syntax structure to extract a syntax element that specifies a picture order count value for each picture in the coded video sequence (except the first picture in decoding order in the coded video sequence) that is proportional to the output time of the picture relative to the output time of the first picture in the coded video sequence (702). If the value of the syntax element is true, the decoder further processes the VPS syntax structure to extract a syntax element for a number of clock ticks corresponding to a difference of one in the picture order count values (706). The decoder can then verify conformance of the coded video sequence to a video buffering model defined at least in part by a value for a number of clock ticks corresponding to a difference of one in the picture order count values, as extracted from the VPS syntax structure and as read from the corresponding syntax element (708).

In one or more instances, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to tangible media such as data storage media, or communication media that includes any media that facilitates the transfer of a computer program from one place to another (e.g., according to a communication protocol). In this manner, computer-readable media may generally correspond to (1) non-transitory tangible computer-readable storage media or (2) communication media such as signals or carrier waves. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and/or data structures for implementing the techniques described in this disclosure. A computer program product may include computer-readable media.

By way of example, and not limitation, computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Likewise, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but rather refer to non-transient, tangible storage media. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs use lasers to reproduce data optically. Combinations of the above should also be included within the scope of computer-readable media.

Instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor," as used herein, may refer to any of the aforementioned structures or any other structure suitable for implementing the techniques described herein. Additionally, in some aspects, the functionality described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated into a combined codec. Furthermore, the techniques may be fully implemented in one or more circuits or logic elements.

The techniques of this disclosure can be implemented in a wide variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs), or sets of ICs (e.g., chipsets). The various components, modules, or units described herein are intended to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require implementation by distinct hardware units. In fact, as described above, the various units may be combined in a codec hardware unit in conjunction with appropriate software and/or firmware, or provided by a collection of interoperating hardware units, including one or more processors as described above.

Various embodiments have been described. These and other embodiments are within the scope of the following claims.

Claims (50)

1. A method for processing video data, the method comprising: Receives a decoded video sequence comprising encoded images of a video sequence; and Receive timing parameters for the decoded video sequence, the timing parameters including the following indication in the video parameter set VPS syntax structure referenced by the decoded video sequence: whether the image order count (POC) value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 2. The method of claim 1, wherein the instruction includes the vps_poc_proportional_to_timing_flag syntax element. 3. The method of claim 1, wherein receiving timing parameters for the decoded video sequence further comprises: The number of clock ticks in the VPS syntax structure corresponding to a difference of one between the POC values is received only if the indication indicates that the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 4. The method according to claim 1, Receiving the instruction includes receiving the instruction only if the syntax element for the number of units in the time scale and clock ticks is present in the VPS syntax structure. 5. The method of claim 1, wherein receiving the timing parameters for the decoded video sequence further comprises: Receive an indication of whether the syntax element for the number of units in the time scale and clock tick exists in the VPS syntax structure. 6. The method of claim 5, wherein the indication in the VPS syntax structure regarding the presence of the syntax element for the number of units in the time scale and clock ticks includes the vps_timing_info_present_flag syntax element. 7. The method of claim 1, wherein receiving the timing parameters for the decoded video sequence further comprises: The number of clock beats corresponding to a difference of one between the POC value and the time interval between the output time of the first image in the decoded video sequence (SPS syntax structure referenced by the decoded video sequence) is received only if the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 8. The method of claim 1, wherein the indication includes a first indication, and wherein receiving the timing parameters for the decoded video sequence further includes: The second indication in the VUI portion of the SPS syntax structure is received only if the syntax element for the number of units in the time scale and clock beat exists in the video availability information (VUI) portion of the sequence parameter set (SPS) syntax structure referenced by the decoded video sequence: whether the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 9. The method of claim 8, wherein the second instruction comprises the sps_poc_proportional_to_timing_flag syntax element. 10. The method of claim 1, wherein receiving the timing parameters for the decoded video sequence further comprises: The following indication is received from the Video Availability Information (VUI) section of the Sequence Parameter Set (SPS) syntax structure referenced by the decoded video sequence: whether the syntax elements for the number of units in the time scale and clock beats exist in the VUI section of the SPS syntax structure. 11. The method of claim 10, wherein the indication in the VUI portion of the SPS syntax structure referenced by the decoded video sequence regarding the presence of syntax elements for the number of units in the time scale and clock beats in the VUI portion of the SPS syntax structure includes the sps_timing_info_present_flag syntax element. 12. The method of claim 1, wherein receiving the decoded video sequence includes receiving a decoded bitstream, the decoded bitstream including a bit sequence forming a representation of the encoded picture, the method further comprising: verifying the conformity of the bitstream to a video buffer model of a decoded picture buffer and a decoded picture buffer, the video buffer model being defined at least in part by the indication. 13. The method of claim 1, wherein the timing parameters include timing parameters for hypothetical reference decoding operations. 14. A method for encoding video data, the method comprising: Images of an encoded video sequence are used to generate a decoded video sequence including the encoded images; and The timing parameters for the decoded video sequence are signaled by signaling the following indication in the Video Parameter Set (VPS) syntax structure referenced by the decoded video sequence: whether the Picture Order Count (POC) value of each picture in the decoded video sequence that is not the first picture in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first picture in the decoded video sequence and the output time of the picture. 15. The method of claim 14, wherein the instruction includes the vps_poc_proportional_to_timing_flag syntax element. 16. The method of claim 14, wherein signaling the timing parameters for the decoded video sequence further comprises: The number of clock ticks corresponding to a difference of one between the POC values is signaled in the VPS syntax structure only when the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 17. The method according to claim 14, Sending the indication by signaling includes sending the indication only when the number of syntax elements used for time scales and clock ticks are present in the VPS syntax structure. 18. The method of claim 14, wherein signaling the timing parameters for the decoded video sequence further comprises: The VPS syntax structure is signaled to indicate whether a syntax element for the number of units in the time scale and clock tick exists in the VPS syntax structure. 19. The method of claim 18, wherein the indication in the VPS syntax structure regarding the presence of the syntax element for the number of units in the time scale and clock ticks includes the vps_timing_info_present_flag syntax element. 20. The method of claim 14, wherein sending the timing parameters for the decoded video sequence by signaling further comprises: The number of clock beats corresponding to a difference of one between the POC values is signaled in the Video Usability Information (VUI) portion of the Sequence Parameter Set (SPS) syntax structure referenced by the decoded video sequence only when the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the first image. 21. The method of claim 14, wherein the indication includes a first indication, and wherein signaling the timing parameters for the decoded video sequence further includes: A second indication is signaled in the VUI portion of the SPS syntax structure only when the syntax element for the number of units in the time scale and clock beat exists in the video availability information (VUI) portion of the sequence parameter set (SPS) syntax structure referenced by the decoded video sequence: whether the POC value of each image in the decoded video sequence that is not a first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 22. The method of claim 21, wherein the second instruction comprises the sps_poc_proportional_to_timing_flag syntax element. 23. The method of claim 14, wherein sending the timing parameters for the decoded video sequence by signaling further comprises: The following indication is sent by signal in the Video Availability Information (VUI) section of the Sequence Parameter Set (SPS) syntax structure referenced by the decoded video sequence: whether the syntax elements for the number of units in the time scale and clock beat exist in the VUI section of the SPS syntax structure. 24. The method of claim 23, wherein the indication in the VUI portion of the SPS syntax structure referenced by the decoded video sequence regarding the presence of syntax elements for the number of units in the time scale and clock beats in the VUI portion of the SPS syntax structure includes the sps_timing_info_present_flag syntax element. 25. An apparatus for processing video data, the apparatus comprising: Processor, configured to: Receives a decoded video sequence comprising encoded images of a video sequence; and Receive timing parameters for the decoded video sequence, the timing parameters including the following indication in the video parameter set VPS syntax structure referenced by the decoded video sequence: whether the image order count (POC) value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 26. The apparatus of claim 25, wherein the instruction includes the vps_poc_proportional_to_timing_flag syntax element. 27. The apparatus of claim 25, wherein, in order to receive timing parameters for the decoded video sequence, the processor is further configured to: The number of clock ticks in the VPS syntax structure corresponding to a difference of one between the POC values is received only if the indication indicates that the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 28. The apparatus according to claim 25, In order to receive the instruction, the processor is further configured to receive the instruction only if a number of syntax elements for the time scale and clock ticks are present in the VPS syntax structure. 29. The apparatus of claim 25, wherein, in order to receive the timing parameters for the decoded video sequence, the processor is further configured to receive an indication of the presence of a syntax element in the VPS syntax structure for the number of units in the time scale and clock beats. 30. The apparatus of claim 29, wherein the indication in the VPS syntax structure regarding the presence of the syntax element for the number of units in the time scale and clock ticks includes the vps_timing_info_present_flag syntax element. 31. The apparatus of claim 25, wherein, in order to receive the timing parameters for the decoded video sequence, the processor is further configured to: The number of clock beats corresponding to a difference of one between the POC value and the time interval between the output time of the first image in the decoded video sequence (SPS syntax structure referenced by the decoded video sequence) is received only if the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 32. The apparatus of claim 25, wherein the indication includes a first indication, and wherein, in order to receive the timing parameters for the decoded video sequence, the processor is further configured to: The second indication in the VUI portion of the SPS syntax structure is received only if the syntax element for the number of units in the time scale and clock beat exists in the video availability information (VUI) portion of the sequence parameter set (SPS) syntax structure referenced by the decoded video sequence: whether the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 33. The apparatus of claim 32, wherein the second instruction includes the sps_poc_proportional_to_timing_flag syntax element. 34. The apparatus of claim 25, wherein, in order to receive the timing parameters for the decoded video sequence, the processor is further configured to: The following indication is received from the Video Availability Information (VUI) section of the Sequence Parameter Set (SPS) syntax structure referenced by the decoded video sequence: whether the syntax elements for the number of units in the time scale and clock beats exist in the VUI section of the SPS syntax structure. 35. The apparatus of claim 34, wherein the indication in the VUI portion of the SPS syntax structure referenced by the decoded video sequence regarding the presence of syntax elements for the number of units in the time scale and clock beats in the VUI portion of the SPS syntax structure includes the sps_timing_info_present_flag syntax element. 36. The apparatus of claim 25, wherein, in order to receive the decoded video sequence, the processor is further configured to: Receive a decoded bitstream, the decoded bitstream comprising a bit sequence forming a representation of the encoded image; and verify the conformity of the bitstream to a video buffer model of a decoded image buffer and a decoded image buffer, the video buffer model being defined at least in part by the indication. 37. The apparatus of claim 25, wherein the timing parameters include timing parameters for hypothetical reference decoding operations. 38. An apparatus for encoding video data, the apparatus comprising: Processor, configured to: Images of an encoded video sequence are used to generate a decoded video sequence including the encoded images; and The timing parameters for the decoded video sequence are signaled by signaling the following indication in the Video Parameter Set (VPS) syntax structure referenced by the decoded video sequence: whether the Picture Order Count (POC) value of each picture in the decoded video sequence that is not the first picture in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first picture in the decoded video sequence and the output time of the picture. 39. The apparatus of claim 38, wherein the instruction includes the vps_poc_proportional_to_timing_flag syntax element. 40. The apparatus of claim 38, wherein, in order to signal the timing parameters for the decoded video sequence, the processor is further configured to: The number of clock ticks corresponding to a difference of one between the POC values is signaled in the VPS syntax structure only when the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 41. The apparatus according to claim 38, In order to send the indication by signal, the processor is further configured to send the indication by signal only when a number of syntax elements for the time scale and clock ticks are present in the VPS syntax structure. 42. The apparatus of claim 38, wherein, in order to signal the timing parameters for the decoded video sequence, the processor is further configured to: The VPS syntax structure is signaled to indicate whether a syntax element for the number of units in the time scale and clock tick exists in the VPS syntax structure. 43. The apparatus of claim 42, wherein the indication in the VPS syntax structure regarding the presence or absence of the syntax element for the number of units in the time scale and clock ticks includes the vps_timing_info_present_flag syntax element. 44. The apparatus of claim 38, wherein, in order to signal the timing parameters for the decoded video sequence, the processor is further configured to: The number of clock beats corresponding to a difference of one between the POC values is signaled in the Video Usability Information (VUI) portion of the Sequence Parameter Set (SPS) syntax structure referenced by the decoded video sequence only when the POC value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the first image. 45. The apparatus of claim 38, wherein the indication includes a first indication, and wherein, in order to signal the timing parameters for the decoded video sequence, the processor is further configured to: A second indication is signaled in the VUI portion of the SPS syntax structure only when the syntax element for the number of units in the time scale and clock beat exists in the video availability information (VUI) portion of the sequence parameter set (SPS) syntax structure referenced by the decoded video sequence: whether the POC value of each image in the decoded video sequence that is not a first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image. 46. The apparatus of claim 45, wherein the second instruction comprises the sps_poc_proportional_to_timing_flag syntax element. 47. The apparatus of claim 38, wherein, in order to signal the timing parameters for the decoded video sequence, the processor is further configured to: The following indication is sent by signal in the Video Availability Information (VUI) section of the Sequence Parameter Set (SPS) syntax structure referenced by the decoded video sequence: whether the syntax elements for the number of units in the time scale and clock beat exist in the VUI section of the SPS syntax structure. 48. The apparatus of claim 47, wherein the indication in the VUI portion of the SPS syntax structure referenced by the decoded video sequence regarding the presence of syntax elements for the number of units in the time scale and clock beats in the VUI portion of the SPS syntax structure includes the sps_timing_info_present_flag syntax element. 49. An apparatus for processing video data, comprising: A means for receiving a decoded video sequence comprising encoded images of a video sequence; and A means for receiving timing parameters for the decoded video sequence, the timing parameters including the following indication in the video parameter set (VPS) syntax structure referenced by the decoded video sequence: whether the picture order count (POC) value of each picture in the decoded video sequence that is not the first picture in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first picture in the decoded video sequence and the output time of the picture. 50. A non-transitory computer-readable storage medium storing instructions for processing video data, the instructions causing the one or more processors, when executed, to perform the following operations: Receives a decoded video sequence comprising encoded images of a video sequence; and Receive timing parameters for the decoded video sequence, the timing parameters including the following indication in the video parameter set VPS syntax structure referenced by the decoded video sequence: whether the image order count (POC) value of each image in the decoded video sequence that is not the first image in the decoded video sequence according to the decoding order is proportional to the time interval between the output time of the first image in the decoded video sequence and the output time of the image.