HK1207469B - Image sensor pixel cell with switched deep trench isolation structure - Google Patents

Abstract

The present invention relates to an image sensor pixel cell with switched deep trench isolation structure. A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is disposed in the first region and coupled between the photodiode and the floating diffusion to selectively transfer image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure lined with a dielectric layer inside the DTI structure is disposed in the semiconductor material isolates the first region on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. Doped semiconductor material inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

Description

Image sensor pixel cell with switching deep trench isolation structure

Technical Field

The present invention relates generally to semiconductor processing. More specifically, examples of the invention relate to semiconductor processing of image sensor pixel cells.

Background

The image capture device includes an image sensor and an imaging lens. The imaging lens focuses light onto the image sensor to form an image, and the image sensor converts the light into an electrical signal. The electrical signals are output from the image capture device to other components of the host electronic system. For example, the electronic system may be a mobile phone, a computer, a digital camera, or a medical device.

There is a continuing need to reduce the size of image sensors, which results in smaller pixel cells for image sensors having the same resolution. As the size of pixel cells continues to decrease, the problems of pixel cell crosstalk and unwanted signal transfer between pixel cells continue to become increasingly challenging. In addition, when the image sensor is miniaturized, the pixel cell contained therein has an increased dark current rate.

Disclosure of Invention

One embodiment of the present invention discloses a pixel cell, comprising: a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge; a floating diffusion disposed in a well region disposed in the epitaxial layer in the first region of the semiconductor material; a transfer transistor disposed in the first region of the semiconductor material and coupled between the photodiode and the floating diffusion to selectively transfer the image charge from the photodiode to the floating diffusion; a Deep Trench Isolation (DTI) structure disposed in the semiconductor material, wherein the DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on another side of the DTI structure, wherein the DTI structure includes: a dielectric layer lining an inside surface of the DTI structure; and a doped semiconductor material disposed over the dielectric layer inside the DTI structure, wherein the doped semiconductor material disposed inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

One embodiment of the present invention discloses an imaging system, comprising: a pixel array having a plurality of pixel cells, wherein each of the plurality of pixel cells includes: a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge; a floating diffusion disposed in a well region disposed in the epitaxial layer in the first region of the semiconductor material; a transfer transistor disposed in the first region of the semiconductor material and coupled between the photodiode and the floating diffusion to selectively transfer the image charge from the photodiode to the floating diffusion; a Deep Trench Isolation (DTI) structure disposed in the semiconductor material, wherein the DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on another side of the DTI structure, wherein the DTI structure includes: a dielectric layer lining an inside surface of the DTI structure; and a doped semiconductor material disposed over the dielectric layer inside the DTI structure, wherein the doped semiconductor material disposed inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to readout image data from the plurality of pixel cells.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Figure 1 schematically illustrates one example of a pixel cell that may be included in an example image sensor having a switched deep trench isolation structure, according to teachings of this disclosure.

Figure 2 is a cross-sectional view illustrating one example of a pixel cell having a switched deep trench isolation structure in accordance with the teachings of this disclosure.

Figure 3 illustrates a timing diagram of signals in an example pixel cell with a switched deep trench isolation structure, according to the teachings of this disclosure.

Figure 4 is a diagram illustrating one example of an imaging system including a pixel array having pixel cells with switched deep trench isolation structures, according to the teachings of this disclosure.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention. Additionally, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the specific details need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.

Reference throughout this specification to "one embodiment," "an embodiment," "one example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. The particular features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. Additionally, it should be appreciated that the figures provided herewith are for explanation purposes to persons skilled in the art and that the drawings are not necessarily drawn to scale.

An example in accordance with the teachings of this disclosure describes a pixel cell having a switched deep trench isolation structure in accordance with the teachings of this disclosure. In one example, the switched deep trench isolation structure is a biased capacitive type isolation structure. As will be shown, in various examples, pixel cells according to the teachings of the present disclosure utilize switched and biased deep trench isolation structures, which reduces pixel crosstalk and also achieves a higher fill factor by featuring a moderately doped N-type epitaxial region between the switched deep trench isolation structures. Thus, in an example, no P-type doped region is needed to line the isolation structure and consume space in the photodiode region where light is illuminated. Increased full well capacity is achieved in accordance with the teachings of the present invention since no P-type doped region is required to line the isolation structure. Furthermore, as will be shown, by switching the deep trench isolation structures with a negative readout pulse voltage in various examples, the lag time is reduced because once transfer of image charge begins, the image charge is pushed out of the photodiode to the floating diffusion of the pixel cell, according to the teachings of the present invention.

To illustrate, figure 1 schematically illustrates one example of a pixel cell 100 having a switched deep trench isolation structure that may be one of a plurality of pixel cells arranged in an example pixel array 192, according to the teachings of this disclosure. In the depicted example, pixel cell 100 is illustrated as being a four-transistor ("4T") pixel cell included in a backside illuminated image sensor, according to the teachings of this disclosure. It should be appreciated that pixel cell 100 is one possible example of a pixel circuit architecture for implementing each pixel cell within pixel array 192 of fig. 1. However, it should be understood that other examples in accordance with the teachings of this disclosure are not necessarily limited to 4T pixel architectures. Persons of ordinary skill in the art having benefit of the present disclosure will appreciate that the present teachings also apply to 3T designs, 5T designs, and various other pixel architectures according to the teachings of the present disclosure.

In the example depicted in fig. 1, pixel cell 100 includes a photodiode ("PD") 120 to accumulate image charge, a transfer transistor T1130, a reset transistor T2160, a floating diffusion ("FD") 170, a source follower ("SF") transistor T3180, and a select transistor T4190. During operation, the transfer transistor T1130 receives a transfer signal TX that transfers image charges accumulated in the photodiode PD 120 to the floating diffusion FD 170. In one example, the floating diffusion FD 170 may be coupled to a storage capacitor for temporarily storing image charge. In one example and as will be discussed in further detail below, according to the teachings of the present disclosure, a deep trench isolation structure (shown in figure 2 below) is included in the pixel cell 100 and is selectively coupled to a readout pulse voltage to reduce image lag in response to the transfer transistor T1130 selectively transferring image charge from the photodiode PD 120 to the floating diffusion FD 170 in response to a transfer signal TX.

As shown in the illustrated example, a reset transistor T2160 is coupled between the power rail VDD and the floating diffusion FD 170 to reset the pixel cell 100 (e.g., discharge or charge the floating diffusion FD 170 and the photodiode PD 120 to a preset voltage) in response to a reset signal RST. The floating diffusion FD 170 is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between power rail VDD and select transistor T4. SF transistor T3 operates as a source follower amplifier providing a high impedance connection to the floating diffusion FD 170. The select transistor T4190 selectively couples the output of the pixel cell 100 to the readout column bit line 193 in response to a select signal SEL.

In one example, control circuitry, an example of which is described in further detail below, generates a TX signal, a RST signal, a SEL signal, and a readout pulse voltage that are selectively coupled to the deep trench isolation. In examples where the pixel array 192 operates with a global shutter, a global shutter signal is coupled to the gate of each transfer transistor T1130 in the pixel array 192 to simultaneously begin the charge transfer from the photodiode PD 120 of each pixel. Alternatively, a rolling shutter signal may be applied to a group of pass transistors T1130 in accordance with the teachings of this disclosure.

Figure 2 is a cross-sectional view illustrating one example of a pixel cell 200 having a switched deep trench isolation structure 201 in accordance with the teachings of the present disclosure. In one example, it is noted that the example pixel cell 200 of fig. 2 is a cross-sectional view of the example pixel cell 100 of fig. 1, and it is to be understood that similarly named and numbered elements mentioned below are linked and function as described above. As shown in the depicted example, pixel cell 200 includes a photodiode 220 disposed in epitaxial layer 203 in first region 209 of semiconductor material 215 to accumulate image charge in response to light 295. In one example, the first region 209 includes pixel circuitry of the pixel cell 200. In the illustrated example, epitaxial region 203 is moderately doped with an N-type dopant. In one example, the back side 216 of the semiconductor material 215 is illuminated with light 295. Thus, light 295 is directed through the back side 216 of the semiconductor material 215 to generate image charges in the photodiode 220. Thus, in the illustrated example, an anti-reflective ("AR") coating/negative charge layer 207 is disposed on the backside 216 surface of the semiconductor material 215. In another example, it is understood that light 295 may be directed through the front side of semiconductor material 215 to generate image charges in a front side illuminated photodiode in accordance with the teachings of this disclosure. Referring back to the example depicted in fig. 2, photodiode 220 is a partially fixed photodiode (PPPD) and is coupled to a ground reference voltage GND via contact 221, as shown.

Continuing with the example described in fig. 2, pixel cell 200 also includes floating diffusion FD270 disposed in well region 204 disposed in epitaxial layer 203 in first region 209 of semiconductor material 215, as shown. In the illustrated example, the well region 204 in which the floating diffusion FD270 is disposed includes a P-type dopant and is also coupled to a ground reference voltage GND via contact 219, as shown. In the example, the pixel cell 200 also includes a transfer transistor 230 disposed in the first region 209 of semiconductor material 215 and coupled between the photodiode 220 and the floating diffusion FD 270. As shown in the example, transfer transistor 230 includes a transfer gate Tg and is coupled to selectively transfer image charge accumulated in photodiode 220 to floating diffusion FD270 in response to a transfer signal TX according to the teachings of this disclosure.

As shown in fig. 2, the pixel cell 200 also includes one or more Deep Trench Isolation (DTI) structures 201 disposed in the semiconductor material 215. In one example, the one or more DTI structures 201 extend all the way to the backside 216 surface of the semiconductor material 215, as shown. Thus, as shown in the depicted example, one or more DTI structures 201 isolate a first region 209 of semiconductor material 215 on one side of the DTI structure 201 from one or more other regions on the other side of the DTI structure 201, such as, for example, a second region 211 of semiconductor material 215. In one example, the second region 211 includes peripheral circuitry of the pixel cell 200. In the depicted example, the peripheral circuitry in the second region 211 of the pixel cell 200 includes standard CMOS circuitry including a standard CMOS N-well 213 and a P-well 214 disposed in a deep P-well 212 disposed in an N-type doped epitaxial layer 203 of semiconductor material 215, as shown.

In one example, each of the one or more DTI structures 201 is a capacitive type isolation structure that includes a dielectric layer 202 lining an inside surface of each of the one or more DTI structures 201. In one example, the dielectric layer is an oxide layer having a thickness of about 100 angstroms, including, for example, silicon dioxide. Each of the one or more DTI structures 201 further includes a doped semiconductor material 218 disposed over the dielectric layer 202 inside the DTI structure 201. In the depicted example, the doped semiconductor material 218 disposed inside each of the one or more DTI structures 201 is selectively coupled to the readout pulse voltage 205 through contact 222 in response to the transfer transistor 230 selectively transferring image charge accumulated in the photodiode 220 to the floating diffusion FD270 in response to the transfer signal TX according to the teachings of this disclosure. In one example, the doped semiconductor material 218 disposed inside each of the one or more DTI structures 201 is lightly doped polysilicon including P-type dopants such that the built-in work function difference between the P-type doped semiconductor material 218 and the N-type doped epitaxial layer 203 of the photodiode 220 forms an electric field that facilitates reducing dark current in the pixel cell 200. In one example, the contact 222 is a metal contact that is an optional metal grid contact to the doped semiconductor material 218 disposed on the backside 216 of the semiconductor material 215, as shown.

In the example depicted in fig. 2, the switched readout pulse voltage 205 is a negative voltage pulse applied during the readout sequence of image charge from photodiode 220 to floating diffusion FD270 via transfer transistor 230 to reduce image lag. In an example, the switched readout pulse voltage 205 is then selectively decoupled from the doped semiconductor material 218 after the image charge has been transferred from the photodiode 220 to the floating diffusion FD270 by the transfer transistor 230. In one example, when the switched readout pulse voltage 205 is not applied, the bias voltage 206 is coupled to the doped semiconductor material 218 via the contact 222. In one example, the bias voltage 206 is a negative bias to generate a field in the pixel cell 200 to reduce dark current in the pixel cell 200. In one example, the negative bias voltage 206 has a magnitude that is less than the magnitude of the switched sense pulse voltage 205.

FIG. 3 illustrates a timing diagram 300 of example signals in the example pixel cell 100 of FIG. 1 and/or the example pixel cell 200 of FIG. 2 having a switched deep trench isolation structure, according to the teachings of this disclosure. As illustrated in the depicted example, the timing diagram 300 shows: prior to time T0, a reset function occurs in which a reset signal RST 360 is applied to, for example, the gate terminal of reset transistor T2160 of fig. 1, and a transmit signal TX 330 is applied to, for example, the gate terminal of transfer transistor T1130 of fig. 1, which is also illustrated as gate terminal Tg of transfer transistor 230 of fig. 2. During this reset period prior to time T0 in fig. 3, the voltage at the floating diffusion FD 170 and photodiode PD 120 of fig. 1 or floating diffusion FD270 and photodiode 220 of fig. 2 is reset to the power rail VDD voltage, which discharges or charges the floating diffusion FD 170 and photodiode PD 120 to a preset voltage.

FIG. 3 illustrates: after the reset function is completed at time T0, the photodiode is illuminated with light during the exposure period between times T0 and T1 to accumulate image charge in the photodiode, illustrated in fig. 2 as light 295 directed through the backside 216 of the semiconductor material 215 to the photodiode 220, for example. As shown, for example, in fig. 3, during the exposure period between times T0 and T1, DTI structure 301 is coupled to receive a negative bias signal 306, which in one example, helps generate an electric field in the pixel cell to reduce dark current in the pixel cell.

Fig. 3 shows: after the exposure function is completed at time T1, the image charge accumulated in the photodiode is then transferred from the photodiode to the floating diffusion via the transfer transistor during the transfer function between times T1 and T3. Fig. 3 shows: this process begins with a pass transistor signal TX 330 applied to turn on a pass transistor, such as, for example, pass transistor 130 of fig. 1 or pass transistor 230 of fig. 2. In one example, after a time delay 317 from T1 to T2, a DTI structure (such as, for example, DTI structure 201 of fig. 2) is coupled to receive a negative readout pulse voltage 305 in response to a transfer transistor signal TX 330 selectively transferring image charge from a photodiode to a floating diffusion, as shown in fig. 3. In one example, the time delay between times T1 and T2 is greater than or equal to zero. In one example, the negative pulse of the readout pulse voltage 305 during the readout sequence of image charge from the photodiode 220 reduces image lag according to the teachings of this disclosure because the electric field created by the negative pulse of the readout pulse voltage 305 helps push the image charge accumulated in the photodiode 220 to the floating diffusion FD270 via the transfer transistor 230 according to the teachings of this disclosure. In the example, after the transfer function is completed at time T3, the DTI structure is then selectively decoupled from the readout pulse voltage 305, and the negative bias voltage 306 is again applied to the DTI structure.

FIG. 3 also illustrates: the partially fixed photodiode 320 and P-well 304 of the pixel cell, which may correspond to the partially fixed photodiode 220 and P-well 204 as illustrated in FIG. 2, are coupled to the ground reference voltage GND via contacts 221 and 219. In one example, since the partially fixed photodiode 220 and the P-well 204 are associated with a ground reference voltage GND, as shown for example in fig. 2, the threshold voltage of the transfer transistor 230 does not bounce when the DTI structure 201 is coupled to selectively receive the negative readout pulse voltage 305 and couple noise into the N-epi 203 side of the photodiode 220.

Figure 4 is a diagram illustrating one example of an imaging system 491 that includes a pixel array 492 having pixel cells with switched deep trench isolation structures in accordance with the teachings of the present invention. As shown in the depicted example, the imaging system 491 includes a pixel array 492 coupled to control circuitry 498 and readout circuitry 494 coupled to functional logic 496.

In one example, the pixel array 492 is a two-dimensional (2D) array of imaging sensors or pixel cells (e.g., pixel cells P1, P2, …, Pn). In one example, each pixel cell is a CMOS imaging pixel. Note that pixel cells P1, P2, …, Pn in pixel array 492 may be examples of pixel cell 100 of fig. 1 and/or pixel cell 200 of fig. 2, and that similarly named and numbered elements mentioned below are related and function similarly as described above. As illustrated, each pixel cell is arranged into rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc.

In one example, after each pixel cell has accumulated its image data or image charge, the image data is read out by readout circuitry 494 over readout column bit line 493 and then transferred to function logic 496. In various examples, readout circuitry 494 can include amplification circuitry, analog-to-digital (ADC) conversion circuitry, or others. Function logic 496 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one example, the readout circuitry 494 may readout a row of image data at a time along readout column bit lines 493 (illustrated) or may readout the image data simultaneously using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels.

In one example, the control circuit 498 is coupled to the pixel array 492 to control an operating characteristic of the pixel array 492. For example, the control circuit 498 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal used to simultaneously enable all pixels within the pixel array 492 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row of pixels, each column of pixels, or each group of pixels is sequentially enabled during successive acquisition windows.

The above description of illustrated examples of the invention, including what is described in the Abstract of the invention, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications can be made without departing from the broader spirit and scope of the invention.

These modifications can be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The specification and figures are accordingly to be regarded in an illustrative rather than a restrictive sense.

Claims (31)

1. A pixel cell, comprising:

a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge;

a floating diffusion disposed in a well region disposed in the epitaxial layer in the first region of the semiconductor material;

a transfer transistor disposed in the first region of the semiconductor material and coupled between the photodiode and the floating diffusion to selectively transfer the image charge from the photodiode to the floating diffusion;

a Deep Trench Isolation (DTI) structure disposed in the semiconductor material, wherein the DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on another side of the DTI structure, wherein the DTI structure includes:

a dielectric layer lining an inside surface of the DTI structure; and

a doped semiconductor material disposed over the dielectric layer inside the DTI structure, wherein the doped semiconductor material disposed inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

2. The pixel cell of claim 1, wherein the doped semiconductor material disposed inside the DTI structure is selectively coupled to the readout pulse voltage to reduce image lag when transferring the image charge from the photodiode to the floating diffusion via the transfer transistor.

3. The pixel cell of claim 1, wherein the doped semiconductor material disposed inside the DTI structure is selectively coupled to the readout pulse voltage after a delay time after selectively switching the transistor to transfer the image charge from the photodiode to the floating diffusion.

4. The pixel cell of claim 1, wherein the doped semiconductor material disposed inside the DTI structure is selectively decoupled from the readout pulse voltage after the image charge has been transferred from the photodiode to the floating diffusion by the transfer transistor.

5. The pixel cell of claim 1, wherein the readout pulse voltage is a negative pulse voltage that is selectively coupled to the doped semiconductor material disposed inside the DTI structure in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

6. The pixel cell of claim 1, wherein the doped semiconductor material disposed inside the DTI structure is coupled to a negative bias voltage to generate a field in the pixel cell to reduce dark current in the pixel cell, wherein the negative bias voltage has a magnitude that is less than a magnitude of the readout pulse voltage.

7. The pixel cell of claim 1, wherein the photodiode and the well region in which the floating diffusion is disposed are coupled to a ground reference voltage.

8. The pixel cell of claim 1, further comprising a metal grid contact coupled to the doped semiconductor material disposed inside the DTI structure.

9. The pixel cell of claim 1, wherein the epitaxial layer in the first region of the semiconductor material is an N-doped epitaxial layer and the well region disposed in the epitaxial layer in the first region of the semiconductor material is a P-doped well region.

10. The pixel cell of claim 1, further comprising peripheral circuitry disposed in the second region of the semiconductor material on the other side of the DTI structure, wherein the DTI structure isolates the first region of the semiconductor material from the peripheral circuitry disposed in the second region of the semiconductor material.

11. The pixel cell of claim 1, wherein said DTI structure extends to a backside surface of said semiconductor material.

12. The pixel cell of claim 1, wherein said pixel cell is adapted to be illuminated from a backside of said semiconductor material.

13. The pixel cell of claim 11, further comprising an anti-reflective coating disposed on the backside of the semiconductor material.

14. The pixel cell of claim 1, wherein said dielectric layer lining said inside surface of said DTI structure comprises silicon dioxide.

15. The pixel cell of claim 1, wherein the doped semiconductor material disposed over the dielectric layer inside the DTI structure comprises lightly doped polysilicon.

16. An imaging system, comprising:

a pixel array having a plurality of pixel cells, wherein each of the plurality of pixel cells includes:

a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge;

a floating diffusion disposed in a well region disposed in the epitaxial layer in the first region of the semiconductor material;

a transfer transistor disposed in the first region of the semiconductor material and coupled between the photodiode and the floating diffusion to selectively transfer the image charge from the photodiode to the floating diffusion;

a Deep Trench Isolation (DTI) structure disposed in the semiconductor material, wherein the DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on another side of the DTI structure, wherein the DTI structure includes:

a dielectric layer lining an inside surface of the DTI structure; and

a doped semiconductor material disposed over the dielectric layer inside the DTI structure, wherein the doped semiconductor material disposed inside the DTI structure is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion;

control circuitry coupled to the pixel array to control operation of the pixel array; and

readout circuitry coupled to the pixel array to readout image data from the plurality of pixel cells.

17. The imaging system of claim 16, further comprising functional logic coupled to the readout circuitry to store the image data read out from the plurality of pixel cells.

18. The imaging system of claim 16, wherein the doped semiconductor material disposed inside the DTI structure is selectively coupled to the readout pulse voltage to reduce image lag when transferring the image charge from the photodiode to the floating diffusion via the transfer transistor.

19. The imaging system of claim 16, wherein the doped semiconductor material disposed inside the DTI structure is selectively coupled to the readout pulse voltage after a delay time after selectively switching the transistor to transfer the image charge from the photodiode to the floating diffusion.

20. The imaging system of claim 16, wherein the doped semiconductor material disposed inside the DTI structure is selectively decoupled from the readout pulse voltage after the image charge has been transferred from the photodiode to the floating diffusion by the transfer transistor.

21. The imaging system of claim 16, wherein the readout pulse voltage is a negative pulse voltage that is selectively coupled to the doped semiconductor material disposed inside the DTI structure in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.

22. The imaging system of claim 16, wherein the doped semiconductor material disposed inside the DTI structure is coupled to a negative bias voltage to generate a field in the pixel cell to reduce dark current in the pixel cell, wherein the negative bias voltage has a magnitude less than a magnitude of the readout pulse voltage.

23. The imaging system of claim 16, wherein the photodiode and the well region in which the floating diffusion is disposed are coupled to a ground reference voltage.

24. The imaging system of claim 16, further comprising a metal grid contact coupled to the doped semiconductor material disposed inside the DTI structure.

25. The imaging system of claim 16, wherein the epitaxial layer in the first region of the semiconductor material is an N-doped epitaxial layer and the well region disposed in the epitaxial layer in the first region of the semiconductor material is a P-doped well region.

26. The imaging system of claim 16, further comprising peripheral circuitry disposed in the second region of the semiconductor material on the other side of the DTI structure, wherein the DTI structure isolates the first region of the semiconductor material from the peripheral circuitry disposed in the second region of the semiconductor material.

27. The imaging system of claim 16, wherein the DTI structure extends to a backside surface of the semiconductor material.

28. The imaging system of claim 16, wherein the pixel cells are adapted to be illuminated from a backside of the semiconductor material.

29. The imaging system of claim 28, further comprising an anti-reflective coating disposed on the backside of the semiconductor material.

30. The imaging system of claim 16, wherein the dielectric layer lining the inside surface of the DTI structure comprises silicon dioxide.

31. The imaging system of claim 16, wherein the doped semiconductor material disposed over the dielectric layer inside the DTI structure comprises lightly doped polysilicon.