HK1195165B - Stacked chip image sensor with light-sensitive circuit elements on the bottom chip - Google Patents

Abstract

The subject application relates to a stacked chip image sensor with light-sensitive circuit elements on the bottom chip. An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage.

Description

Stacked-chip image sensor with photosensitive circuit elements on bottom chip

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims U.S. provisional application No. 61/714,665, filed on day 16, 10/2012.

Technical Field

The present application relates to image sensors, and more particularly, to CMOS image sensors in stacked chip formation. The top chip contains a CMOS imaging array. The bottom chip contains light sensitive circuit elements that need to be shielded from light.

Background

Image sensors have become ubiquitous. It is widely used in digital cameras, cellular phones, surveillance cameras, and medical, automotive, and other applications. The technology used to fabricate image sensors, and more particularly, complementary metal oxide semiconductor ("CMOS") image sensors, continues to advance in large steps. For example, the demand for higher resolution and lower power consumption motivates further miniaturization and integration of these image sensors.

Some conventional image sensors incorporate in-pixel memory. For example, U.S. patent No. 8,445,828, which is incorporated herein by reference, describes a high dynamic range CMOS image sensor incorporating in-pixel memory over varying integration periods. That is, the integration period is determined from the previous integration period in part by the signal stored in the in-pixel memory. Each pixel includes a memory latch circuit that stores integration period information about the pixel. Each of these memory elements may be individually accessed. However, some of the circuit elements incorporated in the in-pixel memory may be sensitive to light-induced leakage.

Disclosure of Invention

The application discloses an imaging sensor system. The system may include: a first semiconductor layer of a first wafer; a Complementary Metal Oxide Semiconductor (CMOS) imaging array formed in the first semiconductor layer, wherein the CMOS imaging array includes N number of pixels, each pixel including a photodiode region formed in a front side of the first semiconductor layer, and wherein the photodiode region is configured to receive light from a backside of the first semiconductor layer; a first metal stack disposed on the front side of the first semiconductor layer; a second semiconductor layer of a second wafer; a second metal stack disposed on the second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first metal stack and the second metal stack; and a storage device formed in the second semiconductor layer and electrically coupled to the CMOS imaging array by way of the first metal stack and the second metal stack, wherein the storage device includes at least N number of storage cells, wherein each of the N number of storage cells is configured to store a signal representative of image charge accumulated by a respective photodiode and wherein each of the N number of storage cells includes a photosensitive circuit element.

The application also discloses an integrated circuit system. The system may include: a first chip having a plurality of first dies, each first die comprising:

a Complementary Metal Oxide Semiconductor (CMOS) imaging array formed in the first semiconductor layer, wherein the CMOS imaging array includes N number of pixels, each pixel including a photodiode region formed in a front side of the first semiconductor layer, and wherein the photodiode region is configured to receive light from a backside of the first semiconductor layer;

a first metal stack disposed on the front side of the first semiconductor layer; and

a second wafer having a plurality of second dies, each second die comprising:

a second metal stack disposed on a second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first metal stack and the second metal stack; and

a storage device formed in the second semiconductor layer and electrically coupled to the CMOS imaging array by way of the first metal stack and the second metal stack, wherein the storage device includes at least N number of storage cells, wherein each of the N number of storage cells is configured to store a signal representative of image charge accumulated by a respective photodiode region and wherein each of the N number of storage cells includes a photosensitive circuit element.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Fig. 1 is an exploded view of a stacked semiconductor wafer with an integrated circuit die according to an embodiment of the invention.

Fig. 2 is a cross-sectional view of an integrated circuit system having stacked device wafers, according to an embodiment of the invention.

FIG. 3 is a circuit diagram of a random access memory network according to an embodiment of the present invention.

Fig. 4 is a circuit diagram illustrating an embodiment of a pixel circuit 400 for two four-transistor ("4T") pixels within a BSI imaging array, according to an embodiment of the invention.

FIG. 5 is a circuit diagram illustrating a pixel circuit for one pixel within a backside illuminated imaging array including a storage capacitor according to an embodiment of the invention.

Fig. 6 is a hybrid cross-section/circuit illustration of a backside illuminated imaging sensor system incorporating the pixel circuit of fig. 5.

FIG. 7 is a circuit diagram illustrating a pixel circuit of a pixel within a backside illuminated imaging array including a storage capacitor according to an embodiment of the invention.

Fig. 8 is a hybrid cross-section/circuit illustration of a backside illuminated imaging sensor system incorporating the pixel circuit of fig. 7.

FIG. 9 is a circuit diagram illustrating pixel circuitry for a pixel within a backside illuminated imaging array including a storage diode, according to an embodiment of the invention.

Fig. 10 is a hybrid cross-section/circuit illustration of a backside illuminated imaging sensor system incorporating the pixel circuit of fig. 9.

Fig. 11 is a circuit diagram illustrating pixel circuitry for pixels within a BSI imaging array and a global random access storage network coupled to a floating diffusion region, in accordance with an embodiment of the invention.

Fig. 12 is a circuit diagram illustrating a pixel circuit for a pixel within a BSI imaging array and a global random access memory network coupled to a column readout line in accordance with an embodiment of the invention.

Fig. 13 is a functional block diagram illustrating an embodiment of a CMOS image sensor according to an embodiment of the present invention.

Detailed Description

Embodiments of a stacked-chip image sensor having photosensitive circuit elements on the bottom chip are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Directional terminology, such as "top," "down," "above," "below," etc., is used with reference to the orientation of the figures being described.

Fig. 1 is an exploded view of stacked device wafers 100 and 100' to be bonded together to form an integrated circuit system 102, according to an embodiment of the invention. The device wafers 100 and 100' may comprise silicon, or gallium arsenide or other semiconductor materials. In the illustrated example, the device wafer 100 includes semiconductor dies 111-119, while the device wafer 100' includes corresponding semiconductor dies (visible in phantom in fig. 1). As will be discussed in more detail below, in some embodiments, each die 111-119 of device wafer 100 may include a backside illuminated CMOS imaging array, while each corresponding die of device wafer 100' includes a storage device for storing an image charge signal accumulated by each photodiode of the CMOS imaging array. The storage device may include light sensitive (e.g., sensitive to light induced leakage) circuit elements. Thus, positioning the memory device on the base device wafer 100' may naturally provide effective light shielding for these light sensitive circuit elements without the need to fabricate a dedicated light shield.

Figure 2 is a cross-sectional view of an integrated circuit system 300 having stacked device wafers 304 and 306, according to an embodiment of the invention. Integrated circuit system 300 is one possible implementation of a portion of integrated circuit system 102 of fig. 1. The illustrated example of integrated circuit system 300 includes a first device wafer 304, a second device wafer 306, and a bonding interface 308. The first device wafer 304 includes a first semiconductor layer 310 and a first metal stack 312, while the second device wafer 306 is shown to include a second semiconductor layer 314 and a second metal stack 316. Semiconductor layer 310 is shown to include semiconductor devices 322 and 320, and metal stack 312 is shown to include metal layers M1, M2, and M3, and dielectric layer 326D. Semiconductor layer 314 is shown to include semiconductor device 318, and metal stack 316 is shown to include metal layers M1, M2, and M3, and dielectric layer 328D.

In one embodiment, either or both of semiconductor layer 310 and semiconductor layer 314 are epitaxially grown silicon layers. As shown, semiconductor layer 314 includes semiconductor device 318 formed in the front side of semiconductor layer 314, while semiconductor layer 310 includes devices 322 and 320 formed in the front side of semiconductor layer 310. In one embodiment, as will be discussed in more detail below, the semiconductor device 322 includes a CMOS imaging array, and the device 320 includes associated peripheral circuitry, such as readout circuitry, control circuitry, or other functional circuitry included in a CMOS image sensor. Continuing with this example, components such as a photosensitive region (e.g., a photodiode region) are included in a CMOS imaging array of the device 322. A photosensitive region (e.g., a photodiode region) of a CMOS image sensor can be formed in the front side and configured to receive light from the back side of semiconductor layer 310. The device 318 may include a storage device, such as a random access memory or the like discussed below with reference to FIG. 3. Thus, the device wafers 304 and 306 can be bonded together to form an integrated circuit system, such as an imaging sensor system that includes devices on the first device wafer 304 and devices on the second device wafer 306, and so forth. As will be shown below, devices 318, 320, and 322 may be formed in their respective semiconductor layers prior to bonding the device wafers 304 and 306 together. In one embodiment, one or both of the front side 307 and the front side 309 are planarized with chemical mechanical polishing. In one embodiment, dielectric layers 326D and 328D each comprise an oxide and are bonded together to form bonding interface 308.

Each CMOS image sensor pixel of the embodiments disclosed herein is formed using stacked chips. The top chip contains a photodetector that receives light to produce an electrical signal. The bottom chip contains the light sensitive circuit elements that need to be shielded from light. The stacked chips may be physically and electrically bonded together by means such as hybrid bonding (e.g., bonding interface 308).

In contrast, some conventional image sensors are formed using a single chip. When a conventional image sensor is formed using a single chip, the photosensitive circuit element must be shielded from light by a light shield. Insufficient shielding will cause undesirable leakage from these circuit elements. Embodiments disclosed herein formed using stacked chips allow for positioning of photosensitive circuit elements on a bottom chip without the need for dedicated light shields. For example, in the embodiment of fig. 2, the photosensitive circuit elements of device 318 are disposed in semiconductor layer 314, with no dedicated light shield disposed between the backside of semiconductor layer 310 and device 318. Such placement provides effective natural light shielding for these circuit elements.

In one embodiment, the top chip (e.g., wafer 304) and the bottom chip (e.g., wafer 306) are physically and electrically bonded together with a hybrid bond, which is a term in the art. For example, hybrid bonding bonds copper to copper and bonds oxide to oxide.

In one embodiment of the integrated circuit system, the bottom chip includes a random access memory network. A conventional CMOS image sensor uses a readout circuit that reads out pixel signals row by row. In the present invention, the electrical signal generated by each pixel's photodetector is stored in a storage device (i.e., memory cell) associated with the pixel. The storage device is configured in a network to permit random access. Since light can cause leakage to the memory device, the memory device is positioned on the bottom chip such that it is shielded from light.

FIG. 3 shows a random access memory network positioned on a bottom chip in some embodiments. Each memory transistor is connected to its associated photodetector positioned on the top chip. X lines, such as X1 and X2, are word lines and are connected to the gates of each memory. The Y lines, such as Y1 and Y2, are bit lines and are used for reading from each memory. Each memory is associated with a single ordered pair, such as (X1, Y1). The random access memory network allows signals from each CMOS image sensor pixel to be read out individually. This situation is more advantageous than the conventional line-by-line readout, since it provides more flexibility and versatility to the image signal processing.

In addition to storing the image signal from each pixel, random access memory networks may also be designed for other purposes. For example, they may be designed to control the integration period of each individual pixel (as disclosed in U.S. patent application publication 2012/0001060), with the difference being: in an embodiment of the invention, the memory elements (e.g., memory latch circuits including M1, M2, and node MEM) are positioned on the bottom chip.

Another embodiment relates to a global shutter CMOS image sensor. Conventional CMOS image sensors operate with an electronic rolling shutter. In the rolling shutter mode of operation, integration of the pixel array occurs row by row from top to bottom. When the integration of each row is finished, the electrical signals of the row are read out, and therefore, the readout of the pixel array also occurs row by row from top to bottom. Rolling shutters tend to be motion related artifacts. In contrast, in a global shutter, the integration of all rows of the entire pixel array begins and ends simultaneously. The electrical signals are stored and then read out row by row. The global shutter does not have motion-related artifacts.

In a global shutter CMOS image sensor, an electrical signal is stored in a storage device. U.S. patent 7,361,877, which is incorporated herein by reference, discloses the use of pinned diodes (e.g., storage region 170) to store photo-charges generated by photodiodes. U.S. patent 8,089,036, which is incorporated herein by reference, discloses the use of a transistor (e.g., storage transistor 340) to store photocharge. U.S. patent application 2009/0201400, again incorporated herein by reference, discloses the use of a capacitor (e.g., storage capacitor C1) to store photo-charges. In some embodiments, discussed further below, photo-charges (i.e., image charges accumulated by the photodiode region) may be stored in any type of storage device, such as pinned diodes, transistors, capacitors, and the like. When capacitors are used in the following embodiments, the capacitors are accessed using transistors as switches. Light can cause diode and transistor leakage, thereby degrading performance. Thus, these photosensitive memory device elements, such as transistors acting as switches, are positioned on the bottom chip so that they are naturally shielded from light.

Fig. 4 is a circuit diagram illustrating an embodiment of a pixel circuit 400 for two four-transistor ("4T") pixels within a BSI imaging array, according to an embodiment of the invention. Pixel circuit 400 is one possible pixel circuit architecture for implementing each pixel within a pixel array (e.g., pixel array 1305 of fig. 13), although it should be understood that embodiments of the invention are not limited to 4T pixel architectures; rather, those skilled in the art, having the benefit of this disclosure generally, will appreciate that the present teachings are also applicable to 3T designs, 5T designs, and various other pixel architectures. In fig. 4, BSI pixels Pa and Pb are arranged in two rows and one column. The illustrated embodiment of each pixel circuit 400 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, and a select transistor T4. During operation, transfer transistor T1 receives a transfer signal TX, which transfers charge accumulated in photodiode PD to floating diffusion node FD. In one embodiment, floating diffusion node FD may be coupled to a storage device, such as the previously mentioned random access memory on the bottom chip, for temporarily storing image charge. Reset transistor T2 is coupled between power rail VDD and floating diffusion node FD to reset (e.g., discharge or charge FD to a preset voltage) under control of reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between power rail VDD and select transistor T4. SF transistor T3 operates as a source follower providing a high impedance output from the pixel. Finally, select transistor T4 selectively couples the output of pixel circuit 400 to the readout column line under control of a select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are generated by a control circuit.

FIG. 5 is a circuit diagram illustrating a pixel circuit 500 for one pixel within a backside illuminated imaging array, according to an embodiment of the invention. Pixel circuit 500 is one possible pixel circuit architecture for implementing each pixel within a pixel array. In fig. 5, the pixel circuit 500 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, a select transistor T4, a control transistor T5, and a storage capacitor C. During operation, the transfer transistor T1 receives a transfer signal TX, which transfers the charge signal U accumulated in the photodiode PD to the storage capacitor C. While the floating diffusion node FD has an intrinsic capacitance, it is not generally a sufficient replacement for the storage capacitor C. For example, the size of the floating diffusion FD necessary to achieve sufficient capacitance will result in unacceptable leakage currents and other non-linear characteristics.

A control transistor T5 is coupled to the storage capacitor to control the transfer of the stored signal U from the storage capacitor to the floating diffusion node FD in response to a control signal CNTRL. Reset transistor T2 is coupled between power rail VDD and floating diffusion node FD to reset (e.g., discharge or charge FD to a preset voltage) under control of reset signal RST. Floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between power rail VDD and select transistor T4. SF transistor T3 operates as a source follower providing a high impedance output from floating diffusion FD. Finally, select transistor T4 selectively couples the output of pixel circuitry 500 to the readout column line under control of a select signal SEL.

In one embodiment, the TX signal, the RST signal, the CNTRL signal, and the SEL signal are generated by a control circuit. In an embodiment, where the pixel array is operated by a global shutter, a global shutter signal is coupled to the gate of each transfer transistor in the entire pixel array to simultaneously initiate the charge transfer between the photodiode PD and the storage capacitor C of each pixel. In one embodiment, the global shutter signal is generated by a global shutter circuit included within the control circuitry of the image sensor.

Fig. 6 is a hybrid cross-section/circuit illustration of a backside illuminated imaging sensor system 600 having a storage device 318 according to an embodiment of the present invention. The illustrated embodiment of the imaging sensor system 600 is similar to the integrated circuit system 300 and illustrates further details of embodiments of the memory device 318 having memory cells that each include a storage capacitor Cn and a control transistor CNTRL. In one embodiment, imaging array 322 includes n number of pixels, where each pixel includes a photodiode region formed on the front side of semiconductor layer 310. Thus, the illustrated embodiment of the storage device 318 includes at least n number of storage cells (i.e., storage capacitors and control transistors). Thus, storage 318 includes at least one memory cell corresponding to each of the pixels included in imaging array 322.

As illustrated, imaging sensor system 600 is sensitive to light incident on the backside of semiconductor layer 310. By using backside illumination sensors, the memory cells included in the memory device 318 can be positioned below the imaging array 322 without blocking light from reaching the imaging array 322. By placing the storage capacitor C on the device wafer 306, the imaging array 322 and the memory cells do not compete for valuable die area. More specifically, the storage capacitor C may be amplified to increase its capacitance without detracting from the duty cycle of the image sensor. Embodiments of the present invention enable the placement of bulk storage capacitors C close to their respective photodiode regions without reducing the sensitivity of the pixel. Furthermore, the backside illumination configuration provides greater flexibility to route signals on the front side of semiconductor layer 310 within metal stacks 312 and 316 without interfering with light received by imaging array 322. In one embodiment, the global shutter signal is routed within the metal stack 312 to all pixels within the imaging array 322. In one example, memory device 318 is electrically coupled to imaging array 322 and/or peripheral circuitry 320 by way of both metal stacks 312 and 316.

Another advantage of placing the memory device 318 on the bottom device wafer 306 is increased isolation from incident photons. Photons reaching the storage capacitor C and/or the control transistor CNTRL may result in increased leakage currents. However, most of the photons incident on the backside of the device wafer 304 terminate within the imaging array 322. Those photons that penetrate through the imaging array 322 are further blocked by the metal stacks 312 and 316.

FIG. 7 is a circuit diagram illustrating a pixel circuit 700 of a seven or eight transistor pixel with a global shutter, according to an embodiment of the invention. Pixel circuit 700 is one possible pixel circuit architecture for implementing each pixel within an imaging array.

The illustrated embodiment of imaging pixel 700 includes select 1 transistor 710, select 2 transistor 715, photodiode 720, transfer transistor 730, storage transistor 740, output transistor 750, reset transistor 760, amplification transistor 780, and row select transistor 790 (also referred to as a readout transistor). In one embodiment, the transistors are similarly sized, except for transfer transistor 730, which reduces space (required for large shutter transistors of conventional technology) and increases the duty cycle.

In one embodiment, the photodiode 720 may be fully reset by selectively activating the select 2 transistor 715 when the reset transistor 760 and the transfer transistor 730 are activated. The select 2 transistor 715 is optional and may be used when a negative gate voltage is applied to the storage transistor 740.

In operation, a controller, such as a control circuit, may be used to control the pixel circuit 700 as follows. Reset transistor 760 is coupled to a voltage source, such as Vdd. Reset transistor 760 is enabled, which precharges node FD. Select 2 transistor 715 and transfer transistor 730 are activated, which precharges photodiode 720. Deactivating the select 2 transistor 715 and the transfer transistor 730 allows the photodiode 720 to be integrated by accumulating photovoltaically generated electrons during the image acquisition window. A negative voltage (e.g., -1.2 volts) may be applied to the gate of the memory transistor 740 prior to integration to accumulate holes in the region under the gate. After integration, transfer transistor 730 receives the transfer signal and activates select 1 transistor 710 and storage transistor 740, which transfers the charge accumulated in photodiode 720 to storage transistor 740, the charge being held in storage transistor 740 until it is ready to be read out. In one embodiment, for example, the gate of storage transistor 740 may be activated using a voltage of approximately 2.8 volts to 3.2 volts.

When the reset transistor 760 is deactivated, the charge present at the FD node gradually decreases due to leakage (e.g., due to dark current). The FD node is coupled to control the gate of an amplification transistor 780. An amplification transistor 780 is coupled between the power rail Vdd and the row select transistor 790. The amplifying transistor 780 operates as a source follower. The "dark" voltage at the FD node may be measured by activating the row select transistor 790 under control of a select signal SEL to selectively couple the output of the pixel circuit 700 to a readout column bit line. The "signal" charge (currently stored at storage transistor 740) may be read by activating output transistor 750, which output transistor 750 couples the charge to the FD node, which in turn biases the gate of amplification transistor 780 to generate a voltage that is coupled to the column bit line via row select transistor 790. In one embodiment, the row select transistor 790 may be omitted such that the drain of the amplifying transistor 780 may be directly coupled to the column bit line. In this embodiment, the amplifying transistor 780 may be referred to as a "readout transistor". When present, the row select transistor 790 is referred to as a "read transistor". In one embodiment, both the amplification transistor 780 and the row select transistor 790 may be removed from the imaging pixel 700, in which case the output transistor 750 operates as a "readout transistor".

In one embodiment, the transfer signal, the reset signal, and the select signal are generated by a control circuit. In embodiments where the imaging array operates with a global shutter, a global shutter signal (e.g., a Tx signal) is coupled to the gate of each transfer transistor 730 in the entire pixel array to simultaneously begin the transfer of charge from the photodiode 720 of each pixel. In one embodiment, the global shutter signal is generated by a global shutter circuit included within the control circuit. Thus, the transfer transistor 730 and the Tx signal serve the dual purpose of providing an image shutter or shutter signal and a charge transistor or transfer signal for reading out image charge from the photodiode 720. In addition, the photodiode 720 is reset via the transfer transistor 730 and the select 2 transistor 715 (when present).

FIG. 8 is a hybrid cross-section/circuit illustration of a backside illuminated imaging sensor system 800 with a storage device 318 according to an embodiment of the invention. The illustrated embodiment of the imaging sensor system 800 is similar to the integrated circuit system 300 and illustrates further details of embodiments of the storage device 318 having storage cells that each include a storage transistor St, as discussed above in FIG. 7. In one embodiment, imaging array 322 includes n number of pixels, where each pixel includes a photodiode region formed on the front side of semiconductor layer 310. Thus, the illustrated embodiment of the storage device 318 includes at least n number of memory cells (i.e., storage transistors St). Thus, storage 318 includes at least one memory cell corresponding to each of the pixels included in imaging array 322.

As illustrated, imaging sensor system 600 is sensitive to light incident on the backside of semiconductor layer 310. By using backside illumination sensors, the memory cells included in the memory device 318 can be positioned below the imaging array 322 without blocking light from reaching the imaging array 322. By placing the memory transistor St on the device wafer 306, the imaging array 322 and the memory cell do not compete for valuable die area. More specifically, the gate of the memory transistor St may be amplified to increase its capacitance without detracting from the duty cycle of the image sensor. In one example, memory device 318 is electrically coupled to imaging array 322 and/or peripheral circuitry 320 by way of both metal stacks 312 and 316.

Another advantage of placing the memory device 318 on the bottom device wafer 306 is increased isolation from incident photons. Photons reaching the memory transistor St may result in an increased leakage current. However, most of the photons incident on the backside of the device wafer 304 terminate within the imaging array 322. Those photons that penetrate through the imaging array 322 are further blocked by the metal stacks 312 and 316.

FIG. 9 is a circuit diagram illustrating a pixel circuit 900 for a pixel with a global shutter according to an embodiment of the invention. Pixel circuit 900 is one possible pixel circuit architecture for implementing each pixel within an imaging array.

As illustrated, the pixel circuit includes a photodiode PD. In one embodiment, the photodiode PD is a pinned photodiode having one doped layer and another doped pinned layer for collecting charge generated from incident light. The shutter gate Gsh transfers the accumulated charge to a second pinned diode or storage diode Sd for storage of the transferred charge. The transfer gate TX transfers charge to a sensing node, preferably a floating diffusion FD, which is adjacent to the storage diode Sd. The sense node (e.g., FD) converts the charge to a voltage, which is then sensed by an amplifier, preferably a source follower SF. The reset transistor RST resets the floating diffusion FD to a reference voltage. An overflow drain (not shown) is adjacent the photodiode PD for draining excess charge from the photodiode PD.

Operation of the pixel circuit 900 involves the combined use of the shutter gate Gsh, the transfer gate TX, and the reset gate RST to drain the photodiode PD. The reset gate RST is also used to reset the floating diffusion FD to a set bias greater than that of the photodiode PD and, in conjunction with the shutter gate Gsh, drains all charge from the storage diode Sd. The shutter gate Gsh is turned on and then the transfer gate TX is turned off for all pixels to start the shutter window at the same time. The signal from the incident light generates a charge on the photodiode PD integrated on the storage diode Sd. To end the shutter window, the shutter gate Gsh is opened and the signal charge is held on the storage diode Sd. The floating diffusion FD is then reset to the reference voltage by clocking the reset transistor RST on and off and then reading out the output. The transfer gate TX is then turned on so that the signal charge is transferred to the floating diffusion FD and the output is read out. The image signal is the difference between the two readouts.

Fig. 10 is a hybrid cross-section/circuit illustration of a backside illuminated imaging sensor system 1000 with a storage device 318 according to an embodiment of the present invention. The illustrated embodiment of the imaging sensor system 1000 is similar to the integrated circuit system 300 and illustrates further details of embodiments of the storage device 318 having storage cells that each include a storage diode Sd, as discussed above in fig. 9. In one embodiment, imaging array 322 includes n number of pixels, where each pixel includes a photodiode region formed on the front side of semiconductor layer 310. Thus, the illustrated embodiment of storage device 318 includes at least n number of storage cells (i.e., storage diodes Sd). Thus, storage 318 includes at least one memory cell corresponding to each of the pixels included in imaging array 322.

As illustrated, imaging sensor system 600 is sensitive to light incident on the backside of semiconductor layer 310. By using backside illumination sensors, the memory cells included in the memory device 318 can be positioned below the imaging array 322 without blocking light from reaching the imaging array 322. By placing the memory diodes Sd on the device wafer 306, the imaging array 322 and the memory cells do not compete for valuable die area. More specifically, the storage diode Sd may be amplified to increase its storage capacity without detracting from the duty cycle of the image sensor. In one example, memory device 318 is electrically coupled to imaging array 322 and/or peripheral circuitry 320 by way of both metal stacks 312 and 316.

Another advantage of placing the memory device 318 on the bottom device wafer 306 is increased isolation from incident photons. Photons reaching the memory diode Sd may result in an increased leakage current. However, most of the photons incident on the backside of the device wafer 304 terminate within the imaging array 322. Those photons that penetrate through the imaging array 322 are further blocked by the metal stacks 312 and 316.

Fig. 11 is a circuit diagram illustrating an embodiment of a pixel circuit 1100 and a global random access memory network 1104 for a pixel within a BSI imaging array in accordance with an embodiment of the invention. Pixel circuit 1100 is one possible pixel circuit architecture for implementing each pixel within an imaging array (e.g., pixel array 1305 of fig. 13), although it should be understood that embodiments of the invention are not limited to 4T pixel architectures; rather, those skilled in the art, having the benefit of this disclosure generally, will appreciate that the present teachings are also applicable to 3T designs, 5T designs, and various other pixel architectures.

In fig. 11, each pixel circuit 1100 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, and a select transistor T4. The pixel circuit 1100 is coupled and operates similar to the pixel circuit 400 of fig. 4. However, as shown in fig. 11, in this embodiment, each floating diffusion FD is coupled to a global random access storage network 1104, the global random access storage network 1104 receiving and storing image charge read out from each photodiode region PD of the imaging array.

The random access storage network 1104 is one possible implementation of the storage device 318 of FIG. 2, and is positioned within the bottom device wafer 308 such that the photosensitive elements of the random access storage network are substantially shielded from light incident on the backside of the top device wafer 304.

In one embodiment, random access memory network 1104 comprises the random access memory network of FIG. 3. Thus, in this embodiment, each of the Y lines (e.g., Y1, Y2, … …, Yn) is coupled to a floating diffusion region of a corresponding pixel included in the imaging array. Similarly, each of the X lines (e.g., X1, X2, etc.) is coupled to memory controller/readout circuitry 1106. Memory controller/sense circuitry 1106 is coupled to generate signals to control both write and read operations of the random access memory network 1104. The random access storage network 1104 allows signals from each photodiode region to be stored simultaneously, while also allowing each stored signal to be read out individually and in any order.

Fig. 12 is a circuit diagram illustrating an embodiment of a pixel circuit 1100 for a pixel within a BSI imaging array and a global random access memory network 1104 coupled to a column readout line in accordance with an embodiment of the invention. The pixel circuit 1100 is coupled and operates similar to the pixel circuit described with reference to fig. 11. However, as shown in fig. 12, in this embodiment, rather than being coupled to each floating diffusion FD, a global random access storage network 1104 is coupled to each column readout line of the imaging array to receive and store image charges read out from each floating diffusion FD of the imaging array.

In one embodiment, random access memory network 1104 comprises the random access memory network of FIG. 3. Thus, in this embodiment, each of the Y lines (e.g., Y1, Y2, … …, Yn) is coupled to a column readout line (i.e., bit line) for a column of pixels included in the imaging array. Similarly, each of the X lines (e.g., X1, X2, etc.) is coupled to memory controller/readout circuitry 1106. Random access storage network 1104 allows signals from each floating diffusion to be stored simultaneously, while also allowing each stored signal to be read out individually in any order.

Fig. 13 is a functional block diagram illustrating an embodiment of a CMOS image sensor 1300 according to an embodiment of the invention. CMOS image sensor 1300 may be one implementation of at least one of the semiconductor devices mentioned previously, including device 300. The illustrated embodiment of image sensor 1300 includes an imaging array 1305, readout circuitry 1310, functional logic 1315, and control circuitry 1320.

The imaging array 1305 is a two-dimensional ("2D") array of backside illuminated imaging sensors or pixels (e.g., pixels P1, P2, … …, Pn). In one embodiment, each pixel is an active pixel sensor ("APS"), such as a complementary metal oxide semiconductor ("CMOS") imaging pixel or the like. As illustrated, each pixel is configured into rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, place, or object, which may then be used to render a 2D image of the person, place, or object.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 1310 and transferred to functional logic 1315. The readout circuitry 1310 may include amplification circuitry, analog-to-digital ("ADC") conversion circuitry, or other circuitry. Function logic 1315 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red-eye, adjusting a metric, adjusting contrast, or other methods). The control circuitry 1320 is coupled to the pixel array 1305 to control the operating characteristics of the pixel array 1305.

The above description of illustrated embodiments of the invention, including what is described in the "Abstract of the disclosure", is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (18)

1. An imaging sensor system, comprising:

a first semiconductor layer of a first wafer;

a Complementary Metal Oxide Semiconductor (CMOS) imaging array formed in the first semiconductor layer, wherein the CMOS imaging array includes a number N of pixels, each pixel including a photodiode region formed in a front side of the first semiconductor layer, and wherein the photodiode region is configured to receive light from a backside of the first semiconductor layer;

a first metal stack disposed on the front side of the first semiconductor layer;

a second semiconductor layer of a second wafer;

a second metal stack disposed on the second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first metal stack and the second metal stack; and

a storage device formed in the second semiconductor layer and electrically coupled to the CMOS imaging array by way of the first and the second metal stacks, wherein the storage device includes at least N number of memory cells, wherein each of the N number of memory cells is configured to store a signal representative of image charge accumulated by a respective photodiode region, and wherein each of the N number of memory cells includes a photosensitive circuit element, and wherein the photosensitive circuit element is disposed in the second semiconductor layer without an optical shield between the backside of the first semiconductor layer and the photosensitive circuit element.

2. The imaging sensor system of claim 1, wherein each pixel of the CMOS imaging array further comprises a floating diffusion region formed in the first semiconductor layer, wherein the floating diffusion region is selectively coupled to a respective photodiode for converting the accumulated image charge to a voltage signal.

3. The imaging sensor system of claim 2, wherein each photosensitive circuit element comprises a storage transistor to store the signal representative of the image charge.

4. The imaging sensor system of claim 2, wherein each photosensitive circuit element comprises a pinned photodiode to store the signal representative of the image charge.

5. The imaging sensor system of claim 2, wherein each of the N number of storage units includes a storage capacitor to store the signal representative of the image charge, and wherein each photosensitive circuit element comprises a control transistor coupled to a respective storage capacitor to control outward transfer of the stored signal from the storage capacitor.

6. The imaging sensor system of claim 2, wherein the storage device is a random access storage network of storage cells configured to allow simultaneous storage of signals representative of image charge accumulated by each photodiode region and random access of each stored signal.

7. The imaging sensor system of claim 6, wherein the random access storage network is coupled to each floating diffusion region of the CMOS imaging array such that each storage cell of the random access storage network is coupled to receive and store the image charge read out from a respective photodiode region.

8. The imaging sensor system of claim 6, wherein the N number of pixels are configured in columns and rows,

the CMOS imaging array further comprises a plurality of column readout lines for reading out signals representing image charges accumulated by photodiode regions of the same column, wherein the random access storage network is coupled to each of the plurality of column readout lines to receive and store the signals.

9. The imaging sensor system of claim 1, wherein:

the first metal stack comprises at least one first metal layer and at least one first dielectric layer,

the second metal stack comprises at least one second metal layer and at least one second dielectric layer, and

the bonding interface comprises an interface between the first dielectric layer and the second dielectric layer.

10. An integrated circuit system, comprising:

a first chip having a plurality of first dies, each first die comprising:

a CMOS imaging array formed in a first semiconductor layer, wherein the CMOS imaging array includes N number of pixels, each pixel including a photodiode region formed in a front side of the first semiconductor layer, and wherein the photodiode region is configured to receive light from a backside of the first semiconductor layer;

a first metal stack disposed on the front side of the first semiconductor layer; and

a second wafer having a plurality of second dies, each second die comprising:

a second metal stack disposed on a second semiconductor layer, wherein the first wafer is bonded to the second wafer at a bonding interface between the first metal stack and the second metal stack; and

a storage device formed in the second semiconductor layer and electrically coupled to the CMOS imaging array by way of the first and the second metal stacks, wherein the storage device includes at least N number of memory cells, wherein each of the N number of memory cells is configured to store a signal representative of image charge accumulated by a respective photodiode region, and wherein each of the N number of memory cells includes a photosensitive circuit element, and wherein the photosensitive circuit element is disposed in the second semiconductor layer without an optical shield between the backside of the first semiconductor layer and the photosensitive circuit element.

11. The integrated circuit system of claim 10, wherein each pixel of the CMOS imaging array further comprises a floating diffusion region formed in the first semiconductor layer, wherein the floating diffusion region is selectively coupled to a respective photodiode for converting the accumulated image charge to a voltage signal.

12. The integrated circuit system of claim 11, wherein each photosensitive circuit element comprises a storage transistor to store the signal representative of the image charge.

13. The integrated circuit system of claim 11, wherein each photosensitive circuit element comprises a pinned photodiode to store the signal representative of the image charge.

14. The integrated circuit system according to claim 11, wherein each of the N number of storage cells includes a storage capacitor to store the signal representative of the image charge, and wherein each photosensitive circuit element comprises a control transistor coupled to a respective storage capacitor to control outward transfer of the stored signal from the storage capacitor.

15. The integrated circuit system according to claim 11, wherein the storage device is a random access storage network of storage cells configured to allow simultaneous storage of signals representative of image charge accumulated by each photodiode region and to allow random access to each stored signal.

16. The integrated circuit system of claim 15, wherein the random access storage network is coupled to each floating diffusion region of the CMOS imaging array such that each storage cell of the random access storage network is coupled to receive and store the image charge read out from a respective photodiode region.

17. The integrated circuit system of claim 15, wherein the N number of pixels are configured in columns and rows, the CMOS imaging array further comprising a plurality of column readout lines for reading out signals representing image charge accumulated by photodiode regions of a same column, wherein the random access storage network is coupled to each of the plurality of column readout lines to receive and store the signals.

18. The integrated circuit system of claim 10, wherein:

the first metal stack comprises at least one first metal layer and at least one first dielectric layer,

the second metal stack comprises at least one second metal layer and at least one second dielectric layer, and

the bonding interface comprises an interface between the first dielectric layer and the second dielectric layer.