HK1242048B - An electronic device and method of making thereof - Google Patents

Description

Electronic device and method for manufacturing the same

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Patent Application No. 14/879,884, filed on October 9, 2015. This application also claims priority to U.S. Patent Application No. 15/235,472, filed on August 12, 2016. Both applications are incorporated herein by reference in their entirety.

Technical Field

The present application relates to electronic devices and methods of manufacturing the same, and more particularly, to printable electronic devices and methods of manufacturing the same.

Background Art

Single-crystal silicon is used in most electronic applications. There are exceptions, such as displays and some imagers, where amorphous silicon is applied to a non-semiconductor substrate to operate the display or imager pixels. In many applications, displays or imagers are fabricated on top of silicon electronic devices. For liquid crystal display (LCD) applications, amorphous silicon has provided sufficient performance. However, for next-generation display devices, such as organic light-emitting diodes (OLEDs) and active-matrix (AM) driver transistors made of amorphous silicon, this has proven problematic. Fundamentally, LCDs use voltage devices, while AM-OLEDs require current devices. Attempts to extend traditional methods involve modifying existing amorphous silicon-on-glass technologies. Amorphous silicon is applied to an entire substrate panel, typically more than two meters on a side, and then recrystallized using a large excimer laser and scanning a line focus across the panel. The laser must be pulsed to melt only the Si surface without melting the glass. This technique results in the formation of polycrystalline silicon rather than single crystal silicon. For some detector applications, Si wafers are butted together to form larger, but more expensive, devices.

The mobility of any type of amorphous or polycrystalline transistor (including non-silicon and organic devices) is much less than that of single crystal silicon transistors. The electron mobility in amorphous silicon is ~1 ^cm2 /V·s, compared to the electron mobility in polycrystalline silicon of ~100 ^cm2 /V·s and the electron mobility in high quality single crystal silicon of ~1500 ^cm2 /V·s. Therefore, it is beneficial to use single crystal silicon instead of amorphous silicon in these devices. In a preferred embodiment of the present invention, for the purpose of manufacturing electronic devices, multiple flat single crystal silicon areas are manufactured at predetermined locations on a non-silicon substrate. For example, wafers of single crystal silicon are too expensive for large displays and are too small in size: silicon wafers are typically 300 mm in diameter, compared to current LCD panels on a side of more than 2 meters. In contrast, approximately spherical particles, spheres, and spherical-like particles of single crystal silicon have been made into large sizes less than or equal to 2 mm, which is large compared to the size of a single pixel. US Patent No. 4,637,855, filed April 30, 1985 by Witter et al., entitled "Process for Producing Crystalline Spherical Spheres," which is incorporated herein by reference, describes the manufacture of crystal spheres.

In the past, others have attempted to place diodes onto the curved surface of a silicon sphere, but this has proven challenging. Prior art attempts have been made to photolithographically define structures on spherical surfaces, but this requires non-standard optics and has had limited success. Making electrical contacts to non-planar surfaces also requires non-standard techniques. The complexity involved in manufacturing has prevented real progress.

The curved surface of the Si sphere is also doped with an n-type dopant to form an n-type Si region surrounding a p-type Si region that includes most of the surface of the sphere. One embodiment of the present invention relates to the field of optoelectronic devices because the flat surface and the region directly below can be doped with, for example, an n-type dopant, and the region below can be doped with a p-type dopant to form a solar cell. Silicon sphere solar cells are described in a paper titled "Crystalline Characterization of Spherical Silicon Solar Cells by X-ray Diffraction" by Satoshi OMAE, Takashi MINEMOTO, Mikio MUROZONO, Hideyuki TAKAKURA, and Yoshihiro HAMAKAWA in the Japanese Journal of Applied Physics, Vol. 45, No. 5A, 2006, pp. 3933-3937, #2006, in the Journal of the Japanese Society of Applied Physics.

However, this invention overcomes the limitations of the prior art mentioned above by conveniently utilizing the surface area and region of the planarized particles. Having a planar region with structures formed therein provides a convenient and reliable way to provide electronic contacts to different parts of a device. These electronic devices have traditionally been manufactured using photolithographic techniques. However, photolithography requires complex equipment and a controlled environment and can be very expensive.

Another very important aspect of the invention is that it can enable technology to have a smaller carbon footprint by allowing circuits to be built that consume less energy than similar circuits using LCD technology.

In displays using previous-generation LCD technology, white light is supplied to the back of the display panel, and each LCD pixel uses a filter to select red (R), green (G), or blue (B) light. In this way, two-thirds of the energy in the backlight is filtered. Furthermore, the operation of the LCD pixel depends on polarized light, so further losses are caused by the polarizer. In addition, part of each pixel is occupied by an amorphous silicon transistor, which prevents light from passing through the panel.

The present invention enables the production of large OLED panels that are more efficient than LCD panels. OLED pixels emit light only in the desired color, R, G, or B, so energy is not wasted producing other colors, which are then filtered out and wasted as heat. Furthermore, the OLED emitter can be fabricated on top of the backplane electronics, maximizing the emissive area without blocking the pixel's light-emitting area. By placing the backplane electronics outside the optical path, the design can be optimized for speed and low power consumption, as opposed to compromising on optical path requirements.

Summary of the Invention

According to one embodiment of the present invention, a method for forming an active matrix OLED display is provided, the method comprising: providing a backplane, comprising: providing a backplane substrate; providing semiconductor particles formed separately from the backplane substrate; positioning the semiconductor particles at predetermined locations on the backplane substrate; immovably fixing the semiconductor particles to the predetermined locations on the backplane substrate; after immovably fixing the semiconductor particles, removing a portion of each of the semiconductor particles so as to expose a cross-section of the semiconductor particles, wherein the cross-section is a flat surface; and providing one or more gate-controllable electronic components directly above or directly below each flat surface, the gate-controllable electronic components being configured to control pixels of the active matrix OLED display. The method further comprises: providing an OLED assembly comprising one or more pixel regions, the OLED assembly being electrically connected to the backplane such that at least one of the pixel regions is electrically connected to a corresponding one or more of the gate-controllable electronic components.

The largest dimension of the planar surface may be less than 15 mm and greater than 1 μm; and providing the backplane may further comprise providing at least two electronic contacts to each gateable electronic component supported by the planar surface.

According to another embodiment of the present invention, a method for forming an active matrix OLED display is provided, the method comprising: providing a backplane, the backplane comprising: a backplane substrate; semiconductor particles, the semiconductor particles being formed separately from the backplane substrate and then fixed to predetermined positions on the backplane substrate; the semiconductor particles being flattened to remove portions of the semiconductor particles and expose a flat surface at a cross-section of the semiconductor particles; and gateable electronic components located directly above or below the flat surface, the gateable electronic components being configured to control one or more pixels of the active matrix OLED display. The method further comprises: providing an OLED assembly comprising one or more pixel regions, the OLED assembly being electrically connected to the backplane such that at least one of the pixel regions of the OLED assembly is electrically connected to the gateable electronic component.

The OLED component may be formed separately from the backplane on an OLED substrate different from the backplane substrate, the OLED component including one or more pixel contacts corresponding to each pixel area; and providing the OLED component electrically connected to the backplane may include: combining the OLED component with the backplane, the combining including electrically connecting at least one of the pixel contacts corresponding to at least one of the pixel areas to a gate-controllable electronic component.

The method may further include, prior to bonding, aligning the OLED assembly and the backplane with each other so as to align at least one pixel contact corresponding to at least one of the pixel regions with the gateable electronic component.

The method may further include backfilling at least a portion of the gap between the bonded OLED assembly and the backplane with a substantially black underfill.

The electrical connection may include connecting at least one of the one or more pixel contacts to the gateable electronic component using one or more of a conductive epoxy, solder, and a low temperature solder.

The backplane may further include: a conformal coating covering the backplane substrate and at least a portion of the semiconductor particles; and wherein: the semiconductor particles can be flattened to further remove portions of the conformal coating; the maximum dimension of the flat surface may be less than 15 mm; at least a portion of the semiconductor particles directly below or above the flat surface may be doped with a first dopant of a first type, and wherein another portion of the semiconductor particles directly below or above the flat surface may be doped with a second dopant of a second type; one of the first dopant and the second dopant is n-type; and the gate-controllable electronic component includes: a first contact at or above the flat surface, the first contact contacting the first dopant; and a second contact at or above the flat surface, the second contact contacting the second dopant; and the electrical connection includes a conductive link between one of the first contact and the second contact and at least one pixel region.

According to another embodiment of the present invention, an active matrix OLED display is provided, comprising: a backplane, the backplane comprising: a backplane substrate; semiconductor particles, the semiconductor particles are formed separately from the backplane substrate and then fixed to predetermined positions on the backplane substrate; the semiconductor particles are flattened to remove portions of the semiconductor particles and expose a flat surface at a cross-section of the semiconductor particles; and a gate-controllable electronic component located directly above or below the flat surface; and an OLED assembly including one or more pixel areas, the OLED assembly being electrically connected to the backplane so that at least one pixel area of the OLED assembly is electrically connected to the gate-controllable electronic component, the electrical connection being configured to allow the gate-controllable electronic component to control at least one pixel area of the OLED assembly.

The active matrix OLED display may further include a substantially black underfill filling at least a portion of a gap between the bonded OLED assembly and the backplane.

An active matrix OLED display in which the backplane may further include: a conformal coating covering the backplane substrate and at least a portion of the semiconductor particles; and wherein: the semiconductor particles may be planarized to further remove portions of the conformal coating; the maximum dimension of the planar surface may be less than 15 mm; at least a portion of the semiconductor particles directly below or above the planar surface may be doped with a first dopant of a first type, and wherein another portion of the semiconductor particles directly below or above the planar surface may be doped with a second dopant of a second type; one of the first dopant and the second dopant is n-type; and the gate-controllable electronic component may include: a first contact at or above the planar surface, the first contact contacting the first dopant; and a second contact at or above the planar surface, the second contact contacting the second dopant; and the electrical connection may include a conductive link between one of the first contact and the second contact and at least one pixel region.

According to another embodiment of the present invention, an imager is provided, comprising: a detector assembly for detecting photons and, in response, generating an electrical signal; a backplate comprising: a backplate substrate; semiconductor particles formed separately from the backplate substrate and then fixed to predetermined positions on the backplate substrate; the semiconductor particles being flattened to remove portions of the semiconductor particles and expose a flat surface at a cross-section of the semiconductor particles; and a gateable electronic component located directly above or below the flat surface; and an electrical connection between the gateable electronic component and the detector assembly, the electrical connection being configured to allow the gateable electronic component to collect the electrical signal.

The detector assembly may be an X-ray detector.

The backplate of the imager may further include: a conformal coating covering the backplate substrate and at least a portion of the semiconductor particles; and wherein: the semiconductor particles can be planarized to further remove portions of the conformal coating; the maximum dimension of the planar surface can be less than 15 mm; at least a portion of the semiconductor particles directly below or above the planar surface can be doped with a first dopant of a first type, and wherein another portion of the semiconductor particles directly below or above the planar surface can be doped with a second dopant of a second type, one of the first dopant and the second dopant being n-type; and the gateable electronic component includes: a first contact at or above the planar surface, the first contact contacting the first dopant; and a second contact at or above the planar surface, the second contact contacting the second dopant; and the electrical connection may include a conductive link between one of the first contact and the second contact and at least one pixel area detector assembly.

According to another embodiment of the present invention, a method for manufacturing a backplane is provided, the method comprising: providing a backplane substrate comprising one or more predetermined positions, each predetermined position being configured to receive a semiconductor particle; providing semiconductor particles formed separately from the backplane substrate; placing the semiconductor particles on the backplane substrate; mechanically shaking the backplane substrate and the semiconductor particles so that one semiconductor particle occupies each position; fixing the semiconductor particles to each corresponding position of the backplane substrate; after fixing the semiconductor particles to each corresponding position, removing a portion of each of the semiconductor particles so as to expose a cross-section of the semiconductor particle, the cross-section being a flat surface.

The method may further include providing at least one gateable electronic component directly above or below each planar surface.

Mechanically shaking may include vibrating the backplate substrate.

Mechanically agitating may include one or more of: rotating the backplane substrate about one or more axes; and translating the backplane substrate in one or more directions.

Securing may include applying an adhesive to each location prior to placing the semiconductor particles on the backplane, the adhesive being configured to secure at least one semiconductor particle to each corresponding location of the backplane substrate.

Fixing may include heating the semiconductor particles and the backplane substrate to fuse the semiconductor particles to the backplane substrate.

Fixing may include: applying a conformal coating to the backplane substrate after mechanically shaking to at least partially cover the semiconductor particles and the backplane substrate; and removing further includes removing at least a portion of the conformal coating covering the semiconductor particles to expose the flat surface.

According to another embodiment of the present disclosure, a method for forming a plurality of electronic devices on a substrate is provided, the method comprising: providing semiconductor particles formed separately from the substrate; placing the semiconductor particles at predetermined locations on the substrate; immovably securing the semiconductor particles to the predetermined locations on the substrate; after immovably securing the semiconductor substrate, removing a portion of each of the semiconductor particles to expose a cross-section of the semiconductor particles, wherein the cross-section is a planar surface; and providing one or more gated electronic components directly above or below each planar surface. For each planar surface, providing the one or more gated electronic components comprises: depositing a first amount of a first liquid medium including a dopant on a first portion of the planar surface, and depositing a second amount of the first liquid medium on a second portion of the planar surface, the first amount of medium being separated from the second amount of medium by a gap; heating the first amount of medium, the second amount of medium, and the corresponding semiconductor particles, the heating being configured to cause at least some of the dopant to diffuse from the first liquid medium into the planar surface; depositing a dielectric material in the gap on the planar surface; selectively removing the first amount of medium and the second amount of medium from the planar surface; depositing an electronic contact on each of the first portion and the second portion; and depositing an additional electronic contact on the dielectric material.

According to another embodiment of the present disclosure, an electronic device is provided, comprising: a substrate; a semiconductor particle formed separately from the substrate and then affixed to the substrate; the semiconductor particle planarized to remove portions of the semiconductor particle and expose a planar surface at a cross-section of the semiconductor particle; and a gateable electronic component located directly above or below the planar surface. The gateable electronic component is formed by depositing a first amount of a first liquid medium including a dopant on a first portion of the planar surface and a second amount of the first liquid medium on a second portion of the planar surface, the first amount of medium being separated from the second amount of medium by a gap; heating the first amount of medium, the second amount of medium, and the semiconductor particle, the heating being configured to cause at least some of the dopant to diffuse from the first liquid medium into the planar surface; depositing a dielectric material in the gap on the planar surface; selectively removing the first amount of medium and the second amount of medium from the planar surface; depositing an electronic contact on each of the first portion and the second portion; and depositing additional electronic contacts on the dielectric material.

According to another embodiment of the present specification, a method for forming an electronic device on a substrate is provided, the method comprising: providing a semiconductor particle formed separately from the substrate; immovably fixing the semiconductor particle to the substrate; after immovably fixing, depositing a first quantity of a first liquid medium including a dopant on a first portion of a surface of the semiconductor particle, and depositing a second quantity of the first liquid medium on a second portion of the surface, the first quantity of the medium being separated from the second quantity of the medium by a gap; heating the first quantity of the medium, the second quantity of the medium, and the semiconductor particle, the heating being configured to cause at least some of the dopant to diffuse from the first liquid medium into the surface; depositing a dielectric material in the gap on the surface; selectively removing the first quantity and the second quantity of the medium from the surface; depositing an electronic contact on each of the first portion and the second portion; and depositing additional electronic contacts on the dielectric material.

The method may include forming a barrier island in the gap on the plane before depositing the first and second quantities of dielectric material; and selectively removing the barrier island from the surface before depositing the dielectric material.

Forming the barrier islands may include depositing a third amount of a second liquid medium including the barrier material in the gaps on the surface.

Forming a barrier island may include: depositing a layer of photosensitive material on the surface; exposing an area of the photosensitive material covering the gap to light configured to modify the photosensitive material; and selectively removing unexposed areas of the photosensitive material layer from the surface, thereby forming a barrier island including the photosensitive material modified by light.

Depositing the dielectric material may include depositing a fourth amount of a third liquid medium including the dielectric material in the gap on the surface.

The fourth quantity of media may wet the first and second quantities of media at a wetting angle of less than approximately 90°.

Heating can also selectively remove barrier islands from the surface.

Depositing the first quantity of the medium and the second quantity of the medium may include: depositing an initial quantity of the first liquid medium on the surface, the initial quantity of the medium covering a first portion of the surface, a second portion of the surface, and a barrier island arranged between the first portion and the second portion; and heating the initial quantity of the medium to reduce the volume of the initial quantity of the medium by at least partially evaporating one or more components of the first liquid medium, thereby exposing the barrier island and forming the first quantity of the medium and the second quantity of the medium separated from each other by the barrier island.

The surface includes a flat surface.

The flat surface includes the planarized surface of the semiconductor particles.

The first quantity of media and the second quantity of media are separated by a gap of about 0.1 μm to about 100 μm.

Printing is used to one or more of: deposit a first quantity of dielectric; deposit a second quantity of dielectric; deposit a dielectric material; deposit an electronic contact on each of the first portion and the second portion; deposit additional electronic contacts.

Printing includes one or more of the following: screen printing; inkjet printing; decals; flexographic printing; gravure printing; and offset printing.

According to another embodiment of the present specification, a method for forming an electronic device is provided, the method comprising: providing a semiconductor substrate having a surface, the surface comprising a first portion and a second portion, the first portion and the second portion being separated by a gap; forming a barrier island in the gap on the surface; depositing a first quantity of a first liquid medium comprising a dopant on the first portion of the surface, and depositing a second quantity of the first liquid medium on the second portion of the surface, the first quantity of medium being separated from the second quantity of medium by the barrier island; heating the first quantity of medium, the second quantity of medium, and the semiconductor substrate, the heating being configured to cause at least some of the dopants to diffuse from the first liquid medium into the surface; selectively removing the barrier island from the surface; depositing a dielectric material in the gap on the surface; selectively removing the first quantity of medium and the second quantity of medium from the surface; depositing an electronic contact on each of the first portion and the second portion; and depositing additional electronic contacts on the dielectric material.

Forming the barrier islands may include depositing a third amount of a second liquid medium including the barrier material in the gaps on the surface.

Forming a barrier island may include: depositing a layer of photosensitive material on the surface; exposing areas of the photosensitive material covering the gap to light configured to modify the photosensitive material; and selectively removing unexposed areas of the photosensitive material layer from the surface, thereby forming a barrier island comprising photosensitive material modified by light.

Depositing the dielectric material may include depositing a fourth amount of a third liquid medium including the dielectric material in the gap on the surface.

The fourth quantity of media may wet the first quantity of media and the second quantity of media at a wetting angle of less than approximately 90°.

Heating can also selectively remove barrier islands from the surface.

Depositing the first quantity of the medium and the second quantity of the medium may include: depositing an initial quantity of the first liquid medium on the surface, the initial quantity of the medium covering a first portion of the surface, a second portion of the surface, and a barrier island arranged between the first portion and the second portion; and heating the initial quantity of the medium to reduce the volume of the initial quantity of the medium by at least partially evaporating one or more components of the first liquid medium, thereby exposing the barrier island and forming the first quantity of the medium and the second quantity of the medium separated from each other by the barrier island.

The surface includes a planarized surface of a semiconductor substrate.

Printing is used to one or more of: deposit a first quantity of dielectric; deposit a second quantity of dielectric; deposit a dielectric material; deposit an electronic contact on each of the first portion and the second portion; deposit additional electronic contacts.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of an array of semiconductor spheres adhesively placed on a substrate to permanently affix the spheres at predetermined locations.

FIG2 is a photograph of an array of glass spheres arranged on a non-silicon substrate.

3a is a cross-sectional view of semiconductor spherical particles deposited on a gridded substrate with a conformal coating deposited on top of the spherical particles.

FIG. 3 b is a cross-sectional view of the semiconductor spherical particle shown in FIG. 3 a after planarization.

Figures 4a to 4f illustrate methods of forming contacts on a flat surface and to the outer surface of, for example, a sphere, for providing a solar cell array.

5a is a partial cross-sectional view of complementary NMOS and PMOS circuits formed on a planarized semiconductor grain that is doped with a p-type material during grain formation.

FIG5 b is a cross-sectional view of a single transistor device fabricated within a single planarized sphere.

Figure 5c is an isometric view of a circuit with a symbolic representation showing a gated transistor in a flattened spherical particle.This single cell would also form a standalone circuit that could be packaged and act as a standalone device, replacing a similar device fabricated on a silicon wafer.

Figure 5d shows the spherical particles of Figure 5b, illustrating that an array of these particles can be made with adjacent particles (not shown) having transistors therein.

6a to 6d are cross-sectional views of particles, where the maximum depth is shown perpendicular to the planarized surface.

Figure 7 shows a cross-section of an active matrix display.

FIG8 shows a cross-sectional view of another embodiment of an active matrix display.

FIG9 shows a cross-sectional view of a pixel region of an electroluminescent component.

FIG10 shows a cross-sectional view of another embodiment of an active matrix display.

11 a to 11 e illustrate steps in a method of forming an electronic device on a semiconductor substrate.

12a to 12f illustrate steps in another method of forming an electronic device on a semiconductor substrate.

13a-13g illustrate steps in another method of forming an electronic device on a semiconductor substrate.

14a-14g illustrate steps in another method of forming an electronic device on a semiconductor substrate.

DETAILED DESCRIPTION

Turning now to FIG. 1 , a substrate 10 is shown, which can be plastic, glass, semiconductor material, or any other suitable stable material for supporting electronic circuits. An adhesive layer 12 is applied to the upper surface of substrate 10 and has a grid 14 with predetermined gaps between grid elements sized appropriately to accommodate semiconductor spheres 16 having diameters less than 15 mm, and preferably less than 2 mm. The term "semiconductor sphere" as used hereinafter is intended to include spheres, spheroids, and semiconductor spheres having imperfections due to imperfections in the formation of the spheres. The arrangement shown in FIG. 1 generally allows circuit designers a great deal of control over where the spherical semiconductor material is located, and therefore, the location of the semiconductor devices on the planarized surface of the spheres 16 is determined after the spheres are planarized. Although the grid is shown with uniform spacing between grid openings, a grid with non-uniform spacing can be used to position the spheres in any desired pattern. Orienting the spheres can be very difficult if the electronic devices are fabricated on the planarized surface prior to positioning the spheres on the substrate. Thus, semiconductor spheres 16 are first fixedly attached to substrate 10 and then planarized to expose regions of high-quality semiconductor material within the sphere interior suitable for silicon electronic device fabrication; by way of example, CMOS devices can be formed in the planarized layer by doping the sphere material below and within the planarized layer. Spherical particles are described in detail and are particularly convenient for positioning and planarization, however, many other particle shapes can be used, as long as the particles can be conveniently positioned and fixed to the substrate and as long as the particles can be planarized to provide a surface on which electronic devices will be fabricated.

Typically, for most chip-based electronics, the unused chip area is reduced to a minimum, so the device density is high. The density is so high that the unused substrate area that is wasted because no active devices are manufactured on it is small. In displays and imagers, the device area is dictated by the needs of the devices that are not the electronics. Therefore, as displays get larger, the device density gets lower. At a certain point, it is no longer desirable to coat several square meters with low-quality Si to make a few devices, or millions of devices compared to the millions in a PC CPU. According to this invention, high-quality Si is placed only where it is needed, thus covering a smaller portion of the total display area of a large display. This technology turning point will occur as a result of the upcoming transition to faster OLED devices. OLEDs are current devices, and amorphous silicon on glass cannot carry the required current and speed.

Silicon spheres have been used previously to make large-area photovoltaic panels, as described in U.S. Patent No. 4,614,835, filed on December 30, 1983 in the name of Carson et al., "Photovoltaic Solar Arrays Using Silicon Microparticles," incorporated herein by reference. For photovoltaic applications, the surface of the spheres forms the active area. The silicon spheres can be made from low-cost powdered silicon, and the resulting recrystallized surface layer of silicon dioxide can outgas a large number of impurities. Repeated melting cycles can improve the overall material purity. Even in the case of polycrystalline particles, the electron mobility is many times that of amorphous silicon.

According to this invention, for electronic devices, it was found that it is preferable to use a flat surface of a cross section of a semiconductor particle such as a sphere rather than a curved outer surface to manufacture the device. This flat surface allows the use of standard photolithography techniques, allows the manufacture of transistors, interconnections, etc. For example, a silicon sphere with a diameter of 20 microns provides a maximum area A = π x r ² = ~ 314 microns ² for device manufacturing. Many transistors with a gate length of approximately 1 micron can be manufactured in this area. For large-area displays, only a small number of transistors are required per pixel, and the pixel size is not proportional to the display size. High definition (HD) is a standard resolution (for example, 1920x1080 pixels). In addition, a flat area of high-quality single-crystal silicon can serve more than one pixel and provide additional functions such as self-test and display performance monitoring and correction.

Using a flat cross-section of a planarized particle, such as a truncated flattened sphere, allows standard photolithographic manufacturing techniques to be used. Furthermore, through planarization, imperfections present on the surface of the sphere or spheroid are removed when etching or polishing the sphere or spheroid to expose the interior region. Advantageously, because the sphere is purified in a separate process, high-temperature processing, unavailable for amorphous silicon on glass substrates, can be used to achieve high-purity single-crystalline silicon material when the glass substrate is melted at temperatures below standard silicon processing temperatures. This is even more important for lower-melting-temperature substrates such as plastic. When the cross-section is exposed, the truncated sphere or other shaped planarized particle can be doped or doubly doped slightly below or above its flat surface to form rings or "wells" of n-type and p-type material; doping can also occur later in the process. This allows for the fabrication of CMOS devices such as those shown in Figure 5. While ion implantation is the preferred method for doping the regions, doping can also be achieved by spin-coating dopants onto the planarized surface. The external surface can be highly doped or metalized to form substrate contacts accessible from the edge of the top surface or from anywhere on the spherical surface, which is effectively the backside. The term "contact" as used in this specification can be a physical wire or metalized contact area, such as a wire or conductive contact pad through which a wire or device can make electrical contact.

The present invention provides spherical silicon particles at known locations on a substrate, preferably a non-silicon substrate. Positioning the silicon spheres on the substrate can be achieved by any of several techniques. Most techniques involve patterning the substrate to have multiple locations where the spheres will be placed. A metal or dielectric grid can first be applied to the substrate permanently or temporarily, or standard photolithographic techniques can be used. Alternatively, dots, dimples, or other patterns of adhesive can be applied to position the spheres. The adhesive material should be selected to have a melting point or adhesiveness that is appropriately matched to subsequent electronic processing at room temperature.

As an alternative to depositing or applying a grid, the substrate can be patterned directly using standard photolithographic techniques to create holes in the substrate into which the adhesive used to secure the semiconductor spheres will be deposited. In some embodiments, a non-malleable ceramic material can be used as the substrate. The holes can be made in environmentally friendly (i.e., non-fired) ceramics using techniques including, but not limited to, punching or drilling.

In another embodiment, as described in U.S. Patent Nos. 6,464,890 and 6,679,998, filed by Knappenberger et al. on August 29 and August 23, 2001, respectively, and incorporated herein by reference, silicon particles can be used to form a monolayer on the substrate surface instead of non-semiconductor spheres used to form the mask. As long as the particles are of a predetermined size, subsequent processing can provide planarized silicon particles, such as spherical particles, at the desired locations.

In FIG1 , an exemplary technique for using a metal grid 14 with an adhesive layer 12 is shown. Spheres 16 are then placed on the surface in sufficient numbers so that moving the spheres on the grid using mechanical vibration results in complete occupancy of the grid openings. The mechanical vibrations move the silicon spheres 16 around the volume defined by the substrate, walls, and lid. In a very short time, the spheres 16 move back and forth so that the probability of encountering an available grid position is consistent as long as the spheres remain available. It is contemplated that other types of mechanical agitation may be used instead of and/or in addition to vibration. For example, the substrate on which the spheres are placed may be rotated about one or more axes and/or translated in one or more directions.

FIG2 shows a micrograph of such a device fabricated on a glass substrate with a grid. In this exemplary case, glass spheres are used and have a diameter of 20 microns. Mechanical vibrations are used to move the glass spheres back and forth across the grid. A high voltage (V≤12 kV) is then applied to the grid to aid in removing the spheres from the upper surface of the grid. Some excess spheres and dust are still visible, but these can be reduced or removed in a cleanroom environment and/or removed in subsequent processing steps.

For large areas, the spheres can be applied in dense lines across the surface in one direction and then vibrated in a wave-like manner across the surface of the substrate. In some embodiments, semiconductor particles can be placed on the surface of the substrate to substantially or completely cover the surface of the substrate before mechanically shaking the substrate and semiconductor particles.

It is foreseeable that similar techniques utilizing mechanical shaking can be used, wherein the substrate includes a through hole for at least partially receiving semiconductor particles at a predetermined position. An adhesive layer can be applied on one side of the substrate, wherein the adhesive layer covers one end of the through hole. The semiconductor particles can be placed on the other side of the substrate relative to the face that bears the adhesive layer, and then the substrate and the semiconductor particles can be mechanically shaken so that the semiconductor particles eventually partially occupy the holes in the substrate. The semiconductor particles can be attached to the part of the adhesive layer that can be reached through the hole, and therefore retained and/or fixed in the hole. The adhesive layer can include glass glue or other adhesives that are suitable, well known to the technician.

Alternatively, an external electrode can be used to apply an electric field in order to move particles on the substrate, as described in "Structure of the process of aggregating microspheres on patterned electrodes" (Ting Zhua, Zhigang Suob, Adam Winkleman and George M. Whitesides, Applied Physics Letters, 88, 144101, (2006)) (hereinafter referred to as Document 1). In this method, an electric potential is generated using a lower electrode placed below a dielectric substrate, and a conductive grid is used as a counter electrode. The holes in the grid create a potential well into which the spheres can fall. The electric field gradient around the hole is sufficient to generate a net force acting on the particles. For an applied electric field (KV) that is large enough, the particles can move into the hole. Initially, vibration may be required to move the spheres back and forth so that they encounter the potential well.

In another approach, a similar process to that used in laser printing can be utilized. In a laser printer, a triboelectrically generated charge is applied to the toner particles. The charged toner particles are then applied to an electrostatically charged (drum) substrate. During laser printing, the toner particles are then transferred to the electrostatically charged substrate (usually paper). During laser printing, a laser is used to write a pattern on a dotted drum, but since the pattern does not change in a production environment, the laser can be replaced by a grid. In first generation laser printers, the toner particle size of approximately 16 microns is essentially the same as the spheres in Figure 2. By applying a voltage to an electrode below the dielectric substrate to attract the charged spheres and applying the opposite polarity to the grid, the spheres are selectively attracted to the holes. This method can be considered an enhancement of the method described in Document 1.

In an alternative embodiment of the invention, the array of spheres can then be transferred from the first substrate running similar to a laser printer drum to another unpatterned substrate running similar to charged paper, exactly like the laser printing described. Alternatively, if the adhesive on the second unpatterned substrate or the adhesive applied to the spheres has, for example, a higher melting temperature, greater adhesive or electrostatic attraction, then the array transfer from the first substrate to the second substrate can also be achieved. When the exemplary device of Figure 1 uses an adhesive layer, the substrate or grid below the layer can be a heat softening layer, such as a thermoplastic layer at high temperature, so that when the substrate is cooled to ambient temperature, the spheres adhere to the contacts and remain in place. The adhesive can be a thin layer applied to the substrate. The relatively small size of the spheres means that a significant contact area is achieved for a small layer thickness of the adhesive.

Because silicon has a higher melting temperature than glass, glass substrates can be used directly if they are heated sufficiently to soften the glass and thereby allow silica-coated or deoxidized spheres to adhere directly to the glass, providing a component that can withstand higher post-processing temperatures. This can be achieved by using electrostatic attraction to transfer arrays of particles from a patterned substrate to unpatterned glass, as in laser printing. By attaching the particles directly to glass, the window for higher temperature processing can be expanded to points where the interior of the semiconductor sphere's cross-section is exposed. The same printing process can be applied to other substrates.

Once the spheres 16 are in place, a conformal coating 18 is applied and then planarized using a variation of a standard planarization technique, such as chemical mechanical polishing, as shown in FIG3a , where a coating 18 of SiO ₂ is shown covering the spherical particles 16 and the grid 14 . FIG3b shows the same array of FIG3a after planarization and before device fabrication on the spheres in the form of truncated hemispheres. Standard planarization techniques used in integrated circuit fabrication can be utilized. Because the topography can exceed what the process supports when multiple layers are deposited sequentially, planarization can occur multiple times in the process, such as after the conformal dielectric coating is applied, followed by planarization; and after the conductive coating is applied, followed by planarization. Connections between layers are made by opening holes or vias at lithographically defined locations and depositing conductive connectors or plugs between the layers. This is particularly beneficial. In the case of planarized metal layers, the layers are patterned to form the desired interconnects. In contrast to the prior art of planarizing a surface without exposing all underlying elements (as described in U.S. Patent No. 4,470,874, filed December 15, 1983, and incorporated herein by reference, entitled Planarization of Multilayer Interconnect Metallization Systems), in the present invention, the planarization process is performed to expose the interior cross-sections of the semiconductor grains.

Although the silicon spheres are randomly oriented, the anisotropy of mobility in Si is small, so the final device manufactured will have higher performance than devices made using amorphous silicon or polycrystalline silicon. However, if the application is less demanding and, for example, does not require a high-speed device, polycrystalline silicon or non-spherical particles can be used.

While spherical particles are preferred, powdered, single-crystal, or multicrystalline silicon can be used if the performance requirements for a particular application are suitable. In addition, multiple placement cycles can be used to place particles of different sizes or different material properties to achieve different functions in the final device, such as doping or crystalline quality or atomic species, such as III-V, such as GaAs, or quaternary alloys for light sources, or SiGe.

Standard photolithography techniques are used to fabricate the device on the exposed silicon surface, as well as the interconnects and other elements required for device functionality. The present invention allows for the fabrication of nearly conventional CMOS devices; however, it may be beneficial to utilize other processes. The present invention does not inherently limit the type of process that can be used. For example, n-type and p-type silicon particles can be deposited in separate steps to implement an n-well and a p-well using separate silicon particles. In conventional CMOS, the n-well shown in FIG5 a must be fabricated within a global p-type substrate. Turning now to FIG5 b , a device similar to that of FIG5 a is shown fabricated within spherical particles doped with p-type material used to form p-type spheres. In this figure, a hemispherical semiconductor device 50 is shown, in which a flattened sphere 56 forms a gated semiconductor transistor device having a source (S), a drain (D), and a gate (G), as well as a contact B, which forms a substrate bias when the device is within the doped well, as shown. In this case, a single device is formed within the flattened semiconductor device. Each line extending from the device to B, S, D, and G is an electrical contact. The number of discrete devices that can be fabricated in/on a single crystal grain depends largely on the size of the planarized area. For example, if the device has a 1 μm gate length and a 1 μm via, the entire device may be a 5 μm x 5 μm device. However, a sphere with a 20 μm diameter would have a surface area greater than 300 ^μm2 , which would accommodate several devices. By way of example, a 2x2 array of pixels or a single pixel with additional circuitry such as lifecycle control would be built in. Considerations for sphere size would be cost, reliability, and yield. The device shown in Figure 5a can be fabricated on any or all of the planarized spheres shown, for example, in Figure 3b.

Symbolic representations of transistors 55a, 55b are shown in Figures 5c and 5d. Further, doping occurs to realize NMOS and PMOS devices in the same sphere. In Figure 5c, an array of function-controllable devices (such as transistors) can be manufactured. Although not shown in the array 58 of the flattened sphere 56, the array of devices will be manufactured in the same process. In other words, all transistors will be doped at the same time. After the devices are manufactured, a passivation layer 59 will be applied directly on the top of the flattened sphere. Layer 59 is shown before it is placed on the active device. Although the advantage of the present invention is that arrays of any size can be manufactured, it may be desirable to cut the array into smaller functional units that can be placed in the desired position. In this case, the current device for cutting silicon wafers can be used.

The final electronic assembly can then serve as the basis for various devices, such as displays or imagers.

According to one aspect of this invention, non-glass substrates such as plastic, polyester film, polyimide, or other application-appropriate materials can also be used, allowing not only reduced production costs but also the realization of flexible and pliable devices. As the size of the semiconductor particles decreases, the minimum bend radius also decreases. For silicon particles smaller than the thickness of the substrate, the mechanical properties will be primarily determined by the non-silicon elements of the device, and thus the device can be made flexible or pliable, or a combination thereof. Devices can also be made where the mechanical properties vary throughout the device, with mechanical stiffness being specified as a function of position within the device.

In a further variation of the invention, a large substrate can be cut to form small devices in the same way that a silicon wafer is cut into devices of a preferred size; the devices are small relative to the substrate. The present technology will be applicable where cost and performance allow the use of non-silicon substrates. For example, in many silicon devices, the area occupied by contact pads and interconnects can be essentially the same as the device area. In other applications, device performance can be enhanced by using a substrate with a large thermal conductivity. Here, the spherical back of the particles provides a larger surface through which heat can be removed.

As mentioned previously, this invention also allows solar cells to be manufactured using similar manufacturing methods. Turning now to Figures 4a to 4f, a process for manufacturing a solar cell is shown, wherein the spheres 16 doped with p-type material shown in Figure 4a are located in openings with a grid 14 and are fixed to a light-transmitting substrate 10 that supports them. In Figure 4b, the spheres and grid are covered with a _SiO2 layer 43, and in Figure 4c, a metallization layer 45 is applied. In Figure 4d, the structure is flattened and the spheres have a flattened upper surface 47. In Figure 4e, a via and conductive socket structure 48 is provided. In addition, not shown in Figure 4e, a flattened area slightly below the flattened surface is doped with n-type material, and in a subsequent step of Figure 4f, interconnects 46 and 49 are formed so that all interconnects are located on the flattened upper surface that contacts the p-material and the n-material. This flattened upper surface actually forms the back of the solar panel.

The term planarized particles or particles with a planarized surface refers to particles in a preferred embodiment that have a longest dimension of 15 mm across the planarized surface and a depth (d) of at least 1 μm perpendicular to the planarized surface. Preferably, these particles are spheres, spheroids, or incomplete spheres or spheroids. However, other particle shapes are within the scope of this invention. Figures 6a to 6d illustrate various particle shapes 60 and show the depth (d) perpendicular to the planarized surface of the particle.

Arrays of electronic devices manufactured according to the foregoing description, including but not limited to the electronic devices shown in Figure 5d, can be used as backplanes for active matrix electro-optical devices. These electro-optical devices may include but are not limited to displays and imagers. In these devices, gate-controlled electronic components manufactured at the flattened cross-section of the semiconductor particles above and/or below the flattened surface can be electrically connected to one or more pixels of the optical portion of the electro-optical device. The optical portion may include a light-emitting portion in the case of a display and/or a light-detecting portion in the case of an imager. Controllable gate-controlled electronic devices including but not limited to transistors can be used to control and/or provide power to light-emitting pixels in the case of a display, and/or can be used to collect electrical signals from light-detecting pixels in the case of an imager.

FIG7 shows a schematic representation of a cross-section of a display 700 including a backplane 705 electrically connected to a light emitting assembly. The light emitting assembly may include, but is not limited to, an organic light emitting diode (OLED) assembly 715, in which case the display 700 may be an active matrix OLED display. Although the following description refers to an OLED assembly, it is contemplated that the light emitting assembly may be any suitable electroluminescent assembly known to those skilled in the art.

The backplane assembly for display 700 may include planarized semiconductor particles, such as planarized spheres 56, secured to substrate 10. Hereinafter, substrate 10 will be referred to as "backplane substrate 10." For the purposes of this description, substrate 10 and backplane substrate 10 may be interchangeable. One or more gated electronic components, including but not limited to transistors 55a, may be formed at the flattened cross-section of the flattened spheres 56 above and/or below the flat surface. Although FIG. 7 shows only one transistor 55a per flattened sphere 56, two or more gated electronic components may be formed at the flattened cross-section of one or more semiconductor particles of backplane 705 above and/or below the flat surface. The gated electronic components may also be of different types and designs, including but not limited to different kinds of transistors. The gated electronic components may also include any lithographically patterned circuit elements. The following description relates to transistor 55a, but it is contemplated that any type and/or kind of suitable circuit elements and/or electronic components known to those skilled in the art may be used in place of and/or in addition to transistor 55a.

Contact 710 may be formed at the flattened cross-section of flattened sphere 56 above and/or below the flat surface. Contact 710 is in electrical contact with transistor 55a. In addition and/or alternatively, contact 710 may be in electrical contact with one or more other circuit elements and/or combinations of circuit elements. These circuit elements may include, but are not limited to, capacitors. Although only one contact 710 is shown for transistor 55a in FIG7 , it is foreseeable that two or more contacts may be formed for each transistor, depending on the design of the transistor and/or the number and type of connectors required between transistor 55a and the pixels of OLED assembly 715. Contact 710 may include a deposited layer of conductive material, including, but not limited to, a metallic material. In addition and/or alternatively, contact 710 may include: a metal-filled epoxy (including, but not limited to, silver epoxy), a carbon-filled epoxy, and a low-temperature solder including indium or an indium-tin alloy.

The OLED assembly 715 may include an OLED substrate 720 and one or more organic light-emitting layers 740 in contact with one or more electrodes. In one embodiment, the OLED assembly 715 may include one or more pixel regions 725, 730. The one or more pixel regions 725, 730 may include a first electrode 735 deposited on the OLED substrate 720, one or more organic light-emitting layers 740 deposited on the first electrode 735, and a second electrode 745 deposited on one of the organic light-emitting layers 740, such that at least one of the organic light-emitting layers 740 is sandwiched between the first electrode 735 and the second electrode 745. While FIG. 7 illustrates each pixel region 725, 730 having its own stack of first electrode 735, organic light-emitting layer 740, and second electrode 745, it is contemplated that the first electrode 735 and one or more of the organic light-emitting layers 740 may span multiple pixel regions. While a particular architecture and geometry of the OLED assembly 715 is shown and described, it is contemplated that different architectures and geometries of the OLED assembly 715 known to those skilled in the art may also be used in the display 700.

The OLED substrate 720 may include a material that is at least partially transparent to light emitted by the organic light-emitting layer 740. The OLED substrate 720 may include materials including, but not limited to, glass, plastic, and polyimide. The first electrode 735 may include a conductive material that is at least partially transparent to light emitted by the organic light-emitting layer 740. The first electrode 735 may include indium tin oxide (ITO). In some embodiments, the OLED substrate 720 may also serve as the first electrode. The second electrode 745 may include a layer of conductive material including, but not limited to, aluminum and/or copper.

Adjacent pixel regions 725, 730 can be distinguished from each other by one or more of a separate first electrode 735, a separate organic light-emitting layer 740, and/or a separate second electrode 745. In some embodiments, one or more of pixel regions 725, 730 can each have two or more different second electrodes, which can serve as pixel contacts for their respective pixel regions. In FIG7 , dashed lines across OLED substrate 720 demarcate the approximate boundaries of each pixel region 725, 730. These dashed lines are for illustrative purposes and do not necessarily represent physical features of OLED assembly 715.

An active matrix OLED display can be formed by electrically connecting the backplane 705 to the OLED assembly 715 so that at least one of the pixel regions 725, 730 is electrically connected to a corresponding one or more gate-controllable electronic components, for example, to the transistor 55a. In FIG7 , the pixel region 725 is shown as being electrically connected to only one contact 710 of the transistor 55a. In other embodiments, other ways of connecting the pixel regions to the transistors may include, but are not limited to: a pixel region may be connected to multiple transistor contacts and/or to multiple transistors; a transistor contact 710 and/or a transistor 55a may be connected to multiple separate second electrodes, i.e., pixel contacts of the pixel region 725; and a transistor 55a may be connected to multiple different pixel regions 725, 730.

The OLED assembly 715 can be electrically connected to the backplane 705 via one or more conductive links 750. The conductive link 750 can connect the transistor 55a to the corresponding pixel area 725. The conductive link 750 may include a conductive bridge located between the contact 710 and the second electrode 745. The conductive link 750 may include a soft and/or flexible conductive link. The conductive link 750 may include one or more conductive epoxies such as silver epoxy, solder, and low-temperature solder. In some embodiments, the transistor 55a may not have a prefabricated contact 710, and the conductive link 750 may connect the second electrode 745 to the transistor 55a. In some embodiments, the pixel area 725 may not include the second electrode 745, and the conductive link 750 may directly connect the contact 710 and/or the transistor 55a to at least one of the organic light-emitting layers 740.

Using soft and/or conductive links 750 can reduce the likelihood of the conductive links 750 damaging the organic light emitting layer 740 and/or the likelihood of the conductive links 750 causing an electrical short to the first electrode 735 due to the conductive links 750 punching through the second electrode 745 and the organic light emitting layer 740. Using conductive links 750 that can be applied at relatively low temperatures can reduce the likelihood of thermal degradation and damage to the organic light emitting layer 740, which can be heat sensitive.

The active matrix OLED display 700 can be formed by electrically connecting the backplate 705 to the OLED assembly 715 using the conductive links 750 described above. To position each pixel region 725, 730 adjacent to its corresponding transistor 55a (before connecting the two), the backplate 705 and the OLED assembly 715 can be aligned with each other before the backplate 705 is coupled to the OLED assembly 715. Alignment can be performed using optical or physical markings on one or both of the backplate 705 and the OLED assembly 715. Alignment can also be performed by placing the backplate 705 and the OLED assembly 715 in a fixture that determines their relative positions.

When the backplane 705 is bonded to the OLED assembly 715 via the conductive links 750, gaps 760 may be maintained between the backplane 705 and the OLED assembly 715. These gaps 760 may be partially or completely filled with a backfill material to further mechanically strengthen the connection between the backplane 705 and the OLED assembly 715. In addition, in order to reduce and/or eliminate any visible reflections from the backplane substrate 10 that may interfere with the image generated by the OLED display 700, the backfill material may be opaque, light-scattering and/or light-absorbing. In some embodiments, the backfill material may be substantially black. Being substantially black may include reflecting a sufficiently small portion of the light incident on the backplane so that the reflected light does not constitute a visible interference with the image generated by the OLED display 700 to the human eye.

During the manufacture of the OLED display 700, the backplane 705 and the OLED assembly 715 can be formed separately and then joined together. For example, the backplane 705 can be formed as previously described. The OLED assembly 715 can be formed separately from the backplane 705 and positioned on an OLED substrate 720 that is different from the backplane substrate 10. Forming the OLED assembly 715 separately from forming the backplane 705 allows each part of the manufacturing process to be optimized independently. In addition, this two-part manufacturing process allows for separate quality control for the OLED assembly process and the backplane manufacturing process. Defects in a batch of backplanes 705 or OLED assemblies 715 will only affect the subcomponent and will not affect the entire display 700.

Furthermore, separate fabrication of the OLED assembly 715 can allow for greater control over the formation of various components of the pixel regions 725, 730, including the organic light-emitting layer 740. The OLED substrate 720 and/or the first electrode 735 can constitute a more suitable substrate, e.g., a flatter or smoother substrate, for depositing the organic light-emitting layer 740, which can be sensitive to non-uniformities in the substrate on which it is deposited. More consistent deposition of the organic light-emitting layer 740 can also reduce the likelihood of punch-through electrical shorts, which can result from a damaged organic light-emitting layer 740 that allows electrical connections between the first electrode 735 and the second electrode 745, the conductive link 750, and/or the contact 710.

To operate the OLED display 700, an electrical potential is applied between the first electrode 735 and the second electrode 745, thereby applying an electrical potential to the organic light-emitting layer 740. The first electrode 735 can be connected to a transistor, a power source, and/or electrical leads on the backplane 705, and/or the first electrode 735 can be connected to a power source and/or electrical leads independent of the backplane 705. The second electrode 745 can be connected to the transistor 55a. One or more of the organic light-emitting layers 740 can then emit light visible to humans, which can be emitted through the first electrode 735 and the OLED substrate 720 and out of the OLED assembly 715 in a light emission direction 755. The transistor 55a can provide power to the organic light-emitting layer 740 and/or control the power applied to the organic light-emitting layer 740 to control the emission properties of the pixel regions 725, 730, including but not limited to brightness and on/off state.

7-10 illustrate three organic light emitting layers 740, it is contemplated that fewer or more than three organic light emitting layers may be used. When multiple organic light emitting layers 740 are present, each layer may comprise a different material.

In some embodiments, each pixel region 725, 730 may emit only one color. In other embodiments, the pixel regions 725, 730 may emit multiple colors. For example, each pixel region 725, 730 may have multiple sub-pixel regions, each of which emits a single color. For example, each sub-pixel may emit one of red, green, and blue light. When the pixel regions 725, 730 have sub-pixel regions, each sub-pixel region may have its own separate second electrode 745, i.e., its own separate sub-pixel contact. Each sub-pixel region may be controlled by one or more corresponding transistors.

FIG8 shows a cross-section of an active-matrix display 800, which may be an active-matrix OLED display. The backplane 705 in display 800 is identical to that in display 700 and includes transistors 55 a having contacts 710 formed above and/or below the planar surface of planarized spheres 56 affixed to backplane substrate 10. Display 800 differs from display 700 in that, in display 800, the light-emitting components are deposited directly onto backplane 705. For example, organic light-emitting layers 740 may be deposited directly onto the planar surface of planarized spheres 56, such that at least one of the organic light-emitting layers 740 is in electrical contact with contacts 710 of transistor 55 a.

The first electrode 735 may be deposited onto one and/or the outermost of the organic light emitting layers 740. While the organic light emitting layers 740 and the first electrode 735 are shown as forming discrete stacks on each different transistor 55a, it is contemplated that one or more of the organic light emitting layers 740 and/or the first electrode 735 may be deposited as a single layer spanning multiple transistors 55a.

In some embodiments, the organic light-emitting layer 740 may be deposited on the surface of the backplane substrate 10 other than the flat surface of the flattened spheres 56 and on the flat surface of the flattened spheres 56. In some embodiments, the surface of the backplane substrate 10 may be coated with a material such as a glass sealant, ceramic glass, and/or plastic to reduce and/or eliminate porosity on the surface of the backplane substrate 10 prior to depositing subsequent layers such as the organic light-emitting layer 740. In some embodiments, a second electrode layer may be deposited on the contact 710 prior to depositing the organic light-emitting layer 740 and the first electrode 735.

The first electrode 735 can be connected to a transistor, a power source, and/or an electrical conductor on the backplate 705, and/or the first electrode 735 can be connected to a power source and/or an electrical conductor independent of the backplate 705. When an electric potential is applied between the contact 710 and the first electrode 735, the organic light emitting layer can emit light visible to the human eye along a direction of light emission 755. Similar to the display 700, the pixel regions 805, 810 of the display 800 can each emit only one color, or multiple colors. It is contemplated that other layers can be deposited as part of the display 800, including but not limited to passivation layers, encapsulation layers, and/or protective layers.

FIG9 illustrates a cross-section of pixel region 905, which may form part of an OLED assembly used to form an OLED display similar to display 700. Pixel region 905 is similar to pixel regions 725 and 730 in that it includes an OLED substrate 720, a first electrode 735 formed on OLED substrate 720, an organic light-emitting layer 740 formed on first electrode 735, and a second electrode 910 formed on organic light-emitting layer 740. Pixel region 905 differs from pixel regions 725 and 730 in that second electrode 910 includes an extension 915. Extension 915 may extend beyond organic light-emitting layer 740 and first electrode 735 in pixel region 905. Extension 915 may be formed directly on OLED substrate 720. Second electrode 910 and/or its extension 915 may be insulated from first electrode 735 by an insulating region 920. Insulating region 920 may include a material and/or dielectric with sufficiently low conductivity to prevent electrical shorting between first electrode 735 and second electrode 910.

When connected to the backplate 705, a conductive link 750 may be formed between the contact 710 and the extension 915. Because the connection point may be insulated from and/or spatially removed from the first electrode 735, any damage to the extension 915 during the connection process is less likely to cause a punch-through short between the first electrode 735 and the second electrode 910. Furthermore, because the extension 915 is spatially removed from the organic light emitting layer 740, any thermal, mechanical, and/or chemical damage during the connection process is less likely to damage the organic light emitting layer 740, which may be susceptible to such types of damage.

FIG10 illustrates an active matrix display 1000, which may be an OLED display. Display 1000 is similar to display 700 in that it includes an OLED assembly 715 having an OLED substrate 720, a first electrode 735, an organic light-emitting layer 740, and a second electrode 745. When an electric potential is applied to pixel region 725 across first electrode 735 and second electrode 745, organic light-emitting layer 740 may emit light visible to the human eye, which may pass through first electrode 735 and OLED substrate 720 and be emitted along a light emission direction 755.

The backplane structure of display 1000 differs from that of display 700 in that, in display 1000, backplane substrate 1005 includes one or more vias 1015. Vias 1015 may comprise through-holes connecting one side of backplane substrate 1005 to an opposite side. Alternatively and/or in addition, vias 1015 may comprise conductive paths connecting one side of backplane substrate 1005 to an opposite side. Backplane 1002 may include transistors 55a formed above and/or below the flat surface of flattened spheres 56 secured to backplane substrate 1005. Contacts 1010 may be in electrical communication with transistors 55a and have a middle portion 1020 extending through vias 1015 and terminating at terminal portions 1025 located on or near the side of backplane substrate 1005 opposite the side on which transistors 55a are formed. In embodiments where vias 1015 comprise conductive paths, contact 1010 may comprise a conductive link between transistor 55a and a first end of the conductive path. The second end of the conductive path near the opposite side of the backplane substrate 1005 can then serve as the terminal portion 1025 of the contact 1010. In this manner, a conductive path can be provided between the terminal portion 1025 and the transistor 55a. In some embodiments, the insulating portion 1030 can electrically insulate portions of the contact 1010 from the flattened sphere 56 and/or portions of the transistor 55a.

The OLED assembly 715 can be electrically connected to the backplate 1002 via a conductive link 750 between the second electrode 745 and the terminal portion 1025 of the contact 1010. This geometry allows the OLED assembly 715 to be connected to the side of the backplate 1002 opposite the side that carries the transistor 55a. Because the operation of the transistor 55a can generate heat, being able to connect the OLED assembly 715 to the side of the backplate 1002 opposite the side that carries the transistor 55a can keep the transistor 55a away from the OLED assembly 715 and at least partially protect the OLED assembly 715 from the heat generated by the transistor 55a. In particular, the organic light-emitting layers 740 can be susceptible to damage and/or degradation from heat, so keeping them away from the heat-generating transistor 55a can reduce the likelihood of thermal damage and extend the life of the OLED assembly 715.

In all of the embodiments described above with respect to Figures 7-10, the light emitting assembly (such as the OLED assembly 715) can be replaced with a detector assembly for detecting photons to produce an imager instead of a display. The detector assembly can detect photons and, in response, generate an electrical signal. The signal can then be sampled by gateable electronic components (such as transistor 55a) and/or other suitable circuit elements on the backplane. It is contemplated that the gateable electronic components and other circuit elements of the imager can be different from the gateable electronic components and circuit elements of the display. The detector assembly can be an X-ray detector assembly for converting X-ray photons and generating an electrical signal in response. It is contemplated that the detector assembly can include any detector configured to detect an external event and generate an electrical signal in response. For example, the detector can detect external events other than the incidence of photons, such as contact with molecules, atoms, and/or subatomic particles. It is conceivable that the detector can be integrated vertically onto the top of the backplane.

Figures 11a-11e illustrate steps in a method 1100 for forming an electronic device on a semiconductor substrate. Figure 11a shows a semiconductor substrate 1105 having a surface 1107. A first quantity of liquid medium 1110 is deposited on a portion 1120 of surface 1107. A second quantity of liquid medium 1115 is deposited on a portion 1125 of surface 1107. First quantity of medium 1110 and second quantity of medium 1115 are separated from each other by a gap 1130.

The liquid medium includes a dopant configured to dope the semiconductor substrate 1105. The liquid medium may include a mixture of an organic component, a glass precursor, and a dopant. The organic material may include α-terpineol, isopropyl alcohol, polyvinyl alcohol, starch, carboxymethyl cellulose, dextrin, wax emulsion, polyethylene glycol, lignin sulfonate, methyl cellulose, paraffin wax, polyacrylate, and any other suitable material. In general, a suitable organic material may have one or more of the following properties: a small amount of ash remaining after combustion; easy to burn out at low temperatures; not rough; allows for easy dispersion; non-toxic; and inexpensive. The glass precursor may include silicon dioxide or any other suitable material. The dopant may include boron, phosphorus, or any other suitable material. The liquid medium may be a liquid and/or a glue under the conditions (e.g., temperature and pressure) under which it is deposited onto the semiconductor substrate 1105.

Additionally and/or alternatively, the liquid medium may include any other suitable material or mixture of materials, including but not limited to highly doped Si gel. In some embodiments, the liquid medium may include a mixture of a dopant, a resin, and a solvent, such as described in Hitachi Chemical Technical Report No. 56, which is incorporated herein by reference in its entirety. It is also foreseeable that the liquid medium may include nanoparticles dispersed in a solvent, the nanoparticles being doped with a dopant that can be used to dope a semiconductor substrate; for example, see Yang et al., "Doping Silicon Wafers with Boron Using Silicon Slurry" (Materials Science Technology, J. Met, 2013, 29(7), 652-654), which is incorporated herein by reference in its entirety. Another example of a liquid medium may include a "printable dopant" manufactured and sold by Honeywell and described in a publication entitled "Honeywell Printable Dopant for Advanced c-Si Cells," which is also incorporated herein by reference in its entirety.

First quantity of medium 1110 and second quantity of medium 1115 can be in the form of any of the following: droplets, droplets, beads, flakes, disks, blobs, masses, patches, smears, or any other quantity of liquid medium deposited and retained on surface 1107. First quantity of medium 1110 and second quantity of medium 1115 can have the same shape and/or amount as one another, or can have different shapes and/or amounts than one another.

Because first quantity of medium 1110 and second quantity of medium 1115 are comprised of liquid media, they can be printed onto surface 1107 using any suitable printing technique. Some techniques for printing include, but are not limited to, screen printing, inkjet printing, decals, flexographic printing, gravure printing, and offset printing. In general, any suitable printing technique can be used, depending on factors including, but not limited to, the viscosity of the liquid medium containing the dopant, the resolution and/or minimum feature size, alignment accuracy, and printing throughput. The ability to use printing instead of photolithography can significantly reduce the cost of the manufacturing process.

Although the above description proposes a liquid medium including a dopant, it is also foreseeable that the dopant can be in the form of solid particles that are electrostatically deposited on the semiconductor substrate and/or contained in solid particles that are electrostatically deposited on the semiconductor substrate. This deposition technique can be similar to the technique used in laser printing to transfer toner particles from a laser printer drum to paper, as described above. In other words, solid particles of the dopant and/or solid particles containing the dopant can be laser printed on the semiconductor substrate to form a first quantity of medium and a second quantity of medium. This laser printing technique may not require the transfer of any liquid or slurry to the semiconductor substrate. Similar laser printing techniques can also be used to print other components (e.g., gate dielectrics, source and drain contacts, gate contacts, and barrier islands) formed in conjunction with the manufacture of electronic devices on the semiconductor substrate, which components are described in detail below.

In some embodiments, semiconductor substrate 1105 can be pre-doped, and the dopant in the liquid medium can allow the doping of semiconductor substrate 1105 to be modified. For example, if semiconductor substrate 1105 is p-doped, the dopant in the liquid medium can allow semiconductor substrate 1105 to be n-doped, and vice versa. In the exemplary illustration of FIG11 , semiconductor substrate 1105 can be pre-doped and used to form a conductive channel of a field effect transistor electronic device, the conductive channel extending between the source and drain of the transistor. Dopants from the first quantity of medium 1110 and the second quantity of medium 1115 can be used to further dope semiconductor substrate 1105 (and/or modify the doping of semiconductor substrate 1105) to form the source and drain of the transistor.

Once the first quantity of medium 1110 and the second quantity of medium 1115 have been doped on surface 1107, substrate 1105, first quantity of medium 1110, and second quantity of medium 1115 can be heated to diffuse at least some of the dopant from the liquid medium of each of first quantity of medium 1110 and second quantity of medium 1115 into surface 1107. The heating step can be performed in a furnace. FIG11 b shows substrate 1105 after such a heating step, depicting a first doped region 1135 doped with a dopant from the first quantity of medium 1110 and a second doped region 1140 doped with a dopant from the second quantity of medium 1115.

The shape and size of the doped regions depend on a variety of factors, including, but not limited to, the properties of the dopant, the composition of the substrate 1105, and the heating profile (e.g., temperature over time). The shapes and relative sizes of the doped regions 1135, 1140 shown in FIG. 11b (and in all following figures) are for illustrative purposes only and are not intended to be limiting. Furthermore, the shapes and sizes of the first quantity of medium 1110 and the second quantity of medium 1115 are shown as unchanged between FIG. 11a (before heating) and FIG. 11b (after heating). This is for ease of illustration only, and it is contemplated that the shapes, sizes, states, and/or compositions of the first quantity of medium 1110 and the second quantity of medium 1115 may change after the heating step.

In some embodiments, instead of heating, a laser beam can be directed onto surface 1107 to drive dopants from first quantity of medium 1110 and second quantity of medium 1115 into surface 1107. Using a laser to induce doping can avoid heating the entire semiconductor substrate 1105 to high temperatures and can allow for the use of plastic and/or flexible substrates.

Once substrate 1105 has been doped with dopants from the liquid medium, dielectric material 1145 can be deposited in gap 1130 on surface 1107 (gap 1130 is not labeled in FIG. 11c , but is labeled in FIG. 11a ). FIG. 11c shows dielectric material 1145 deposited in gap 1130. Dielectric material 1145 can include aluminum oxide, a plastic such as polyimide, or any other suitable dielectric material. In some embodiments, dielectric material 1145 can include a polystyrene-block-poly(methyl methacrylate) composite material, such as the materials described in Ko et al., “Polystyrene-block-poly(methyl methacrylate) composite films as gate dielectrics for plastic thin-film transistor applications,” RSC Adv., 2014, 4, 18493, incorporated herein by reference in its entirety. It is also contemplated that dielectric material can be grown in gaps on a semiconductor substrate. For example, in embodiments where the semiconductor substrate comprises silicon, a silicon dioxide (SiO ₂ ) layer can be grown in the gaps of the dielectric material.

First quantity of medium 1110 and second quantity of medium 1115 can be used as a template for depositing dielectric material 1145 in gap 1130. In some embodiments, dielectric material 1145 can also be deposited by depositing a quantity of liquid and/or slurry comprising dielectric material in gap 1130 on surface 1107. This quantity of liquid/slurry comprising dielectric material can be deposited by printing the liquid/slurry in gap 1130 on surface 1107. In embodiments where dielectric material is printed, the dielectric material comprising liquid/slurry can be in a liquid/slurry state in which it is transferred and/or printed onto surface 1107. Dielectric material 1145 can be printed using the techniques described above with respect to first quantity of medium 1110 and second quantity of medium 1115.

While dielectric material 1145 is shown as having a granular shape (e.g., a flat top and curved sides), it is contemplated that dielectric material 1145 may have any other suitable shape. For example, dielectric material 1145 may have a convex shape if dielectric material 1145 has a large wetting angle with first quantity of medium 1110 and/or second quantity of medium 1115 (i.e., if the dielectric material does not readily wet both the first quantity of medium and the second quantity of medium).

Once dielectric material 1145 has been deposited, first quantity of dielectric 1110 and second quantity of dielectric 1115 can be selectively removed from surface 1107. FIG. 11D illustrates semiconductor substrate 1105 with first quantity of dielectric 1110 and second quantity of dielectric 1115 selectively removed. For example, selective wet chemical etching can be used to remove first quantity of dielectric 1110 and second quantity of dielectric 1115, leaving semiconductor substrate 1105 and dielectric material 1145 intact. It is contemplated that any suitable selective removal method can be used, depending on the composition of first quantity of dielectric 1110, second quantity of dielectric 1115, semiconductor substrate 1105, and dielectric material 1145. For example, if first quantity of dielectric 1110 and second quantity of dielectric 1115 comprise silicon dioxide/glass, semiconductor substrate 1105 comprises silicon, and dielectric material 1145 comprises polyimide, a wet chemical etchant (such as hydrofluoric acid or other suitable acid) can be used to selectively remove first quantity of dielectric 1110 and second quantity of dielectric 1115 from surface 1107.

Once the first quantity of dielectric 1110 and the second quantity of dielectric 1115 have been selectively removed, electronic contacts 1150 and 1155 can be deposited on first and second portions 1120 and 1125 of surface 1107 (labeled in FIG. 11 a ). Furthermore, electronic contact 1160 can be deposited on dielectric material 1145. FIG. 11 e illustrates semiconductor substrate 1105 after the deposition of electronic contacts 1150, 1155, and 1160. While FIG. 11 e illustrates electronic contact 1150 as covering the entire first portion 1120 and electronic contact 1155 as covering the entire second portion 1125, it is contemplated that electronic contact 1150 may partially cover first portion 1120 and/or electronic contact 1155 may partially cover second portion 1125. Electronic contact 1160 is deposited such that it does not make electronic contact with electronic contacts 1150 and 1155.

The electronic contacts 1150, 1155, 1160 may be printed using the techniques described above with respect to the first quantity of media 1110 and the second quantity of media 1115, or formed using any other suitable technique. One or more of the electronic contacts 1150, 1155, 1160 may include metal, metal particles, or any other suitable conductive material.

The structure shown in FIG11e can form a field effect transistor in which electronic contact 1150 serves as a drain contact (labeled "D" in FIG11e), electronic contact 1155 serves as a source contact (labeled "S" in FIG11e), electronic contact 1160 serves as a gate contact, and dielectric material 1145 serves as a gate barrier. The conductive channel of the transistor can include the region between doped regions 1135 and 1140 within semiconductor substrate 1105.

Field effect transistors (FETs) fabricated by method 1110 and other methods discussed below may have advantages over FETs and thin film transistors (TFTs) fabricated by photolithography. With respect to FETs fabricated by photolithography, conventional lithography may be very expensive, whereas method 1110 (and other methods discussed below) may be performed inexpensively using a material printer (e.g., a desktop inkjet printer) and a heating furnace. With respect to TFTs, their fabrication may be limited by a low thermal budget (because excessive heat may damage their thin film components), and the TFTs themselves may have limited performance (e.g., relatively low electron mobility) due to the potentially poor quality of the thin layers that form the FETs. In contrast, FETs fabricated by method 1100 (and other methods described below) may have a higher thermal budget because: 1) there are no thin films susceptible to damage from high temperatures, and 2) the semiconductor substrate 1105 may comprise a high-quality crystalline semiconductor, which may have high electron mobility and may be less sensitive to high temperatures than the thin films of the TFTs.

Typically, if the semiconductor substrate (which is used to form the conductive channel between the source and drain electrodes) of electronic devices (e.g., FETs) is printed, these devices may have limited performance due to the low electron mobility of the semiconductor material that can typically be achieved through printing. In contrast, in method 1100 (and other methods described below), the semiconductor substrate 1105 (used to form the conductive channel) does not have to be printed, but can instead be a high-quality, crystalline semiconductor with relatively high electron mobility. In this way, method 1100 combines the low cost advantages of printed electronics with the high performance (e.g., high electron mobility) and high thermal budget that can be achieved by using a high-quality, crystalline semiconductor substrate on which other components can be printed.

Semiconductor substrate 1105 may include any semiconductor material suitable for forming electronic devices. In some embodiments, semiconductor substrate 1105 may include planarized semiconductor particles fixed to another substrate, such as planarized spheres 56 shown in FIG. 5 b . Other examples of semiconductor substrate 1105 may include, but are not limited to, planarized spheres 16 shown in FIG. 3 and FIG. 4 .

In some embodiments, the semiconductor substrate 1105 may include planarized islands of semiconductor material formed in situ on another (e.g., non-semiconductor) substrate by heating a granular/powdered semiconductor precursor deposited on the other substrate. The heating may melt and fuse the particles to form a molten ball. Cooling the ball may cause the molten ball to solidify and crystallize to form crystalline islands of semiconductor material fixed to the other substrate. This method of forming semiconductor islands is described in U.S. Patent No. 9,396,932 and also in U.S. Patent Application No. 15/184,429, both of which are incorporated herein by reference in their entirety. Upon planarization, these semiconductor islands may serve as the semiconductor substrate 1105.

In some cases, the in-situ formation of semiconductor islands can produce disk-shaped semiconductor islands as described in U.S. Patent Application No. 15/184,429. Non-limiting examples of these situations include heating a silicon precursor (powder or flakes) to a temperature above the melting point of silicon (e.g., 1500° C.) on an alumina substrate under oxygen conditions (either in the atmosphere or with another material in contact with the molten ball). Under these conditions, a disk/layer comprising silicon can be formed between the crystalline silicon island and the alumina substrate, and the crystalline silicon island can be disk-shaped. Such a disk-shaped silicon island can also be used (optionally after polishing and/or planarization) as the semiconductor substrate 1105.

Surface 1107 may comprise a flat surface. In embodiments where semiconductor substrate 1105 comprises planarized semiconductor particles, surface 1107 may comprise a flat surface formed at a planarized cross-section of the planarized semiconductor particles. Furthermore, while Figures 11a-e illustrate surface 1107 as flat, it is contemplated that surface 1107 may also be curved. For example, surface 1107 may comprise a curved or otherwise non-planar outer surface of a semiconductor particle, or a curved surface of a flexible semiconductor substrate. Semiconductor substrate 1105 may comprise a polycrystalline semiconductor material or a single crystalline semiconductor material, including but not limited to silicon. Prior to performing the steps of method 1100, semiconductor substrate 1105 may be pre-doped.

In some embodiments, semiconductor substrate 1105 may include a semiconductor wafer, or other suitable polycrystalline or single crystalline semiconductor substrate, in addition to semiconductor particles that are formed separately from and then affixed to another substrate.

In some embodiments, a gate contact (formed by electronic contact 1160) can be deposited after dielectric material 1145 is deposited and before the selective removal of first quantity of dielectric 1110 and second quantity of dielectric 1115. In some embodiments, electronic contact 1160 is selected to be unaffected by and/or not affected by the selective removal method used to selectively remove first quantity of dielectric 1110 and second quantity of dielectric 1115.

In some embodiments, a barrier island can be deposited in the gap on the surface prior to depositing the first quantity of dielectric and the second quantity of dielectric. The barrier island can help control the length of the gap, which is determined by (among other factors) the distance between the first quantity of dielectric and the second quantity of dielectric. Because the length of the gap (among other factors) determines the length of the conductive channel of the FET within the semiconductor substrate, controlling the length of the gap can help control the length of the conductive channel and the performance characteristics of the FET.

In some embodiments, the length of the gap (i.e., the distance between the first quantity of medium and the second quantity of medium) may be in a range of approximately 0.1 μm to approximately 100 μm. In other embodiments, the length of the gap (i.e., the distance between the first quantity of medium and the second quantity of medium) may be in a range of approximately 0.1 μm to approximately 10 μm. In still other embodiments, the length of the gap (i.e., the distance between the first quantity of medium and the second quantity of medium) may be in a range of approximately 0.1 μm to approximately 5 μm.

Figures 12a-f illustrate steps in a method 1200 for forming an electronic device (e.g., a FET) using such a barrier island. Figure 12a shows a barrier island 1205 deposited in a gap 1130 on a surface 1107. The barrier island 1205 can be made of any suitable material that can form a barrier to the first quantity of dielectrics 1110 and the second quantity of dielectrics 1115, and can be selectively removed from the substrate 1105, as discussed in more detail below. In some embodiments, the barrier island 1205 can be deposited as a liquid and/or slurry. The liquid/slurry comprising the barrier material (for forming the barrier island) can include an organic material such as polyimide, plastic, or any other suitable material. The liquid/slurry comprising the barrier material can be printed onto the semiconductor substrate 1105 using the same method described above for printing the first quantity of dielectrics 1110 and the second quantity of dielectrics 1115.

While one or more of the first quantity of dielectric, the second quantity of dielectric, the dielectric material, the barrier islands, and the electronic contacts may be deposited using printing techniques, it is contemplated that two or more different printing techniques may be used to print these components.

12 b , a first quantity of dielectric 1110 and a second quantity of dielectric 1115 may be deposited on first and second portions 1120 and 1125, respectively, of surface 1107. As discussed above, barrier island 1205 may act as a barrier to prevent intrusion (e.g., by flowing or propagating) of first and second quantities of dielectric 1110, 1115 onto gap 1130.

Next, semiconductor substrate 1105, first quantity of dielectric 1110, second quantity of dielectric 1115, and barrier island 1205 may be heated to diffuse at least some of the dopants from first quantity of dielectric 1110 and second quantity of dielectric 1115 into surface 1107, thereby forming doped regions 1135 and 1140, respectively, as shown in FIG12c. Heating may also selectively remove (e.g., burn out) barrier island 1205, thereby clearing gap 1130 on surface 1107 for subsequent deposition of dielectric material 1245, as shown in FIG12d. In some embodiments, in addition to heating, barrier island 1205 may be selectively removed using wet chemical etching or other selective removal methods.

Dielectric material 1245 may have a composition and be deposited in a similar manner to dielectric material 1145. Dielectric material 1245 may have a small wetting angle with first quantity of dielectric 1110 and second quantity of dielectric 1115. Dielectric material 1245 may wet first quantity of dielectric 1110 and second quantity of dielectric 1115 at a wetting angle of less than approximately 90°. In other words, dielectric material 1245 may readily wet first quantity of dielectric 1110 and second quantity of dielectric 1115. This may subsequently determine the shape of dielectric material 1245, i.e., having a concave top and curved sides, as shown in Figures 12d-f.

After depositing dielectric material 1245, the steps of method 1200 depicted in Figures 12d, 12e, and 12f are generally similar to the steps of method 1100 shown in Figures 11c, 11d, and 11e, with one difference being that the shape of electronic contact 1260 is different from that of electronic contact 1160. The shape of electronic contact 1260 is determined by the radius of curvature of the top surface of dielectric material 1245. In embodiments where electronic contact 1260 is deposited and/or printed as a liquid, the concave top of dielectric material 1245 gathers and/or directs the electronic contact away from electronic contacts 1150 and 1155. This can help prevent any electrical shorting between electronic contact 1260 and electronic contacts 1150 and 1155, respectively.

Although dielectric material 1145 is shown in FIG. 11 as having a different shape than dielectric material 1245 in FIG. 12 , it is contemplated that the dielectric material in one or both of methods 1100 and 1200 may be shaped similarly to one of dielectric material 1145 and dielectric material 1245 .

In some embodiments, barrier islands 1205 may comprise the same material as dielectric material 1245, in which case barrier islands 1205 are not selectively removed but remain on surface 1107 throughout the steps of method 1200. However, in these embodiments, barrier islands 1205 may not have the same shape as dielectric material 1245 because barrier islands 1205 should have been deposited before first quantity of dielectric 1110 and second quantity of dielectric 1115 are deposited.

In some embodiments, the first and second quantities of the liquid medium may undergo a volume reduction after being deposited on the surface of the semiconductor substrate. The volume reduction may be due to various factors, including, but not limited to, evaporation of some or all volatile components of the liquid medium during an "annealing" step. Figures 13a-g illustrate steps in a method 1300 for forming an electronic device that utilizes this volume reduction.

First, as shown in FIG13a, barrier islands 1205 are deposited on surface 1107. This step can be similar to the first step in method 1200 shown in FIG12a. Next, as shown in FIG13b, an initial amount of liquid medium (including a dopant) 1305 is deposited on surface 1107 to cover first portion 1120 and second portion 1125 of surface 1107, as well as barrier islands 1205, which in turn cover gap 1130. As discussed above, barrier islands 1205 can be deposited in gap 1130 between first portion 1120 and second portion 1125. The volume of initial amount of medium 1305 is greater than the combined volume of first amount of medium 1110 and second amount of medium 1115.

During the annealing step, the volume of the initial quantity of dielectric 1305 will decrease, as discussed above. The annealing and accompanying volume reduction can be due to preheating, or any other step that can result in a volume reduction of the initial quantity of dielectric 1305 due to at least partial loss of volatile components of the liquid dielectric. FIG13 c shows that after the volume reduction of the initial quantity of dielectric 1305 during the annealing, the previously covered barrier islands 1205 can be exposed, and the initial quantity of dielectric 1305 can form a smaller first quantity of dielectric 1110 and a second quantity of dielectric 1115. While FIG13 c shows the first quantity of dielectric 1110 and the second quantity of dielectric 1115 having the same shape and size, it is contemplated that the first quantity of dielectric and the second quantity of dielectric formed as a result of the annealing can have different shapes and sizes from each other. Furthermore, while the first quantity of medium 1110 and the second quantity of medium 1115 in Figures 13c-e are depicted as having similar shapes and sizes to the corresponding first quantity of medium and second quantity of medium in Figures 11a-c and Figures 12b-d, it is contemplated that the first quantity of medium and second quantity of medium obtained by reducing the volume of the initial quantity of medium 1305 (in method 1300) may have shapes and/or sizes that differ from the first quantity of medium and second quantity of medium deposited on the semiconductor substrate 1105 in method 1100 (Figure 11) and method 1200 (Figure 12).

The last five steps of the method 1300 shown in Figures 13c-13g are similar to the last five steps of the method 1200 shown in Figures 12b-f and will not be described in detail here.

In some embodiments, the barrier islands can be formed by depositing a layer of photosensitive material on the surface of the semiconductor substrate, exposing the region of the photosensitive material layer covering the gap to light that modifies the photosensitive material, and selectively removing the unexposed region of the photosensitive material from the surface to thereby form a barrier island comprising the photosensitive material modified by light. The photosensitive material may include a photoresist, including but not limited to a negative photoresist such as Shipley BPR ^™ -100 photoresist. Exposing the photosensitive material to light can be implemented without expensive and/or complex photolithography equipment. For example, exposure can be implemented using a light source such as a UV LED or laser attached to the print head of an inkjet printer.

Figures 14a-g illustrate steps in method 1400 in which barrier islands are formed by exposing a layer of photosensitive material and then selectively removing unexposed areas. Figure 14a shows a layer of photosensitive material 1405 deposited on substrate 1105. Photosensitive material 1405 can be spin-coated or deposited on a semiconductor substrate using any other suitable technique. Photosensitive material 1405 can include photoresist, or any other suitable material, including but not limited to a negative photoresist such as Shipley BPR ^™ -100 photoresist.

Then, the area of the photosensitive material covering the gap 1130 (marked in Figure 14b) can be exposed to light configured to modify the photosensitive material. After this exposure and modification, the unexposed portion of the photosensitive material 1405 layer can be selectively removed to form a barrier island 1410 comprising the photosensitive material modified by the light, as shown in Figure 14b. By utilizing a light source with a micron or submicron spot size (such as a UV laser), it is possible to directly write small features (such as barrier islands 1410). The selective removal step can remove the unexposed area of the photosensitive material 1405 layer, leaving the exposed portion of the photosensitive material and the intact semiconductor substrate. The selective removal can include wet chemical etching or any other suitable selective removal method.

Once barrier islands 1410 have been formed, a first quantity of dielectric 1110 can be deposited on first portion 1120 of surface 1107 and a second quantity of dielectric 1115 can be deposited on second portion 1125, as shown in FIG14c. The last five steps of method 1400 shown in FIG14c-g are similar to the last five steps of method 1200 shown in FIG12b-f and will not be described in detail here.

Methods 1100, 1200, 1300, and 1400 can be used to form and/or manufacture gate-controllable electronic components, including but not limited to transistors such as FETs. As discussed above, these methods can be performed on a semiconductor substrate, which is a planarized semiconductor particle that is formed separately from another substrate and then immovably fixed to the other substrate. For example, transistors 55a, 55b shown in Figures 5c, 7, 8, and 10 can be formed using one or more of methods 1100, 1200, 1300, and 1400.

The above-described embodiments of the present invention are intended to be examples of the present invention and variations and modifications may be made thereto by those skilled in the art without departing from the scope of the present invention, which is defined solely by the scope of the appended claims.

Claims (22)

1. A method for forming a plurality of electronic devices on a substrate, the method comprising: Provide semiconductor particles formed separately from the substrate; The semiconductor particle is placed at a predetermined position on the substrate; The semiconductor particles are immovably fixed to the predetermined positions on the substrate; After the semiconductor substrate is immovably fixed, a portion of each of the semiconductor particles is removed to expose a cross-section of the plurality of semiconductor particles, wherein the cross-section is a flat surface; and One or more gateable electronic components are provided directly above or below each flat surface. For each flat surface, the one or more gateable electronic components include: A first amount of a first liquid medium comprising a dopant is deposited on a first portion of the flat surface, and a second amount of the first liquid medium is deposited on a second portion of the flat surface, the first amount of medium and the second amount of medium being separated by a gap; Heating the first quantity of media, the second quantity of media, and the corresponding semiconductor particles, wherein the heating is configured to cause at least some of the dopants to diffuse from the first liquid medium into the flat surface; Dielectric material is deposited in the gap on the flat surface; The first quantity of media and the second quantity of media are selectively removed from the flat surface; Electron contacts are deposited on each of the first and second portions; and Additional electronic contacts are deposited on the dielectric material. 2. A method for forming an electronic device on a substrate, the method comprising: Provide semiconductor particles formed separately from the substrate; The semiconductor particles are fixed to the substrate in a non-movable manner; After being immovably fixed, a first amount of a first liquid medium comprising a dopant is deposited on a first portion of the surface of the semiconductor particle, and a second amount of the first liquid medium is deposited on a second portion of the surface, the first amount of medium and the second amount of medium being separated by a gap; Heating the first quantity of media, the second quantity of media, and the semiconductor particles, wherein the heating is configured to cause at least some of the dopants to diffuse from the first liquid medium into the surface; Dielectric material is deposited in the gaps on the surface; Selectively remove the first quantity of medium and the second quantity of medium from the surface; Electron contacts are deposited on each of the first and second portions; and Additional electronic contacts are deposited on the dielectric material; The method further includes: Before depositing the first and second quantities of medium, barrier islands are formed in the gaps on the surface; and The barrier islands are selectively removed from the surface before the dielectric material is deposited. 3. The method of claim 2, wherein forming a potential barrier island comprises: A third quantity of a second liquid medium, comprising a barrier material, is deposited in the gap on the surface. 4. The method of claim 2, wherein forming a potential barrier island comprises: A photosensitive material layer is deposited on the surface; The region of the photosensitive material covering the gap is exposed to light configured to modify the photosensitive material; and Unexposed areas of the photosensitive material layer are selectively removed from the surface to form barrier islands comprising the photosensitive material modified by the light. 5. The method of claim 2, wherein the deposited dielectric material comprises: A fourth quantity of a third liquid medium comprising the dielectric material is deposited in the gap on the surface. 6. The method of claim 5, wherein the fourth quantity of media humidifies the first quantity of media and the second quantity of media at a wetting angle of less than approximately 90 ^° . 7. The method of claim 2, wherein the heating further selectively removes the barrier islands from the surface. 8. The method of claim 2, wherein depositing the first quantity of medium and the second quantity of medium comprises: An initial quantity of the first liquid medium is deposited on the surface, the initial quantity of medium covering a first portion of the surface, a second portion of the surface, and the barrier islands disposed between the first and second portions; and The initial quantity of medium is heated to reduce the volume of the initial quantity of medium by at least partially evaporating one or more components of the first liquid medium, thereby exposing the barrier islands and forming the first quantity of medium and the second quantity of medium separated from each other by the barrier islands. 9. The method of claim 2, wherein the surface comprises a flat surface. 10. The method of claim 9, wherein the flat surface comprises the planarized surface of the semiconductor particles. 11. The method of claim 2, wherein the first quantity of media and the second quantity of media are separated by a gap in the range of about 0.1 μm to about 100 μm. 12. The method of claim 2, wherein printing is used for one or more of the following: The first quantity of deposited medium; A second quantity of medium was deposited; Deposited dielectric materials; Electron contacts are deposited on each of the first and second portions; and Deposit additional electronic contacts. 13. The method of claim 12, wherein the printing comprises one or more of the following: Screen printing; Aniline printing; Gravure printing; printing; Offset printing; and Inkjet printing. 14. A method for forming an electronic device, the method comprising: A semiconductor substrate is provided having a surface, the surface comprising a first portion and a second portion, the first portion and the second portion being spaced apart by a gap; Barrier islands are formed in the gaps on the surface; A first amount of a first liquid medium comprising a dopant is deposited on a first portion of the surface, and a second amount of the first liquid medium is deposited on a second portion of the surface, the first amount of medium and the second amount of medium being separated by the barrier islands; The first quantity of media, the second quantity of media, and the semiconductor substrate are heated, the heating being configured to cause at least some of the dopants to diffuse from the first liquid medium into the surface; The barrier islands are selectively removed from the surface; Dielectric material is deposited in the gaps on the surface; Selectively remove the first quantity of medium and the second quantity of medium from the surface; Electron contacts are deposited on each of the first and second portions; and Additional electronic contacts are deposited on the dielectric material. 15. The method of claim 14, wherein forming the barrier island comprises: A third quantity of a second liquid medium, comprising a barrier material, is deposited in the gap on the surface. 16. The method of claim 14, wherein forming the barrier island comprises: A photosensitive material layer is deposited on the surface; The region of the photosensitive material covering the gap is exposed to light configured to modify the photosensitive material; and Unexposed areas of the photosensitive material layer are selectively removed from the surface to form the barrier island comprising the photosensitive material modified by the light. 17. The method of claim 14, wherein the deposited dielectric material comprises: A fourth quantity of a third liquid medium comprising the dielectric material is deposited in the gap on the surface. 18. The method of claim 17, wherein the fourth quantity of media humidifies the first quantity of media and the second quantity of media at a wetting angle of less than about 90 ^° . 19. The method of claim 14, wherein the heating further selectively removes the barrier islands from the surface. 20. The method of claim 14, wherein depositing the first quantity of medium and the second quantity of medium comprises: An initial quantity of the first liquid medium is deposited on the surface, the initial quantity of medium covering a first portion of the surface, a second portion of the surface, and the barrier islands disposed between the first and second portions; and The initial quantity of medium is heated to reduce the volume of the initial quantity of medium by at least partially evaporating one or more components of the first liquid medium, thereby exposing the barrier islands and forming the first quantity of medium and the second quantity of medium separated from each other by the barrier islands. 21. The method of claim 14, wherein the surface comprises a planarized surface of the semiconductor substrate. 22. The method of claim 14, wherein printing is used for one or more of the following: The first quantity of deposited medium; A second quantity of medium was deposited; Deposited dielectric materials; Electron contacts are deposited on each of the first and second portions; and Deposit additional electronic contacts.