HK1119793A - Efficient charge pump for a wide range of supply voltages - Google Patents

Abstract

A voltage booster and regulator (303) usable with Dickson-type charge pump device is specifically- adapted to maintain efficiency with both high and low supply voltages. For high voltage supplies (e.g., 2.6 volts or more), the charge pump (300) reduces overall power consumption resulting in a more efficient design. For low voltage applications (e.g., for supply voltages less than 2.6 volts), the charge pump uses a booster circuit (303) to increase a clock input potential beyond the supply voltage available to a typical Dickson array. Further, the charge pump (300) avoids inherent diode voltage drops in a typical Dickson array.

Description

Efficient charge pump for wide supply voltage range

Technical Field

The invention relates to a Dickson charge pump. More particularly, the present invention relates to a Dickson charge pump that can operate with either a high supply voltage or a low supply voltage.

Background

Non-volatile digital data memory devices are currently being widely utilized. Various consumer products, such as Personal Data Assistants (PDAs), cellular telephones, and electronic notebooks, require non-volatile memory devices to store information in large capacity compact columns.

A drawback of non-volatile memory devices is the high power consumption rate associated with their operation. Power consumption rates are clearly of great interest for portable products such as the devices listed above, as such devices are typically battery powered.

Most of the power consumed to operate such memories goes to charge pump circuitry that is arranged to raise the voltage value above a power supply level (typically a battery voltage level) to further power a portion of the circuitry integrated in the memory device. This power consumption is due to the high voltages required to perform basic operations such as program and erase operations in the non-volatile memory device. In the case of using a low voltage power supply circuit, the read operation and the program and erase voltages are higher than the power supply voltage.

Therefore, it is very important to provide charge pump circuits that operate with as small a power drain as possible, and the current trend of increasingly lower supply voltages for integrated circuits can only increase this importance.

Referring to fig. 1, a circuit diagram of a typical four-stage Dickson charge pump device includes a series-connected diode D₁To D₅Wherein a coupling capacitor C₁To C₄Each connected to the diode D₁To D₅A node in between. The Dickson charge pump circuit further includes an output capacitor C_L. The output capacitor C_LConnected in parallel with the external load 103. Input clock pulse CLK_AAnd CLK_BHave opposite phases with respect to each other. Clock pulse CLK_AAnd CLK_BInput to the clock driver 101. The clock driver 101 has a power supply voltage V_DD(not shown). Clock pulse CLK_AAnd CLK_BAre denoted as phi 1 and phi 2, respectively. Feeding the clock pulse phase phi 1 to the capacitor C₁And C₃And the clock pulse phase phi 2 is fed into the capacitor C₂And C₄。

In which the current I is constant_outFor charge pump arrangements in steady state flow out through external load 103The input current being from the input voltage V_DDAnd the sum of the current provided from the clock driver. These currents are as described below, regardless of charging or discharging currents to or from any stray circuit capacitances. During the clock period where φ 1 is "high" (i.e., logic "1") and φ 2 is "low" (i.e., logic "0"), the average current is 2' (I)_out) Flowing through each of a plurality of paths in the direction depicted in the figure by solid arrows.

During subsequent clock cycles where φ 1 is "low" and φ 2 is "high", the average current is 2' (I)_out) Flowing through each of the plurality of paths in a direction depicted in the figure as dashed arrows. The average current of each of these aforementioned currents over the entire clock cycle is I_out. The increased voltage from the charge pump device at steady state can be expressed by equation (1),

V_out＝V_in-V_d+n(V_φ′-V₁-V_d) (1)

wherein V_φ′Refers to the voltage amplitude induced at each connection node via the coupling capacitor by the clock pulse variation; v₁Is shown due to the output current I_outThe resulting power drop; v_inRepresents the input voltage, which is normally set to V when boosted positively_DDAnd is set to 0 volt at negative boost; v_dRefers to the forward biased diode voltage; and n represents the number of pump stages.

In addition, V₁And V_φ′Is expressed by the following equation

Wherein C is₁Represents a capacitor C₁To C₄A clock coupling capacitance of one of; c_sIs the stray capacitance at each connection node; v_φIs the amplitude of the clock pulse; f is the frequency of the clock pulses; and T is the clock period of the clock pulse. The power efficiency η of the charge pump device is calculated by the following equation, regardless of whether the current is charged from the clock driver to the stray capacitor or discharged from the stray capacitor to the clock driver and assuming V_in＝V_DD，

Thus, the charge pump device raises the voltage by successively transferring the electron charges to the next stage using the diode as the charge transfer device. However, MOS transistors are easier to implement in semiconductor integrated circuits than PN junction diodes due to fabrication compatibility during fabrication.

Thus, a MOS transistor (as indicated in FIG. 1B) replaces the diode D of FIG. 1A₁To D₅As a charge transfer device. V in equation (1) by using MOS transistors_dBy V_thIn stead of, wherein V_thRepresenting the threshold voltage of the MOS transistor.

Figure 2 shows a simple ring oscillator that may be used to drive any of the Dickson charge pump circuits shown in figures 1A and 1B. The above-mentionedThe ring oscillator is formed by a plurality of inverter elements 203 connected in series₁、203₂、……、203₅The components are as follows. The input nand gate 201 provides a means for disabling the oscillator when a low voltage signal is present at a first input (labeled "clk en") of the nand gate 201. Each oscillator output generates a signal clk andit is stable when the signal at clk _ en is low (i.e., 1, 0). When enabled, the input nand gate 201 inverts the signal from the second input of the nand gate 201. The signal is then passed through an inverter element 203₁、203₂、……、203₅Propagates back to the second input of nand gate 201. This process continues until the enable signal at clk _ en goes back low. The amount of time it takes to propagate the signal back to the second input is taken by inverter element 203₁、203₂、……、203₅The delay of each of them is determined. The inverter delay depends on the supply voltage V_DD(ii) a Supply voltage V_DDDetermination may be applied to inverter element 203₁、203₂、……、203₅The maximum gate-source voltage of the transistors within each of them. Gate-source voltage determination for inverter element 203₁、203₂、……、203₅Driven by the current of each, determining the propagation delay. Will be given by₁The presented signal is provided to a first clock driver portion 204, said first clock driver portion 204 being formed by a nand-gate 205, a first inverter 207₁And a second inverter 207₂In which the elements are connected to each other in series. The first clock driver portion 204 generates the output "clk". Will have f₀Is supplied to a second clock driving section 208, the second clock driving section 208 is composed of a nand gate 209, a first inverter 211₁And a second inverter 211₂In which the elements are connected to each other in series. The second clock driver portion 208 produces an outputOutput signals clk andwith a phase difference of 180 deg. with respect to each other.

Disclosure of Invention

Exemplary voltage boosters and regulators that may be used with Dickson-type charge pump devices are particularly well suited to maintaining efficiency with both high and low supply voltages. For high voltage power supplies (e.g., 2.6 volts or more), the charge pump reduces overall power consumption, resulting in a more efficient design. For low voltage applications (e.g., for supply voltages below 2.6 volts), the charge pump uses a booster circuit to increase the clock input potential above the supply voltage available to a typical Dickson array. In addition, the charge pump avoids the inherent diode voltage drop in a typical Dickson array.

In an exemplary embodiment, a charge pump apparatus includes a plurality of switching devices, a voltage booster, and a voltage regulation device. The plurality of switching devices are configured to connect or disconnect one or more charge storage devices to or from a supply voltage source. A voltage booster includes the one or more charge storage devices and is configured along with the plurality of switching devices to provide a voltage output that is higher than both a threshold voltage of each of the plurality of switching devices and the supply voltage source. The voltage output is adapted to be coupled to an input of a charge pump circuit (e.g., a Dickson-type charge pump). The voltage regulation device is coupled to receive a supply voltage source as an input and is configured to be enabled when the supply voltage source is low and disabled when the supply voltage source is high.

Drawings

Fig. 1A is a prior art Dickson charge pump.

Fig. 1B is a cross-sectional view showing a prior art charge pump device implemented in a CMOS structure.

Fig. 2 is a simple ring oscillator circuit that may be used to drive a charge pump circuit.

Fig. 3 is an exemplary block diagram of the charge pump circuit of the present invention.

Fig. 4 is an exemplary regulated charge pump and booster circuit stage of the charge pump of fig. 3.

Fig. 5A is an exemplary driver circuit of the regulated charge pump and booster circuit stage of fig. 4.

Fig. 5B is a functional representation of the driver circuit of fig. 5A.

Fig. 6 is an exemplary pump stage of the charge pump circuit of fig. 3.

Detailed Description

The block diagram of fig. 3 provides an overview of the various portions of the charge pump circuit 300 of the present invention. The charge pump circuit 300 includes an oscillator circuit 301, a regulated charge pump and booster circuit 303, and a plurality of pump stages 305₁、305₂。

The oscillator circuit 301 receives an enable signal pump _ on (which is fed through an inverter) and a single output clk signal. Details of oscillator 301 are not discussed, as such circuits are well known in the art. One exemplary oscillator circuit that may be used with the present invention is described in detail in U.S. patent application No. 10/995,458 entitled "oscillator circuit for EEPROM High Voltage Generation," filed on 11/22/2004 (claiming priority of french patent application No. 04/08931 filed on 8/17/2004), which is commonly assigned with the present application to Atmel Corporation, San Jose, CA.

Regulated charge pump and booster circuit 303 slave oscillatorThe oscillator 301 receives as input the clk signal. Supply voltage V at lv _ fuse_DDConnected to regulated charge pump and booster circuit 303 and two clocked output signals out andto multiple pump stages 305₁、305₂A clock and an inverted clock input are provided. The two clocked output signals out andmay or may not be raised, depending on the input supply voltage V_DDThe potential of (2). In general, if the supply voltage V_DDLess than about 2.6 volts, the potential of the output signal will be raised. Details of the regulated charge pump and booster circuit 303 are described below with reference to fig. 4, 5A, and 5B.

Multiple pump stages 305₁、305₂May be implemented as a typical Dickson-type pump stage as described with reference to the CMOS-based Dickson pump stage of fig. 1B. Although only two stages are shown, skilled artisans will recognize that higher output voltages and/or currents may be obtained by combining multiple pump stages in parallel and/or in series.

The regulated charge pump and booster circuit 303 is described in more detail in the exemplary embodiment of fig. 4. Fig. 4 includes a clock inversion circuit 401 and a plurality of driver circuits 403₁、403₂. The clock inversion circuit 401 includes two parallel nand-inverter-nand-inverter series connected strings, each string being connected in parallel to the other. Output c of clock inverting circuit 401₀And c₂Shown in the table of fig. 4 as being complementary to each other for a given input (i.e., "0" or "1"), assuming power is turned on (i.e., pwr _ on ═ 1). Each output c₀、c₂For use in a plurality of driver circuits 403₁、403₂Is input.

Driver circuit 403₁、403₂Each cross-coupled to the other. Drive theDevice circuit 403₁、403₂The main circuit that contains both the control voltage regulation and the booster circuit. Each of the exemplary voltage regulation and booster circuits is described in detail with reference to fig. 5A and 5B.

FIG. 5A includes details of a particular exemplary driver circuit 403, which driver circuit 403 may be used as the driver stage 403 of the regulated charge pump and booster circuit 303 of FIG. 3_iAn output stage of each of the above. First and second large capacitors C₁And C₂Storing input supply voltage V_DD. Stored in a second large capacitor C₂Is passed to the Dickson pump stage 305 via clk _ out tap through PMOS transistor P1_i. clk _ out tap is supply voltage V_DDA boosted version of (a). In certain exemplary embodiments, the first bulk capacitor C₁Having a stored value of 4.5 picofarads, and a second large capacitor C₂With a stored value of 55 picofarads. Details of a general exemplary booster circuit are given below with reference to fig. 5B.

Fig. 5A also includes a voltage regulator portion 501. The voltage regulator portion 501 includes additional circuitry that provides a feedback path, preventing the output voltage at int _ hv _ out from exceeding the absolute maximum voltage rating of the IC transistors. In this embodiment, the voltage regulator portion includes PMOS transistors P connected in series₂、P₃And P₄Gate coupled NMOS transistor N₁And N₂、V_DDPass transistor P₅And a NAND gate I₁. In a particular exemplary embodiment, the absolute maximum voltage rating of the IC transistors is 5.5 volts.

The functional representation of fig. 5B provides a high level of explanation of the booster circuit portion of fig. 5A. In operations involving low supply voltages: during a first clock phase phi 1, switch S₁、S₃And S₅Is turned on (i.e., "closed"), and switch S is turned on₂And S₄Off (i.e., "on"). Switch S₅Pulling the output low. At the same time, the capacitor C is charged to the supply voltage level V_DD. At the second clockDuring phase phi 2, switch S₁、S₃And S₅Is turned off and switch S₂And S₄And (4) switching on. The output voltage now rises to approximately the supply voltage V_DDTwice as much. Thus, the subsequent pump stage 305 sees a voltage at 0 volts and 2' V_DDAlternating voltages between them, thereby making the pump stage 305 more efficient because any diode voltage drop constitutes a much smaller percentage of the total starting supply voltage. For example, assume that the pump stage diode voltage drop is 0.7 volts. For a supply voltage of only 1.2 volts, the percent efficiency due to the potential lost on the diode isHowever, by boosting the voltage before entering the pump stage, the percent efficiency is increasedTherefore, the booster circuit portion produces a significant efficiency increase.

In operations involving high supply voltages: due to the regulating function of the circuit, the switch S₁To S₅Operating in a different manner than in low voltage operation. The regulating circuit measures the voltage output by the circuit. As discussed above with reference to FIG. 5A, the conditioning circuit of an exemplary embodiment includes a PMOS transistor P₂To P₅NMOS transistor N₁And N₂And a NAND logic gate I₁. Referring back to FIG. 5B again, if operating at a high voltage, during clock φ 1, switch S₁、S₃And S₅Is turned on and S₂And S₄And (6) turning off. Charging the capacitor again to a potential level V_DD. Due to the switch S₅The output voltage remains low due to the switch-on. During the second clock phase φ 2, if the measured output voltage remains below about 2.6 volts, then switch S₁And S₅Off, S₂Remains off, S₃Remains on and S₄And (4) switching on. The main difference between this high voltage operation and the low voltage operation described above is that the switch S is constantly off₂And constantly turning on the switch S₃. Thus, the output voltage is no longer raised as in low voltage operation, but the output voltage alternates between 0 volts and about 2.6 volts. Thus, the input voltage of the subsequent Dickson charge pump stage is always 0 volts or about 2.6 volts. Alternatively, the energy transferred to the charge pump stage is limited by the value of the capacitor C. Thus, the drawn supply current is limited, thereby making the pump stage perform well at higher voltages (e.g., a uniform and well-known output voltage with a uniform pulse width).

FIG. 6 includes multiple pump stages 305 connected in series₁、305₂、……、305_nWherein each pump stage 305_iConnected to the clkout signal and complement (i.e., opposite phase) from regulated charge pump and booster circuit 303 (fig. 3)Both signals. In this embodiment, V_DDThe pass transistor 601 is selected to be an "nw" device (with a higher than normal threshold voltage V)_t) Rather than "nws" devices, to avoid current leakage back to the power supply at low supply voltages. The "nw" device is a native (i.e., without threshold implant) high voltage n-channel transistor with a p-well. The "nw" transistor has a higher threshold voltage (approximately 0.22 volts) than the "nws" device, and therefore has lower leakage. The "nws" device is an intrinsic high voltage n-channel transistor in the substrate. The threshold voltage of the "nws" transistor is about-0.09 volts. The skilled artisan will recognize that "nws" devices may be used in place of "nw" devices with minimal performance variation.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, it will be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, a skilled artisan will appreciate that although the booster and demodulator circuits have been described in terms of specific circuits and specific voltage levels, equivalent or similar circuits and voltages may be implemented without departing from the scope of the invention presented herein. In addition, the various devices, such as the capacitors described in connection with the booster circuit, may be any charge storage device, such as a transistor connected to act as a charge storage mechanism, a series of plates coupled with an interleaved dielectric fabricated as part of an integrated circuit, or a comb capacitor fabricated by techniques well known in the semiconductor arts. Other items are described in terms of MOS integrated circuit devices, but those skilled in the art will recognize that other fabrication techniques (such as bipolar or BiCMOS techniques) may be readily employed as well. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (13)

1. A charge pump apparatus, comprising:

a voltage booster having

(i) A voltage input adapted to be coupled to a supply voltage source and a voltage output adapted to be coupled to an input of a charge pump circuit;

(ii) one or more charge storage devices; and

(iii) a plurality of switching devices configurable arranged such that:

a first portion of the plurality of switching devices is turned on and a second portion of the plurality of switching devices is turned off during a first clock phase of low supply voltage operation, at least one of the first portion pulls the level of the voltage output low when the second portion charges the one or more charge storage devices, the first portion is turned off and the second portion is turned on to couple the one or more charged charge storage devices to the voltage output during a second clock phase, the level of the voltage output is about twice the level of the low supply voltage source during the second phase, the level of the voltage output is greater than a threshold voltage of each of the plurality of switching devices.

2. The charge pump apparatus of claim 1, wherein a level of the voltage output is greater than a threshold voltage of each of the plurality of switching devices when the voltage booster is operating.

3. The charge pump apparatus of claim 1, further comprising:

an oscillator stage configured to generate a clock output and an inverted clock output; and a Dickson charge pump having a plurality of stages.

4. The charge pump apparatus of claim 3, wherein the supply voltage source is supplied to the Dickson charge pump through a pass transistor selected to avoid current leakage back to the supply voltage source at low supply voltages.

5. The charge pump apparatus of claim 1, wherein the plurality of switching devices are comprised of MOS transistors.

6. The charge pump apparatus of claim 1, wherein the one or more charge storage devices are comprised of capacitors.

7. A charge pump apparatus, comprising:

a voltage booster having

(i) A voltage input adapted to be coupled to a supply voltage source and a voltage output adapted to be coupled to an input of a charge pump circuit;

(ii) one or more charge storage devices;

(iii) a plurality of switching devices configurable arranged such that:

a first portion of the plurality of switching devices being turned on and a second portion of the plurality of switching devices being turned off during a first clock phase of low supply voltage operation, at least one of the first portion pulling the level of the voltage output low when the second portion charges the one or more charge storage devices, the first portion being turned off and the second portion being turned on to couple the one or more charged charge storage devices to the voltage output during a second clock phase, the level of the voltage output being about twice the level of the low supply voltage source during the second phase, the level of the voltage output being greater than a threshold voltage of each of the plurality of switching devices; and

a voltage regulation device coupled to receive the supply voltage source as an input, the voltage regulation device configured to be enabled when the supply voltage source is low and disabled when the supply voltage source is high.

8. The charge pump apparatus of claim 7, wherein a level of the voltage output is higher than a threshold voltage of each of the plurality of switching devices when the voltage booster is operating.

9. The charge pump apparatus of claim 7, further comprising:

an oscillator stage configured to generate a clock output and an inverted clock output; and a Dickson charge pump having a plurality of stages.

10. The charge pump apparatus of claim 9, wherein the supply voltage source is supplied to the Dickson charge pump through a pass transistor selected to avoid current leakage back to the supply voltage source at low supply voltages.

11. The charge pump apparatus of claim 7, wherein the plurality of switching devices are comprised of MOS transistors.

12. The charge pump apparatus of claim 7, wherein the one or more charge storage devices are comprised of capacitors.

13. The charge pump apparatus of claim 7, wherein the low voltage is less than about 2.6 volts.