HK1115937B - High current semiconductor power device soic package - Google Patents

Abstract

The present invention discloses a high current semiconductor power small form integrated circuit package. The package includes a relatively thick lead frame formed from a single specification material with a thickness greater than 8mil, the lead frame having multiple leads and a first lead frame region comprising a chip soldered to it; A pair of wire bonding areas set on the same plane as the top surface of the chip; Aluminum large-diameter bonding wires that connect the chip to multiple leads; A resin body that seals at least a portion of the chip, bonding wires, and lead frame.

Description

Low profile integrated circuit package for high current semiconductor power devices

Technical Field

The present invention relates to semiconductor devices, and more particularly to high current semiconductor device low profile integrated circuit packages.

Background

Power semiconductor packages have evolved from through-hole to surface mount packages as printed circuit board technology has evolved. Surface mount packages generally include a lead frame on which a semiconductor device is mounted. The semiconductor device and a part of the lead frame are generally sealed with a resin material. In a leaded package, the lead terminals extend outside the resin body and include bonding areas for providing wire bond connections from the semiconductor device to the lead terminals.

Issues of significant concern in semiconductor device packaging include high heat dissipation, low parasitic inductance, low electrical resistance between the semiconductor device and surrounding circuitry, good reliability in terms of thermal cycling and thermal shock/fatigue, and minimal consumption of circuit board space.

Conventional power semiconductor packages include 8 to 32 pin Small Outline Integrated Circuit (SOIC) packages. In high current applications, conventional SOIC packages suffer from poor thermal performance due to the thickness of the lead frame and the package bottom encapsulation. In addition, semiconductor chips are conventionally attached to the leadframe of the SOIC package with a material such as silver paste that has poor thermal properties.

Conventional SOIC packages are further limited in their use in many applications because the terminal pins of the SOIC package do not match the TO 252(DPAK package) land pattern on the printed circuit board. In addition, conventional SOIC packages have lead frames that are easily deformed, resulting in a lower assembly rate and relatively small wire bonding area that limits the number of bonding wires that can be used to reduce package resistance.

Disclosure of Invention

The technical problem TO be solved by the present invention is TO provide a high current semiconductor power device SOIC package that can be used in a variety of high current applications and in many applications TO replace TO 252 devices.

To achieve the above objects, the present invention provides a high current semiconductor SOIC package comprising a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, said lead frame having a plurality of leads and a first leadframe region including a die bonded thereto; a pair of wire bonding regions disposed on the same plane as the top surface of the chip; an aluminum large diameter bonding wire connecting the chip to the plurality of leads; and a resin body encapsulating the chip, the bonding wire, and at least a portion of the lead frame.

As a further improvement of the present invention, a high current semiconductor power device SOIC package housing an electronic device with flattened leads further includes a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame including a plurality of leads and a lead frame region having an electronic device soldered thereto; a pair of wire bonding regions disposed on the same plane as a top surface of the electronic device; bonding wires of aluminum having a thickness of up to 20 mils connecting the electronic device to the plurality of leads; and a resin body encapsulating the electronic device, the bonding wire, and at least a portion of the lead frame.

The present invention generally provides a high current semiconductor power device SOIC package having a leadframe formed from a single gauge material having a thickness of 8 to 10 mils greater than conventional. Advantageously, a thicker lead frame facilitates bonding of large diameter aluminum bonding wires. The use of aluminum bonding wires significantly reduces package resistance over conventional gold wire configurations. The bonding wire may have a diameter of up to 20 mils. The thicker leadframe material further provides improved package thermal performance by promoting heat flow laterally out of the drain leads. This effect can be obtained even in the case where the bottom of the lead frame region is exposed. Further, the source bonding region and the gate bonding region may be disposed at substantially the same height as the chip height. In this manner, a short length of bonding wire may be used, thereby reducing resistance and inductance.

The high current semiconductor power device SOIC package further includes outwardly extending drain, source and gate leads that can match the TO 252 bond pad pattern. Therefore, the high current semiconductor power device SOIC package of the present invention can be used to replace DPAK packages in many high current applications.

Drawings

FIG. 1 is a top view of an embodiment of a high current semiconductor power device SOIC package according to the present invention;

FIG. 1A is a cross-sectional view of the high current semiconductor power device SOIC package of FIG. 1 according to the present invention;

FIG. 1B is a bottom view of the high current semiconductor power device SOIC package of FIG. 1 in accordance with the present invention;

FIG. 2 is a top view of a matrix lead frame according to the present invention;

FIG. 2A is an enlarged view of a lead frame and its support according to the present invention;

FIG. 3 is a perspective view of a high current semiconductor power device SOIC package surface mounted TO a TO 252 land pattern in accordance with the present invention; and

fig. 4 is a perspective view of a DPAK device surface mounted TO a TO 252 land pattern.

Detailed Description

Best mode for carrying out the invention will be described in detail with reference to fig. 1 to 4. This description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention, since the scope of the invention is best defined by the appended claims.

The present invention generally provides a high current semiconductor power device SOIC package having a leadframe formed from a single gauge material having a thickness of 8 to 10 mils greater than conventional. Advantageously, a thicker lead frame facilitates bonding of large diameter aluminum bonding wires. The use of aluminum bonding wires significantly reduces package resistance over conventional gold wire configurations. The bonding wire may have a diameter of up to 20 mils. The thicker leadframe material further provides improved package thermal performance by promoting heat flow laterally out of the drain leads. This effect can be obtained even in the case where the bottom of the lead frame region is exposed. Further, the source bonding region and the gate bonding region may be disposed at substantially the same height as the chip height. In this manner, a short length of bonding wire may be used, thereby reducing resistance and inductance.

The high current semiconductor power device SOIC package further includes outwardly extending drain, source and gate leads that can match the TO 252 bond pad pattern. Therefore, the high current semiconductor power device SOIC package of the present invention can be used to replace DPAK packages in many high current applications.

Referring to fig. 1, 1A and 1B, a high current semiconductor power device SOIC package is shown generally at 100. The thicker single gauge material lead frame 130 includes a lead frame region 152 to which the chip 101 is connected. The chip 101 is preferably soldered to the leadframe region 152 by a solder layer 170 to facilitate the use of aluminum large diameter bonding wires. A portion of the lead frame 130 may be molded in the resin body 108.

The lead frame 130 includes a source lead 116, a gate lead 112, and a drain lead 126. The source lead 116 may be melted and extend out of the resin body 108. The outer portion of source lead 116 further includes a laterally extending portion 116a and first and second portions 116b and 116c, which first and second portions 116b and 116c extend perpendicularly from laterally extending portion 116a in spaced relation to each other. The inner source bonding region 118 is connected to the source contact of the chip by a bonding wire 110. The inner source bonding region 118 extends substantially the entire length of the fused source lead 116 to provide the maximum number of bonding wires 110 to reduce on-resistance and inductance. The drain lead 126 may be connected to the leadframe region 152 and include a laterally extending portion 126a and first and second portions 126b and 126c, the first and second portions 126b and 126c extending perpendicularly from the laterally extending portion 126a in spaced relation to one another. The gate lead 112 may be connected to a gate contact region 120, which gate contact region 120 may in turn be connected to a gate region 127 by a bonding wire 106. The gate lead 112 further includes a lateral extension portion 112a and a portion 112b vertically extending from the lateral extension portion 112 a. The source and drain locking holes 114 and 124 may be formed in the source and drain leads 116 and 126, respectively. A locking notch 128 is formed in the drain lead 126.

With specific reference to fig. 1A, the lead frame 130 is formed of a single gauge material having a thickness of greater than a conventional 8 to 10 mil. Advantageously, a thicker lead frame 130 facilitates bonding of larger diameter bonding wires 110 and 106 of aluminum and/or a larger number of such bonding wires. The use of aluminum large diameter bonding wires significantly reduces package inductance and resistance over conventional gold wire configurations. In addition, the use of aluminum large diameter bonding wires enables the package 100 to be used for high current applications. The bonding wires 110 and 106 may have diameters of up to 20 mils. The thicker leadframe material further provides improved package thermal performance by promoting heat flow laterally out of the drain leads.

With continued reference to fig. 1A, source bonding region 118 and gate bonding region 120 (not shown) are disposed substantially on the same plane as top surface 102 of chip 101. In this manner, the short length of bonding wires 110 and 106 used can reduce resistance and inductance. The bottom 180 of the lead frame 130 is exposed at the bottom of the package 100.

The lead frame 130 further includes a pair of side chip bars 190. The side chip bar 190 serves to reinforce the mechanical properties of the matrix lead frame 200 (fig. 2 and 2A) and enables the thick lead frame 130 to be manufactured in the form of a high-density matrix lead frame 200, thereby improving assembly efficiency and reducing packaging costs. The side chip bars 190 further provide greater mold adhesion to the lead frame 130 and reduce moisture exposure to the chip 101.

Fig. 3 shows a TO 252 land pattern 300 including a drain region 310, a source region 320 and a gate region 330. A high current semiconductor power SOIC device 100 in accordance with the present invention is shown surface mounted to the land pattern 300 with drain lead 126 mounted to drain region 310, a portion of source lead 116 including portion 116c and a portion of portion 116a mounted to source region 320, and gate lead 112 including portions 112a and 112b mounted to gate region 330. When mounted to source region 320, source portion 116c, along with gate portion 112b, provides SOIC device 100 with less resistivity and better heat dissipation performance. In addition, the source portion 116c and the gate portion 112b provide matching of the SOIC device 100 TO the TO 252 land pattern 330.

For comparison purposes, in fig. 4, DPAC package 400 is shown mounted to land pattern 300.

The high current semiconductor power SOIC device of the present invention can be used in many high current applications TO replace TO 252(DPAK) devices. The relatively thick lead frame formed of a single gauge material results in a higher assembly rate and allows for an increased number of bonding wires that can be used to reduce package resistance.

It is clear that the above embodiments can be varied in many ways without departing from the scope of the invention. In addition, various aspects of a particular embodiment may contain subject matter of patented aspects that do not relate to other aspects of the same embodiment. Further, various aspects of the different embodiments may be combined together. The scope of the invention should, therefore, be determined by the appended claims and their legal equivalents.

Claims (13)

1. A high current semiconductor power low profile integrated circuit package, comprising:

a relatively thick leadframe formed from a single gauge material having a thickness greater than 8 mils, the leadframe having a plurality of leads and a first leadframe region including a die bonded thereto;

a pair of wire bonding regions disposed on the same plane as the top surface of the chip;

bonding wires of aluminum up to 20mil diameter connecting the chip to a plurality of leads; and

a resin body sealing the chip, the bonding wire, and at least a part of the lead frame;

the package has terminal pins mountable TO a TO 252 package land pattern, the high current semiconductor power low profile integrated circuit package further including outwardly extending drain, source and gate leads capable of mating with the TO 252 package land pattern, the terminal pins mating with the pins of the high current semiconductor power low profile integrated circuit package;

the bonding region includes a source bonding region that extends the full length of the molten source lead.

2. The package of claim 1, wherein the leadframe region is exposed through a bottom surface of the package.

3. The package of claim 1, wherein the chip comprises an integrated circuit.

4. The package of claim 3, wherein at least one of the plurality of leads is connected to the integrated circuit terminal by a wire-less bond.

5. The package of claim 3, wherein the integrated circuit comprises a FET field effect transistor device.

6. The package of claim 5, wherein the plurality of leads include a source lead connected to the source region, the gate region and the drain region of the FET device, respectively, a gate lead and a drain lead, the source lead including a laterally extending portion and first and second portions extending perpendicularly from the laterally extending portion in spaced relation to one another, the gate lead including a laterally extending portion and a portion extending perpendicularly from the laterally extending portion, the source lead laterally extending portion and the first and second portions, and the gate lead laterally extending portion and the portion extending perpendicularly from the laterally extending portion being exposed outside the resin body.

7. The package of claim 6, wherein the source lead comprises a fused solid sheet.

8. The package of claim 6, wherein the source lead and the gate lead are disposed adjacent to each other on a side of the semiconductor package opposite the drain lead.

9. The package of claim 6, wherein the source lead is connected to a source bonding region disposed inside the resin body, the gate lead is connected to a gate bonding region disposed inside the resin body, the source bonding region and the gate bonding region are disposed on a same plane as a top surface of the FET device, and the bonding wire connects the source lead to the source bonding region and the gate lead to the gate bonding region.

10. The package of claim 6, wherein the drain lead includes a notch for clamping the die.

11. The package of claim 6, wherein the drain lead includes a notch for positioning the package during reflow soldering.

12. The package of claim 1, wherein the leadframe further comprises a pair of side chip bars.

13. A high current semiconductor power device low profile integrated circuit package having a flattened lead containing an electronic device, the package comprising:

a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame including a plurality of leads and a lead frame area having an electronic device soldered thereto;

a pair of wire bonding regions disposed on the same plane as a top surface of the electronic device;

bonding wires of aluminum having a diameter of up to 20mil connecting the electronic device to the plurality of leads; and

a resin body sealing the electronic device, the bonding wire, and at least a portion of the lead frame;

the package has terminal pins that can be mounted TO the TO 252 package land pattern, the high current semiconductor power low profile integrated circuit package with flat leads that houses the electronic device further includes outwardly extending drain, source and gate leads that can match the TO 252 package land pattern, the terminal pins matching the pins of the high current semiconductor power low profile integrated circuit package;

the bonding region includes a source bonding region that extends the full length of the molten source lead.