HK1114241B - Semiconductor device having enhanced performance and method - Google Patents

Description

Semiconductor device with improved performance and method

Technical Field

The present invention relates generally to semiconductor devices, and more particularly to power switching devices including high speed devices such as RF power amplifiers and methods of making the same.

Background

A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a common type of power switching device. The MOSFET device includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to the channel region and separated therefrom by a thin dielectric layer.

When the MOSFET device is in an on-state, a voltage is applied to the gate structure to form a conducting channel region between the source and drain regions, which allows current to flow through the device. In the off state, any voltage applied to the gate structure is low enough so that no conduction channel is formed and thus no current flow occurs. During the off-state, the device must support a high voltage between the source and drain regions.

Designers are often faced with trade-offs in optimizing the performance of MOSFET devices with respect to device performance parameters. In particular, the selection of available device structures or fabrication processes may improve one device parameter, but such selection may at the same time degrade one or more other device parameters. For example, the output current or drive current (I) of the MOSFET device can be increased_DS) Available structures and processes for capability and on-resistance also reduce their breakdown voltage (BVdss) capability and increase gate-to-drain capacitance.

Accordingly, there is a need for an improved semiconductor device structure and method of fabricating the same that addresses the above and other problems.

Drawings

FIG. 1 illustrates a highly enlarged, partial cross-sectional view of a semiconductor structure, in accordance with an embodiment of the present invention;

FIG. 2 is a drawing showing I embodiments of the present invention_DSFollowing V_GSA graph of variation;

FIG. 3 is a drawing showing I embodiments of the present invention_DSATAnd BV_DSSA graph of performance;

FIG. 4 illustrates a highly enlarged, partial cross-sectional view of an embodiment of the present invention during an early stage of manufacture;

FIG. 5 illustrates a highly enlarged, partial cross-sectional view of an embodiment of the present invention at a later stage of manufacture;

FIG. 6 illustrates a highly enlarged, partial cross-sectional view of an embodiment of the present invention at yet a later stage of manufacture;

FIG. 7 illustrates a highly enlarged, partial cross-sectional view of an embodiment of the present invention at a later stage of manufacture;

FIG. 8 illustrates a highly enlarged, partial cross-sectional view of an embodiment of the present invention at a further, later stage of manufacture;

Detailed Description

For ease of understanding, the elements in the drawings are not necessarily drawn to scale, and like element numbers are used where appropriate throughout the drawings. Although the following discussion describes an n-channel device, the invention also relates to a p-channel device, which may be formed by changing the conductivity type of the layers and regions described to the opposite type.

Furthermore, the devices of the present invention may comprise either a cellular design (in which the body region is a plurality of cellular regions) or a monolithic design (in which the body region comprises a single region formed in an elongated pattern, typically a serpentine pattern). However, for ease of understanding, the device of the present invention will be described in a cellular design throughout the specification. It should be understood that this means that the present invention includes both a cellular design and either a single base design.

Fig. 1 shows a partial cross-sectional view of an Insulated Gate Field Effect Transistor (IGFET), MOSFET, power transistor or switching device or cell 10, according to an embodiment of the present invention. By way of example, device 10 is one of many such devices that are integrated with logic and/or other components in a semiconductor chip as part of a power integrated circuit. Alternatively, device 10 is one of many such devices that are integrated together to form a discrete transistor device.

Device 10 includes a region 11 of semiconductor material comprising, for example, an n-type silicon substrate having a resistance in the range of about 0.001 to about 0.005ohm-cm, and may be doped with arsenic. In the embodiment shown, the substrate 12 provides a drain contact. A semiconductor layer or extended drain region 14 is formed in or on substrate 12. In one embodiment, layer 14 is formed using a conventional epitaxial growth process. Alternatively, the extended drain region 14 is formed using conventional doping and diffusion processes. In an embodiment suitable for a 50 volt (volt) device, layer 14 is n-type doped with a doping concentration of about 1.0 x 10¹⁵Atom/cm³(atoms/cm³) And a thickness on the order of about 3 to about 5 microns. The thickness and doping concentration of layer 14 is increased or decreased depending on the desired BVdss rating of device 10. It should be understood that other materials may be used for the body 11 of semiconductor material or portions thereof, including silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, silicon carbide, or similar materials.

A body or doped region 31 is formed in semiconductor layer 14 and extends from major surface 18 of body 11 of semiconductor material. By way of example, body region 31 comprises p-type conductivity and has a doping concentration suitable for forming an inversion layer (inversion layer) that operates as conduction channel 45 of device 10. Body region 31 extends from major surface 18 to a depth such as from about 0.5 to about 3.0 microns. An n-type source, current carrying, or input region 33 is formed within or within body region 31 and extends from major surface 18 to a depth of, for example, about 0.1 microns to about 0.5 microns. A p-type body contact or contact region 36 is also formed within body region 31 and provides a lower contact resistance to body region 31 at major surface 18. In addition, the contact region 36 reduces the sheet resistance (sheet resistance) of the body region 31 under the source region 33, which suppresses the parasitic bipolar effect.

First dielectric layer 41 is formed over or adjacent to portions of major surface 18. For example, dielectric layer 41 includes a thermal oxide layer having a thickness of about 0.05 microns to about 0.2 microns. Second dielectric layer 42 is formed over dielectric layer 41. In one embodiment, second dielectric layer 42 comprises silicon nitride and has a thickness of about 0.05 microns.

Gate dielectric layer 43 is formed on other portions of major surface 18 adjacent body region 31 or adjacent to other portions of major surface 18 adjacent body region 31. Gate dielectric layer 43 comprises, for example, silicon oxide and has a thickness of about 0.01 microns to about 0.1 microns. In alternative embodiments, gate dielectric layer 43 comprises silicon nitride, tantalum pentoxide, titanium dioxide, barium strontium titanate, or combinations thereof, including combinations with silicon oxide, and the like.

In an optional embodiment, a doped polycrystalline semiconductor layer, conductive layer, shield layer, or ground layer 46 is formed over dielectric layers 41 and 42. Conductive layer 46 comprises a doped polysilicon layer or a polysilicon layer, for example, and has a thickness of about 0.1 microns. Although not shown, conductive layer 46 may be directly or indirectly connected or coupled to a conductive contact or source contact layer 63.

Third dielectric layer 48 is formed over conductive layer 46 and fourth dielectric layer 51 is formed over third dielectric layer 48. By way of example, dielectric layer 48 comprises silicon nitride (e.g., about 0.05 microns thick), and dielectric layer 51 comprises a deposited conductive layer 53 of silicon oxide (e.g., about 0.7 microns thick) formed over dielectric layer 51 and comprising, for example, n-type polysilicon or polysilicon (e.g., about 0.3 microns thick).

Conductive spacer gate regions, vertical spacer gate regions, or spacer-defined gate regions or conductive electrodes 57 are formed over gate dielectric layer 43 and are separated from conductive layers 46 by dielectric spacers 59. Conductive spacer gate regions 57 in conjunction with gate dielectric layer 43 form a control electrode or gate structure 58. Conductive split gate region 57 comprises, for example, n-type polysilicon or polysilicon and is about 0.2 to about 0.8 microns thick. In an exemplary embodiment, dielectric spacer 59 comprises silicon nitride and is about 0.1 microns thick. Spacer gate regions 57 are connected to conductive layer 53 to provide a conductive gate structure that controls the formation of channel 45 and the conduction of current within device 10. In the embodiment shown, conductive connection 77 connects spacer gate region 57 to conductive layer 53. The conductive connection 77 comprises, for example, n-type polysilicon. The spacer-defined gate region refers to a control electrode formed of a gate material deposited on one surface to control a channel formed on the other vertical surface. In the case of device 10, channel 45 is formed at major surface 18, which is considered to be a horizontal plane. The control electrode film used to form the split gate regions 57 is deposited along a vertical plane 68 perpendicular to the surface 18.

The conductive spacer gate region 57 provides minimal gate-drain overlap compared to conventional devices, thereby significantly reducing gate charge. Additionally, in device 10, electrical routing for the gate is provided by conductive layer 53, which is elevated above major surface 18, thereby further reducing the gate charge. In addition, conductive layer 46 functions, among other things, as a ground plane or shield layer interposed between the gate and drain regions to further reduce the gate-to-drain capacitance. These features provide increased switching speed and reduced input charge requirements.

A fifth dielectric layer 61 is formed over portions of device 10 and comprises, for example, silicon nitride having a thickness of about 0.05 microns. An interlayer dielectric (ILD) layer 62 is formed over portions of device 10 and comprises, for example, silicon oxide having a thickness of about 0.8 microns. An opening (opening) is formed in the dielectric layer to provide contact to the device 10 for the source contact layer 63. As shown, a portion of major surface 18 is etched such that source contact layer 63 contacts both source regions 33 and body regions 36. In one embodiment, the source contact layer 63 includes an aluminum silicon alloy or the like. A drain contact layer or conductive electrode 66 is formed on the opposite surface of region 11 of semiconductor material and comprises, for example, a solderable metal structure such as titanium-nickel-silver, chromium-nickel-gold, or the like.

In accordance with the present invention, device 10 further includes doped regions, current spreading regions, doped masking regions (doped field regions), or localized dopingHetero region 43 formed within a portion of semiconductor layer 14 adjacent, near, or in close proximity to body region 31 and adjacent or near major surface 18. Specifically, doped region 47 is disposed or positioned within semiconductor layer 14, wherein current I flows when device 10 is in operation_DSExiting the channel 45 (i.e., the drain edge of the channel) into the extended drain region 14. In one embodiment, doped regions 47 are confined from the vertical and horizontal directions near major surface 18 at outer edges 450 of channel 45. Doped region 47 extends from body region 31 a distance 473 on the order of about 0.1 to 0.4 microns, with a doping concentration outside or outside of doped region 47 and near major surface 18 equal to or near the background doping concentration (background doping concentration) of semiconductor layer 14.

Doped region 47 comprises the same conductivity type as semiconductor layer 14 and has a doping concentration that is about 5 times to about 50 times the doping concentration of semiconductor layer 14. In one embodiment, the doping concentration of doped region 47 is about 20 to 40 times the doping concentration of semiconductor layer 14. By way of example, for a 50V device, doped region 47 includes approximately 1.0 × 10 at outer edge 471¹⁵Atom/cm³And about 2.0 x 10 at the edge 450 of the channel region 45¹⁶Atom/cm³Dopant concentration of (a). The inventors of the present invention have found that the localized doped regions 47 provide enhanced performance over devices employing, for example, blanket or more continuous layers of increased doping near the major surface 18. For example, for a given breakdown voltage BV_DSSIn other words, a higher I can be obtained_DSAnd a lower on-resistance. Higher BV can be achieved by using local areas according to the invention than those using covered areas_DSSThereby providing a device with increased voltage blocking performance. Moreover, device 10 has lower gate-to-drain and shield-to-drain capacitance than those devices employing blanket or continuous layers, thereby providing device 10 with enhanced switching performance.

Fig. 2 shows the drain current I of the device 10_DSPerformance at 28V bias with V_GSA graph of the variation. The figure further depicts I_DSWith dopingVariation of various peak doping concentrations in region 47, wherein line 1A corresponds to undoped region 47 and line 2A corresponds to 1.0 × 10¹⁶Atom/cm³Line 3A corresponds to 2.0 x 10¹⁶Atom/cm³Line 4A corresponds to 3.0 x 10¹⁶Atom/cm³Line 5A corresponds to 4.0 x 10¹⁶Atom/cm³Line 6A corresponds to 5.0 x 10¹⁶Atom/cm³Line 7A corresponds to 6.0 x 10¹⁶Atom/cm³Line 8A corresponds to 7.0 x 10¹⁶Atom/cm³Line 9A corresponds to 8.0 x 10¹⁶Atom/cm³Line 10A corresponds to 9.0 x 10¹⁶Atom/cm³Line 11A corresponds to 1.0 x 10¹⁷Atom/cm³The peak doping concentration of (a). As shown in fig. 2, the local doped region 47 significantly increases I with increasing peak doping concentration_DSAnd (4) performance.

FIG. 3 shows the saturation current I_DSATFollowing breakdown voltage BV_DSSA graph of the variation. Lines 1B through 11B correspond to the same peak doping concentrations as lines 1A through 11A shown in fig. 2 above. As shown in FIG. 3, the device 10 according to the invention exhibits a slight increase in BV although only_DSSHowever, realize I_DSATThe performance is significantly enhanced.

Turning now to fig. 4-7, a method of forming a device 10 according to the present invention is described. Fig. 4 shows an enlarged partial cross-sectional view of device 10 at an early stage of fabrication. First dielectric layer 41 is formed over major surface 18 and comprises, for example, silicon oxide having a thickness of about 0.05 microns to about 0.2 microns. Thermal oxide growth at about 900 degrees celsius is suitable. Next, a second dielectric layer 42 is formed over first dielectric 41 and comprises, for example, about 0.1 microns of silicon nitride.

Next, conductive layer 46 is formed over second dielectric layer 42. In one embodiment, conductive layer 46 comprisesIncluding about 0.1 micron polysilicon, and which is either deposited doped or undoped. If conductive layer 46 is initially deposited undoped, then conductive layer 46 is doped using, for example, ion implantation techniques. In one embodiment, conductive layer 46 is p-type and doped with boron. About 5.0X 10 using an implant energy of about 30KeV¹⁵To about 1.0X 10¹⁶Atom/cm²The boron ion implant dose of (a) is sufficient to dope conductive layer 46.

Next, a third dielectric layer 48 is formed over conductive layer 46, and a fourth dielectric layer 51 is formed over third dielectric layer 48. Third dielectric layer 48 comprises, for example, silicon nitride (e.g., about 0.05 microns thick), and dielectric layer 51 comprises a deposited oxide (e.g., about 0.7 microns thick). A conductive layer 53 is then formed over the fourth dielectric layer 51 and comprises, for example, n-type polysilicon (e.g., about 0.3 microns thick). Protective layer 54 is formed over conductive layer 53 and comprises, for example, about 0.15 microns of silicon nitride.

Photolithography and etching steps are performed to etch portions of layers 54, 53, 51, 48, 46, and 42 to provide openings 70. This also forms a pedestal stack structure 56 that includes the remaining portions of layers 42, 46, 48, 51, 53 and 54. In one embodiment, the opening 70 has a width 73 on the order of about 5.0 microns to about 8.0 microns.

In one embodiment for forming doped region 47, n-type dopants are introduced or implanted into semiconductor layer 14 through opening 70. In this implementation, the edge of doped region 47 is defined by a side surface 68 of base structure 56 (i.e., doped region 47 is self-aligned to base structure 56). By way of example, by implanting at an implant energy of about 250KeV, and at an angle in the range of about 25 degrees to about 60 degrees orthogonal, about 5.0X 10¹¹Atom/cm²To about 2.0X 10¹²Atom/cm²A dose of phosphorus is implanted to form doped regions 47. In one embodiment, the angle is about 45 degrees. The amount of tilt is adjusted based on the width 73 of the opening 70 and the height of the base stack structure 56. The implant energy is selected so that the wafer surface is not doped within the openings 70But forms a subsurface layer of about 0.5 microns below the opening 70. Therefore, when the doped region 31 is formed, the channel region of the device is not counter-doped at the surface within the opening 70, thereby increasing mobility within the channel region. Moreover, an angled implant forms a doped region about 0.5 microns beyond side surface 68. The angled implant is incident on the side surface 68 and penetrates the layers 41, 42, 46, 48, forming doped regions 47. The doped region extends from the surface to a depth of about 0.5 microns below the surface. The portion of the ion implant implanted into the subsurface below the opening 70 is counter-doped by a thicker channel implant or doping process when the doped region 31 is formed as described below. The implanted dopants are then activated and diffused at this point or at a later step, for example, after forming doped regions 31. Activating the dopants at this point will cause the dopants to diffuse further under the pedestal stack 56, which desirably increases the distance 473 (shown in fig. 1).

In an alternative embodiment for forming doped region 47, a conventional implant angle of seven degrees is employed, and the implanted dopants are then activated and diffused to laterally move the dopants under pedestal structure 56 to provide a similar structure. Alternatively, the dopant may be activated at a later stage. In yet another embodiment, doped regions 47 are formed prior to forming pedestal structures 56 in a non-self-aligned manner using conventional masking steps. Pedestal structures 56 are then formed over major surface 18 to provide doped regions 47 in the desired locations.

Fig. 5 shows an enlarged partial cross-sectional view of device 10 after an additional process step of forming dielectric spacers 59. In one embodiment, a silicon nitride film is deposited over pedestal stack structure 56 and first dielectric layer 41. By way of example, a silicon nitride film about 0.1 microns thick is deposited using chemical vapor deposition techniques. Next, a conventional anisotropic etch back step is used to remove portions of the silicon nitride layer on pedestal stack structure 56 and first dielectric layer 41, while leaving portions of the silicon nitride layer on sidewalls or vertical surfaces 68 to form dielectric spacers 59. In an alternative embodiment, the doped regions 47 are formed at this stage of fabrication using the angled implant conditions noted above. In one embodiment, the implanted dopant is then also activated diffused at this stage to provide lateral diffusion under the pedestal stack 56.

In a further step, a silicon oxide wet etch is then used to remove portions of dielectric layer 41 within openings 70. By way of example, dielectric layer 41 is etched using dilute hydrofluoric acid (e.g., 50: 1). In an exemplary embodiment, the etch time is extended (e.g., 8 to 15 minutes) to undercut or remove material from dielectric layer 41 from under dielectric spacers 59 to form recessed portions 74. Recessing dielectric layer 41 in this manner ensures that channel 45 (shown in fig. 1) formed within body region 31 extends into semiconductor layer 14 to allow channel current to flow more efficiently. In an exemplary embodiment, the portion 74 is recessed below the dielectric spacer 59 by a distance of less than about 0.1 microns. A thermal silicon oxide is then grown to a thickness of about 0.0125 microns on major surface 18 within opening 70 to form gate dielectric layer 43.

Fig. 6 shows an enlarged partial cross-sectional view of device 10 after additional processing. A conformal layer of semiconductor material 571 is deposited over device 10 to a thickness of about 0.1 microns to about 0.15 microns. Boron dopants are then introduced into major surface 18 through opening 70 and conformal layer of semiconductor material 571 to provide p-type dopants for body region 31. By way of example, conformal layer of semiconductor material 571 comprises undoped polysilicon, and boron is implanted into semiconductor layer 14 through the undoped polysilicon. Region 31 is doped by a minimum of two ion implantations, each at a dose of about 1.0 x 10¹³Atom/cm²And the two implants have energies of about 45KeV and 100KeV, respectively, suitable for a 50V device.

Fig. 7 shows an enlarged partial cross-sectional view of device 10 after yet another process. Next, a second conformal layer of semiconductor material is deposited over conformal layer of semiconductor material 571 and both layers are etched to provide spacer gates 57. By way of example, the second conformal layer of semiconductor material comprises about 0.2 microns of n-type polysilicon, which may be doped during deposition or subsequently doped using ion implantation or other doping techniques. After forming the spacer gates 57, an additional 0.015 micron of gate dielectric (e.g., silicon oxide) is added to the surfaces of the spacer gates 57 and the exposed portions of the gate oxide 43.

In one embodiment, the etching step to form the barrier gate 57 also exposes the upper portions of the protective layer 54 (fig. 6) and the dielectric barrier 59. The protective layer 54 and the upper portion of dielectric barrier 59 are then etched to remove the protective layer 54 and the upper portion of dielectric barrier 59 is removed between barrier gate 57 and conductive layer 53. This leaves a gap between conductive layer 53 and barrier gate 57.

In another step, a conductive material such as polysilicon is deposited to provide connected conductive portions 77. Connected conductive portion 77 fills the gap formed during removal of protective layer 54 and portions of dielectric spacers 59 and connects or electrically connects spacer gate 57 to conductive layer 53. An n-type doping step is then performed to dope the connected conductive portions 77 and provide dopants for the source regions 33. In an exemplary embodiment, a 3.0 x 10 with an 80KeV implant energy for this doping step is used¹⁵Atom/cm²Implant dose of arsenic.

Fig. 8 shows an enlarged partial cross-sectional view of device 10 after yet another step in fabrication. A fifth dielectric layer 61 is deposited and comprises, for example, about 0.05 microns of silicon nitride. Subsequently, an ILD layer 62 is deposited over the fifth dielectric layer 61. In an exemplary embodiment, ILD layer 62 comprises deposited silicon oxide having a thickness of about 0.8 microns. An optional ILD taper etch (taperetch) is used to gradually thin portion 62a of ILD layer 62, which helps to gradually cover subsequently formed layers.

Next, contact openings 81 are formed using conventional photolithography and etching steps, which expose a portion of major surface 18. Subsequently, a p-type ion implantation step is used to form contact region 36 through opening 81. By way of example, 3.0X 10 is used¹⁴Atom/cm²And an implant energy of 80 KeV. Followed by conformal barrierLayers are deposited and etched to form the barriers 82. In one exemplary embodiment, a 0.3 micron silicon nitride layer is deposited and etched to form the barriers 82. At this stage, a rapid annealing step is used to activate and diffuse the various ion implants. For example, device 10 is exposed to a temperature of about 1030 degrees Celsius for about 45 seconds.

An etching step is then used to remove portions of major surface 18 to form recessed portions 84. This allows source contact layer 63 to contact source region 33 and contact region 36, which can shorten both regions together. The barrier 82 is then removed. In a subsequent process, a source contact layer 63 is deposited and patterned. The substrate 12 is then optionally thinned, and a drain contact layer 66 is deposited to provide the structure shown in fig. 1. It is further understood that other conductive layers, such as silicide layers, may be formed prior to depositing source contact layer 63.

In view of the foregoing, it is apparent that a novel device and method of making the same are disclosed. Included, among other features, are semiconductor devices having a locally doped region proximate to a channel region portion of the device that, among other things, increases I_DSATAnd (4) performance. In addition, this increase in performance did not significantly reduce BV_DSSOr significantly increase the gate to drain or shield to drain capacitance.

While the invention has been described and illustrated with reference to specific embodiments, it is not intended that the invention be limited to these exemplary embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. Accordingly, it is intended that the present invention embrace all such modifications and variations as fall within the scope of the appended claims.

Claims (10)

1. A semiconductor device, comprising:

a semiconductor material having a major surface, wherein the semiconductor material comprises a first conductivity type;

a control electrode formed spaced apart from the semiconductor material;

a body region of a second conductivity type formed within said major surface adjacent said control electrode, wherein a portion of said body region forms a channel region when said semiconductor device is in operation;

a source region of the first conductivity type formed within the body region;

a local doped region of the first conductivity type formed in the semiconductor material proximate a drain edge of the channel region, wherein the local doped region is confined near the major surface in both a vertical direction and a horizontal direction, the local doped region having an outer edge opposite the drain edge, and wherein a dopant concentration of the local doped region is at least 5 times a dopant concentration of a portion of the semiconductor material located outside the body region and the local doped region, and wherein the portion of the semiconductor material is contiguous with the major surface and the local doped region; and

a groundplane layer formed over the portion of the semiconductor material and overlapping the outer edge.

2. The semiconductor device of claim 1, wherein said localized doped region extends from said body region a lateral distance in the range from about 0.1 microns to about 0.4 microns.

3. The semiconductor device of claim 1, wherein a doping concentration of the local doped region is about 5 times to about 50 times a doping concentration of the semiconductor material.

4. The semiconductor device of claim 1, wherein a second surface of the semiconductor material opposite the major surface forms a conductive electrode.

5. The semiconductor device of claim 1, further comprising a pedestal structure formed overlying a portion of the major surface, the pedestal structure having a side surface, wherein the control electrode comprises a conductive material disposed along the side surface, and wherein the localized doped region has an edge bounded by the side surface of the pedestal structure.

6. The semiconductor device of claim 5 wherein the pedestal structure comprises the groundplane layer.

7. The semiconductor device of claim 6, wherein the ground plane layer comprises polysilicon.

8. The semiconductor device of claim 5, wherein the pedestal structure comprises:

a first dielectric layer formed over a major surface of the semiconductor material;

a second dielectric layer formed over the first dielectric layer;

a conductive layer formed over the second dielectric layer, wherein the conductive layer is connected to the control electrode.

9. The semiconductor device of claim 8, wherein said conductive material comprises polysilicon.

10. The semiconductor device of claim 1, wherein said localized doped region has an approximate thickness of 5.0 x 10¹⁶Atom/cm³To about 1.0X 10¹⁷Atom/cm³Peak doping concentration within the range.