HK1108071B - Phase frequency detector with a d flip flop - Google Patents

Description

Phase frequency detector with D flip-flop

Technical Field

The present invention relates to electronics, and more particularly to a phase frequency detector circuit using D flip-flop elements.

Background

In recent years, the evolution of telecommunication technology has led to a corresponding evolution of electronic technology. Wireless communication devices are now common like previous dial-up telephones. One key component in many wireless circuits is a delta-sigma modulated fractional-N frequency synthesizer. Such a circuit is capable of synthesizing almost all of the required signal frequencies. As part of this assembly, a Phase Frequency Detector (PFD) receives an input reference signal having a known frequency and a variable input signal, i.e., a divider input, having a variable frequency determined by dividing the frequency of a VCO (voltage controlled oscillator). The PFD outputs a signal proportional to the phase difference between the input reference signal and the divider input. Thus, the output signal can be used to increase or decrease the frequency of the VCO to minimize the phase difference. Such a feedback circuit is called a phase locked loop or PLL.

Current PFD designs suffer from what is commonly referred to as "dead space". When the frequency synthesizer is in lock, the phase difference between the reference input and the divider input is very close to zero. Thus, an output (or outputs, since a PFD may have more than one output) should not be active, or the pulses generated should be narrow if the output is active. Due to the small phase error near zero caused by the delay and uncontrollable conditions, it is not possible to generate a complete pulse at the output of the PFD. This results in a flat or non-linear portion, commonly referred to as a dead zone, in the transfer curve of the PFD. This is not very severe for integer-N synthesizers, but for delta-sigma modulated fractional-N frequency synthesizers it results in an increased spur level of the fractional-N.

Thus, there is a need for systems and assemblies that avoid the above-mentioned problems. It is therefore an object of the present invention to mitigate, if not overcome, the disadvantages of the prior art.

Disclosure of Invention

The present invention provides a method, system and assembly for use with or as a phase frequency detector. The phase frequency detector extends (stretch) one of its output pulses, forcing the PLL to operate in a region where the phase difference between the divided input and the reference input is not close to zero. This enables the detector to operate in a more linear region. Also disclosed as part of the invention is a novel structure for a D-type flip-flop. In one embodiment, the D-type flip-flop toggles on both the rising and falling edges of the reference input, thereby enabling the use of lower frequency inputs while taking advantage of higher frequencies.

In a first aspect, the present invention provides a D-type flip-flop comprising:

a first FET (field effect transistor) receiving an input signal at its gate terminal;

a delay element also receiving the input signal, the delay element outputting a delayed logical negation of the input signal;

a second FET receiving the output of the delay element at its gate terminal, the drain terminal of the second FET being connected to the source terminal of the first FET, the source terminal of the second FET being connected to relative ground;

a reset FET connected to said relative ground by a source terminal thereof, a drain terminal of said reset FET being connected to a connection node, a gate terminal of said reset FET being connected to an external reset input;

a third FET connected to the connection node by its source terminal, a drain terminal of the third FET connected to a power supply, a gate terminal of the third FET connected to the drain terminal of the first FET;

a fourth FET connected to the drain terminal of the first FET through a source terminal of the fourth FET, a drain terminal of the fourth FET being connected to the power supply, and a gate terminal of the fourth FET being connected to the connection node,

wherein

The output of the flip-flop is connected out from the connection node;

the first, second and reset FETs are of the same type; and

the third and fourth FETs are of the same type.

In a second embodiment, the present invention provides a phase frequency detector circuit comprising:

a first D flip-flop receiving a reference input;

a second D flip-flop receiving a frequency division input;

a first NAND gate receiving a first select input and the divide input;

a first NOT gate receiving an output of the first NAND gate;

a NOR gate receiving an output of the first NOT gate and an output of the first D flip-flop;

a second NOT gate receiving the output of the NOR gate and producing a first output of the detector circuit;

a second NAND gate receiving the output of the first D flip-flop gate and an output of the second D flip-flop;

a third NOT gate receiving an output of the fourth NAND gate, the output of the third NOT gate being received as a reset input to the first and second D flip-flops.

In a third embodiment, the present invention provides a phase frequency detector circuit comprising:

a first D flip-flop receiving a reference input;

a second D flip-flop receiving a frequency division input;

a first NAND gate receiving a select input and the divide input;

a second NAND gate receiving a logical negation of an output of the first NAND gate and an output of the second D flip-flop;

a first NOT gate receiving an output of the second NAND gate and generating an output of the detector circuit;

a third NAND gate receiving an output of the first D flip-flop and the output of the second D flip-flop;

a second NOT gate receiving an output of the third NAND gate, the output of the second NOT gate being received as a reset input to the first and second D flip-flops.

In another embodiment, the present invention provides a phase frequency detector circuit comprising:

a first D flip-flop receiving a reference input;

a second D flip-flop receiving a frequency division input;

a first NAND gate receiving a first select input and the divide input;

a first NOT gate receiving an output of the first NAND gate;

a NOR gate receiving an output of the first NOT gate and an output of the first D flip-flop;

a second NOR gate receiving an output of the NOR gate and producing a first output of the detector circuit;

a second NAND gate receiving a second select input and the divide input;

a third NAND gate receiving an output of the first D flip-flop and an output of the second D flip-flop;

a third NOT gate receiving an output of the third NAND gate, the output of the third NOT gate being received as a reset input to the first and second D flip-flops;

a fourth NAND gate receiving a second select input and the divide input;

a fifth NAND gate receiving a logical negation of an output of the first NAND gate and the output of the second D flip-flop;

a fourth NOT gate receiving an output of the fifth NAND gate and generating a second output of the detector circuit.

In a fifth embodiment, the present invention provides a phase frequency detector comprising:

at least two D flip-flops;

a plurality of logic gates, at least one of the logic gates being connected to at least one of the D flip-flops,

wherein

At least one of the at least two D flip-flops comprises:

a first FET (field effect transistor) receiving an input signal at its gate terminal;

a delay element also receiving the input signal, the delay element outputting a delayed logical negation of the input signal;

a second FET receiving the output of the delay element at its gate terminal, the drain terminal of the second FET being connected to the source terminal of the first FET, the source terminal of the second FET being connected to relative ground;

a reset FET connected to said relative ground by a source terminal thereof, a drain terminal of said reset FET being connected to a connection node, a gate terminal of said reset FET being connected to an external reset input;

a third FET connected to the connection node by its source terminal, a drain terminal of the third FET connected to a power supply, a gate terminal of the third FET connected to the drain terminal of the first FET;

a fourth FET connected to the drain terminal of the first FET through a source terminal of the fourth FET, a drain terminal of the fourth FET being connected to the power supply and a gate terminal of the fourth FET being connected to the connection node,

wherein

The output of the flip-flop is connected out from the connection node;

the first, second and reset FETs are of the same type; and

the third and fourth FETs are of the same type.

Drawings

A better understanding of the present invention can be obtained by considering the following detailed description with reference to the following drawings, in which:

FIG. 1 illustrates a phase frequency detector according to the prior art;

FIG. 2 illustrates a phase frequency detector according to an aspect of the present invention;

FIG. 3 illustrates a D flip-flop that may be used in the phase frequency detector of FIG. 2; and

fig. 4 shows a modification of the D flip-flop of fig. 3.

Detailed Description

Referring to fig. 1, a phase frequency detector 10 according to the prior art is shown. Two D-type flip-flops 20, 30 are shown, with flip-flop 20 receiving a reference input 40 and flip-flop 30 receiving a variable frequency input 50, a so-called frequency-dividing input. As is well known in the art, the PFD 10 attempts to minimize the phase difference between the reference input 40 and the divider input 50. The outputs 60, 70 may be used as feedback to the VCO. When the reference edge (reference edge) is in the sub-divisionWhen the frequency edge (divider edge) arrives before, the output 60, i.e., the pull-up output (output Q of the D flip-flop 20) is high. Therefore, in this case, the signal of the VCO must be "pulled up" or increased to match the divider input. Similarly, if the dividing edge arrives first, the other output, i.e., the pull-down output (output Qe of D flip-flop 30) is high. This means that the reference frequency must be lowered to match the divider input. To be suitable for use in logic, each output has a corresponding logical negation as part of the output. Output 60A (PUB or pull-up bus (bar) or output Qe) is the logical negation of output signal 60, and output 70A (PDB or pull-down bus or output Qe)) Is the logical not of output 70.

The system resets after each pulse, so the D flip-flops 20, 30 may resample the incoming reference and divider inputs. The system reset is accomplished using NAND gate 80 and NOT gate 90. The NAND gate 80 receives the outputs 60, 70, and the output of the NAND gate 80 is received by the NOT gate 90. The output of the NOT gate 90 is received at the reset port of the D flip-flops 20, 30. Due to the delay of the gates 80, 90, a reset will not occur immediately, resulting in an output with a limited pulse width even when the PFD is locked (i.e. when the reference frequency and the divider input have a minimum phase difference). The pulse width of the output is proportional to the phase difference between the rising edges of the inputs. Alternatively, the NAND gate 80 AND the NOT gate 90 may be replaced with a single AND gate. It should be noted that for clarity, when referring to the outputs of the D flip-flops, we refer to Q or Qe rather than the logical negation of these outputs.

Referring to fig. 2, a novel apparatus for a phase frequency detector 100 is shown. Two D flip-flops 120, 130 receive a reference input 140 and a divider input 150. The divider input 150 is a variable frequency input signal that may be adjusted up or down depending on the state of the output signal, while the reference input signal 160 is a fixed frequency input signal. Much like the system of FIG. 1, the pull-up output 160 has a corresponding logical not output, i.e., a pull-up bus output 160A. The pull-down output 170 also has a corresponding logical not, i.e., a pull-down bus (PDB) output 170A.

The reset arrangement of the system of fig. 2 is the same as that of fig. 1, i.e. the NAND gate 180 receives the outputs 160, 170 and passes their outputs to the NOT gate 190. The output of the NOT gate 190 is received by the reset inputs of the D flip-flops 120, 130.

To select which output is to be stretched or which output is to have its pulse spread, select inputs 200, 210 are provided. If select input 200 is high, then pull-down output 170A is extended, and if select input 210 is high, then pull-up output 160 is extended.

This is achieved by appropriately gating the select outputs of the D flip-flops using the select inputs 200, 210. Select input 200 is received by NAND gate 220 along with divider input 150. The output of NAND gate 220 is received by NAND gate 240 along with the logical negation 230 of the pull-down output 170. The output of NAND gate 240 is then received by NOT gate 250. The output of the NOT gate 250 is the extended pull-down bus output 170A. The NAND gate 220 can be a single NOT gate that receives the select input 200, if desired.

For the extended pull-up output 160, the select input 210 is received by the NAND gate 260 along with the divider input 150. The output of the NAND gate 260 is received by a NOT gate 270, and the output of the NOT gate 270 is received by a NOR gate 280. NOR gate 280 also receives the pull-up output of D flip-flop 120. The result of the NOR gate 280 is NOT gated (NOT gate 290) to produce the pull-up output 160 of the phase frequency detector 100.

It should be noted that the embodiment of FIG. 2 extends the pulses of the pull-up output 160 and the pull-down bar output 170A, while similar devices with different strobe connections can provide pulse extension of the other outputs. The logic behind the embodiment shown in FIG. 2 is: the frequency divided output is OR'd with the pull-up output OR the pull-down bus bar output of the detector. Two select inputs are used to control which output is extended or expanded. If the pull-up output is extended or extended, the feedback will likewise extend or extend the other output (pull-down bus output) to compensate. In the same way, if the pulldown bus output is expanded, the pullup output will also be expanded to compensate. This arrangement introduces a DC phase offset and the loop is not locked at zero degrees phase offset but at an offset controlled by the divided pulse width. Thus, the phase frequency detector can operate in a more linear region.

It should further be noted that although fig. 2 shows two select inputs 200, 210, the present invention may be implemented with only one select input and only one of the output pulses is extended. Gates 220,240, 250 are not required if only the extended output pulse 160 is required to implement the present invention. Likewise, if only the extended output pulse 170A is needed, the gates 260, 270, 280, 290 are not needed. In both of these alternative embodiments, a single select input (either of select inputs 200, 210, as the case may be) will still extend the corresponding output pulse.

Referring to fig. 3, a novel D flip-flop structure that can be used in the phase frequency detector of fig. 2 is shown. The input 300 of the D flip-flop 310 is received by a NOT gate 320 (delay element) and the gate of a FET (field effect transistor) 330. The output of the NOT gate is received by the gate of FET 340. FET 340 has its source terminal connected to Vss 350 and its drain terminal connected to the source terminal of FET 330. The drain terminal of FET 330 is connected to the gate terminal of FET 360. The source terminal of FET 360 is connected to connection node 370 and the output 380 of D flip-flop 310 is taken from connection node 370. The source terminal of FET 390 is also connected to the drain terminal of FET 330. The drain terminal of FET 390 is connected to VDD 400. VDD 400 is also connected to a drain terminal of FET 360.

Connection node 370 serves as the connection point for the gate terminal of FET 390 and the drain terminal of reset FET 410. The gate terminal of the reset FET 410 receives the reset input of the D flip-flop 310, and its source terminal is connected to Vss 350.

In the phase frequency detector of fig. 2, the D flip-flop 310 of fig. 3 will receive the reference input 140 at the input terminal 300. The reference input is applied to FET 330 and a delayed, inverted version of the reference input is applied to FET 340. When the rising edge of the reference input occurs, FET 330 pulls the left side of the latch (the cross-coupled latch formed by FETs 390, 360) low. Then, to make the latch edge sensitive, the falling edge of the inverted input reference signal applied to FET 340 is lowered and the left branch of the latch is turned off.

It should be noted that as can be seen in fig. 3, FETs 330, 340, 410 are n-channel FETs and FETs 360, 390 are p-channel FETs. Although MOSFETs (metal oxide semiconductor field effect transistors) are contemplated for use, other types of FETs such as JFETs may also be used.

The D-type flip-flop in fig. 3 is sensitive only to the rising edge of the input and therefore only reacts to the rising edge. By adding FETs and gates, the flip-flop can react to both rising and falling edges of the input. This enables the use of lower input frequencies while achieving the performance of higher input frequencies.

Referring to fig. 4, a D-type flip-flop 500 is similar to that of fig. 3 except for the addition of branch delay elements (NOT gates) 510, 520 and FETs 530, 540. The delay element 510 receives the input 300 and the output of the NOT gate 510 is received by the gate terminal of the FET 540. The output of NOT gate 510 is also received by a delay element (NOT gate) 520, the output of delay element 520 being received by the gate terminal of FET 530. The source terminal of FET 530 is connected to relative ground (Vss)350, while the drain terminal of FET 530 is connected to the source terminal of FET 540. The drain terminal of FET 540 is connected to the drain terminal of FET 330.

The D flip-flop of fig. 4 may also be used in the phase frequency detector of fig. 2. The input frequency can be doubled using the D flip-flop of fig. 4. Thus, inputting the reference frequency n has the same effect as using the input frequency 2 n.

Alterations and modifications in the described structures and embodiments are contemplated as would normally occur to one skilled in the art to which the invention relates, and such alterations and modifications are intended to be covered by the scope of the invention as defined by the appended claims.

Claims (5)

1. A phase frequency detector circuit comprising:

a first D flip-flop receiving a reference input;

a second D flip-flop receiving a frequency division input;

a first NAND gate receiving a first select input and the divide input;

a first NOT gate receiving an output of the first NAND gate;

a NOR gate receiving an output of the first NOT gate and an output of the first D flip-flop;

a second NOT gate receiving the output of the NOR gate and producing a first output of the detector circuit;

a second NAND gate receiving the output of the first D flip-flop and an output of the second D flip-flop;

a third NOT gate receiving an output of the second NAND gate, the output of the third NOT gate being received as a reset input to the first and second D flip-flops.

2. A phase frequency detector circuit according to claim 1, further comprising:

a third NAND gate receiving a second select input and the divide input;

a fourth NAND gate receiving an output of the third NAND gate and an output of the second D flip-flop;

a fourth NOT gate receiving an output of the fourth NAND gate and generating a second output of the detector circuit.

3. A phase frequency detector circuit according to claim 1 wherein at least one of said first D flip-flop and said second D flip-flop comprises:

a first FET receiving an input signal at its gate terminal;

a delay element also receiving the input signal, the delay element outputting a delayed logical negation of the input signal;

a second FET receiving the output of the delay element at its gate terminal, the drain terminal of the second FET being connected to the source terminal of the first FET, the source terminal of the second FET being connected to relative ground;

a reset FET connected to said relative ground by a source terminal thereof, a drain terminal of said reset FET being connected to a connection node, a gate terminal of said reset FET being connected to an external reset input;

a third FET connected to the connection node by its source terminal, a drain terminal of the third FET connected to a power supply, a gate terminal of the third FET connected to the drain terminal of the first FET;

a fourth FET connected to the drain terminal of the first FET through a source terminal of the fourth FET, a drain terminal of the fourth FET being connected to the power supply, and a gate terminal of the fourth FET being connected to the connection node,

wherein

The output of the flip-flop is connected out from the connection node;

the first, second and reset FETs are of the same type; and

the third and fourth FETs are of the same type.

4. A phase frequency detector circuit according to claim 3 wherein at least one of said first D flip-flop and said second D flip-flop further comprises:

a first branch delay element receiving the input signal and outputting a delayed logical not of an output of the first branch delay element;

a fifth FET connected to the drain terminal of the first FET through a drain terminal of the fifth FET, a gate terminal of the fifth FET receiving an output of the first branch delay element;

a sixth FET connected to a fifth FET, a drain terminal of the sixth FET connected to a source terminal of the fifth FET, a source terminal of the sixth FET connected to the relative ground, a gate terminal of the sixth FET connected to an output of a second branch delay element, and an output of the first branch delay element received by the second branch delay element.

5. A phase frequency detector circuit according to claim 2 wherein said first and second select inputs determine which of said first and second outputs of said detector circuit output pulse is to be spread.