HK1193676B - Image sensor with fixed potential output transistor - Google Patents

Abstract

The present invention relates to an image sensor with fixed potential output transistor. An image sensor pixel includes a photosensitive region and pixel circuitry. The photosensitive region accumulates an image charge in response to light incident upon the image sensor. The pixel circuitry includes a transfer-storage transistor, a charge-storage area, an output transistor, and a floating diffusion region. The transfer-storage transistor is coupled between the photosensitive region and the charge-storage area. The output transistor has a channel coupled between the charge-storage area and the floating diffusion region and has a gate tied to a fixed voltage potential. The transfer-storage transistor causes the image charge to transfer from the photosensitive region to the charge-storage area and to transfer from the charge-storage area to the floating diffusion region.

Description

Image sensor with fixed potential output transistor

Technical Field

The present disclosure relates generally to image sensors, and particularly, but not exclusively, to image sensors having global shutters.

Background

Image sensors are ubiquitous. It is widely used in many different types of applications. In certain types of applications, such as the medical field, the size and image quality of the image sensor is of particular importance. Therefore, there is a need to minimize the image sensor without compromising image quality.

Fig. 1 is a circuit diagram illustrating a conventional shared pixel structure 100. The shared pixel structure 100 includes a pixel circuit 105 of two pixels located within an image sensor. Each pixel circuit 105 includes a photodiode region ("PD") and transistor circuitry that provides a variety of functionality for the conventional operation of each pixel. For example, pixel circuitry 105 may include circuitry to start accumulation of image charge within photodiode region PD, circuitry to reset image charge within photodiode region PD, circuitry to transfer image charge to a storage node ("MEM"), and circuitry to transfer image charge to a floating diffusion region ("FD"). To control this functionality, pixel circuitry 105 requires routing that takes up valuable space within each pixel at the expense of photodiode area PD. Adjusting this routing within each pixel reduces the area of the photodiode region PD exposed to light, thereby reducing the fill factor of the pixel and degrading pixel sensitivity and image quality.

Disclosure of Invention

One embodiment of the present invention provides an image sensor comprising an array of pixels, the image sensor comprising: a first photosensitive region of a first pixel disposed within or on a substrate layer to accumulate image charge in response to light incident on the first pixel; and first pixel circuitry of the first pixel disposed within or on the substrate layer, the first pixel circuitry comprising: a first transfer storage transistor coupled between the first photosensitive region and a first charge storage region to transfer the image charge from the first photosensitive region to the first charge storage region; and a first output transistor having a channel coupled between the first charge storage region and a floating diffusion region to selectively transfer the image charge from the first charge storage region to the floating diffusion region, wherein a gate of the first output transistor is coupled to a first fixed voltage potential and selectively transfers the image charge from the first charge storage region to the floating diffusion region in response to a control signal applied to the gate of the first transfer storage transistor.

One embodiment of the present invention provides a method of operating an image sensor, comprising: accumulating a first image charge on a first photosensitive region of a first pixel in response to light incident on the first photosensitive region; transferring the first image charge from the first photosensitive region to a first charge storage region by temporarily enabling a first transfer storage transistor coupled between the first photosensitive region and the first charge storage region; storing the first image charge within the first charge storage region; temporarily enabling a first output transistor having a gate coupled to a first fixed voltage potential by applying a first control signal to a gate of the first pass storage transistor; and transferring the first image charge from the first charge storage region to a floating diffusion region through the first output transistor while applying the first control signal to the gate of the first transfer storage transistor, wherein the first output transistor is coupled between the first charge storage region and the floating diffusion region.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles described.

Fig. 1 (prior art) is a circuit diagram illustrating a conventional shared pixel structure.

FIG. 2 is a functional block diagram illustrating an imaging system according to an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating adjacent pixels with shared pixel circuitry, each pixel including an output transistor having a gate connected to a fixed voltage potential, according to an embodiment of the invention.

Fig. 4 is a symbolic cross-sectional view of a pixel circuit including a gate connected to an output transistor at a fixed voltage potential, according to an embodiment of the invention.

FIG. 5 is a flow chart illustrating a method for operating an imaging system according to an embodiment of the present invention.

Fig. 6A to 6D illustrate various stages of charge transfer within a pixel including an output transistor having a gate connected to a fixed voltage potential, according to an embodiment of the present invention.

FIG. 7A is a timing diagram illustrating the operation of a global shutter image sensor according to an embodiment of the present invention.

FIG. 7B is a timing diagram illustrating the global transfer of image charge from the photosensitive region to the charge storage region according to an embodiment of the present invention.

Fig. 7C is a timing diagram illustrating progressive readout of image charges according to an embodiment of the present invention.

Detailed Description

Embodiments of systems and methods for operation of an image sensor are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 2 is a block diagram illustrating an imaging system 200 according to an embodiment of the present invention. The illustrated embodiment of imaging system 200 includes pixel array 205, readout circuitry 210, functional logic 215, and control circuitry 220.

Pixel array 205 is a two-dimensional ("2D") array of pixels (e.g., pixels P1, P2.., Pn). In one embodiment, each pixel is a complementary metal oxide semiconductor ("CMOS") imaging pixel. As illustrated, each pixel is arranged in rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to obtain image data of a person, place, or object, which can then be used to generate a 2D image of the person, place, or object.

After each pixel has obtained its image data or image charge, the image charge is read out by readout circuitry 210 and transferred to functional logic 215. The readout circuitry 210 may include amplification circuitry, analog-to-digital ("ADC") conversion circuitry, or others. Function logic 215 may simply store the image charge or even manipulate the image charge by applying a post-image effect (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 210 may readout a row of image charges at a time along readout column lines (bit lines) or may readout the image charges using a variety of other techniques (not illustrated), such as serial readout or readout of all pixels in parallel all at once.

Control circuitry 220 is coupled to pixel array 205 to control the operating characteristics of pixel array 205. For example, the control circuit 220 may generate a shutter signal to control image acquisition. In one embodiment, the shutter signal is a global shutter signal to enable all pixels within pixel array 205 to simultaneously capture their respective image charges during a single acquisition window. In an alternative embodiment, the shutter signal is a rolling shutter signal, whereby each row, column, or group of pixels is sequentially enabled during successive acquisition windows.

FIG. 3 is a circuit diagram 300 illustrating neighboring pixels 305 and 310 with shared pixel circuitry 315 according to an embodiment of the invention. Pixels 305 and 310 are one possible implementation of pixels within pixel array 205. Fig. 4 is a symbolic cross-sectional view of pixel circuit 400, which is an example implementation of a pixel in pixels 305 or 310.

The illustrated embodiments of pixels 305 and 310 each include a photosensitive region PS, a transfer-storage transistor TS, a transfer-storage gate signal line TSGS, a charge-storage area CSA, an output transistor OT having a gate 410 connected to a fixed potential (e.g., ground), and a global shutter transistor GS. The illustrated embodiment of circuit diagram 300 also includes voltage rails VDD and AVDD, reset signal line RSTS, global shutter signal line GSS, bit line 320, and local interconnect line 325, all of which are routed within a metal stack (not illustrated) present within pixel array 205. The metal stack may include one or more metal layers separated by intermetal dielectric layers. In one embodiment, the first metal layer includes lines oriented in a first direction within pixel array 205 (e.g., horizontally or vertically), while the second metal layer includes only lines oriented substantially perpendicular to the lines within the first metal layer. In another embodiment, the first metal layer includes local interconnect lines 325 that are oriented substantially perpendicular to other lines within the first metal layer, thereby reducing the number of lines included within the second metal layer. In one embodiment, the first metal layer includes a voltage rail VDD, a transfer storage gate signal line TSGS, a reset signal line RSTS, and a local interconnect line 325, and the second metal layer includes a voltage rail AVDD, a global shutter signal line GSS, and a bit line 320.

The illustrated embodiment of shared pixel circuit 315 includes a floating diffusion region FD, a readout transistor RO, and a reset transistor RST. Floating diffusion region FD is coupled between readout transistor RO and output transistor OT of pixels 305 and 310. Enabling output transistor OT couples floating diffusion region FD to charge-storage area CSA via output channel 405.

In one embodiment, the pixel circuit 400 is disposed on or within the substrate 415. In one embodiment, the substrate 415 is substantially comprised of silicon. In one embodiment, gate 410 and substrate 415 are P-type doped, while charge-storage area CSA and output channel 405 are N-type doped. In one embodiment, charge-storage area CSA and output channel 405 are lightly N-doped, while output transistor gate 410 is heavily P-doped and substrate 415 is lightly P-doped. In one embodiment, the source and drain of output transistor OT correspond to charge-storage area CSA and floating diffusion region FD, respectively. In other embodiments, all doping polarities may be reversed. In one embodiment, the output transistor OT is a depletion type junction gate field effect transistor having a negative threshold voltage. In one embodiment, the gate 410 is spaced from the floating diffusion region FD by more than 0.18 μm.

FIG. 5 is a flow chart illustrating a process 500 for operating the image system 200 according to an embodiment of the present invention. The process 500 is described with reference to fig. 6A-6D. The order in which some or all of the process blocks appear in process 500 should not be construed as limiting. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that some of the process blocks may be performed in a variety of orders not illustrated.

In process block 505, image charge is accumulated within photosensitive region PS in response to light incident on photosensitive region PS (see fig. 6A). In one embodiment, incident photons of incident light induce photo-regeneration of charge carriers that are subsequently accumulated as image charge. In a global shutter image sensor, integration occurs for all pixels in the pixel array 205 at the same time.

In a process block 510, image charge is transferred from photosensitive region PS to charge-storage area CSA by enabling transfer-storage transistor TS (see FIG. 6B). In one embodiment, the transfer storage transistor is enabled by applying a positive voltage signal to the transfer storage transistor TS, thereby increasing the voltage potential between the gate of the transfer storage transistor TS and the photosensitive region PS to be greater than the threshold voltage of the transfer storage transistor TS. In one embodiment, the threshold voltage of pass memory transistor TS ranges from 0.5 to 0.8 volts. Enabling transfer-storage transistor TS couples photosensitive region PS to charge-storage area CSA. In the case of a global shutter image sensor, the corresponding transfer storage transistor TS for each pixel within pixel array 205 is simultaneously enabled. This results in the global transfer of each pixel's corresponding image charge from its corresponding photosensitive area PS into its corresponding charge-storage area CSA.

In process block 515, image charge is stored within charge-storage area CSA (see fig. 6C). The signal applied to the pass storage transistor TS is deasserted, thereby disabling the pass storage transistor TS. Deactivating transfer-storage transistor TS decouples photosensitive region PS from charge-storage area CSA and isolates image charge within charge-storage area CSA.

In process block 520, isolated image charges within charge-storage area CSA are transferred to floating diffusion region FD (see fig. 6D) row by row within pixel array 205. Each transfer memory transistor TS located within a selected row of pixels in the pixel array 205 receives a negative voltage signal via the transfer memory gate signal line TSGS. This results in a decrease in the voltage potential of charge-storage area CSA. The decrease in the voltage potential of charge-storage area CSA increases the voltage potential between output transistor gate 410 (which is connected to a fixed potential) and charge-storage area CSA until the threshold voltage of output transistor OT is reached, thereby enabling output transistor OT and transferring image charge to floating diffusion region FD via output channel 405. Thus, the transfer of image charge from charge-storage area CSA to floating diffusion region FD through output transistor OT is controlled via a control signal received at transfer-storage transistor TS from transfer-storage signal gate line TSGS (rather than via the selective application of a control signal to gate 410). Thus, this reduces the number of lines that need to be routed within the metal stack of pixel array 205 and increases the fill factor of each pixel. In one embodiment, the threshold voltage of the output transistor OT ranges from-0.6 to-0.2 volts. In one embodiment, the voltage applied to the gate of pass storage transistor TS to enable output transistor OT ranges from-3.0 to-1.5 volts.

In process block 525, the image charges are read out on bit lines 320 row by row. As illustrated in fig. 3, the gate of the read transistor RO is coupled to the floating diffusion region FD, while the read transistor RO terminal is coupled to the voltage rail AVDD and the bit line 320. When the image charge is transferred to the gate of the readout transistor RO (i.e., at the floating diffusion region FD), the readout transistor RO generates a signal indicating that the image charge reaches the readout circuit 210 via the bit line 320. In one embodiment, image charge from pixel 305 is read out during one row readout while image charge from pixel 310 is read out during a separate row readout.

Fig. 7A is a timing diagram illustrating the operation of the imaging system 200 according to an embodiment of the present invention. Fig. 7A illustrates one possible implementation of the timing of one frame (i.e., frame 2) of the imaging system 200. In the present invention, a frame is the time allotted for both capturing the image charge in each pixel within pixel array 205 and reading out the image charge captured during the preceding frame. As illustrated, operation of imaging system 200 includes an integration phase 705 in which image charge is accumulated in photosensitive region PS of each pixel within pixel array 205. Prior to the integration phase 705, the voltage potential of the photosensitive region PS of each pixel within the pixel array 205 is reset to a fixed potential (photosensitive region reset 700). Similarly, after integration 705, the voltage potential of charge-storage area CSA for each pixel within pixel array 205 is reset (global pixel reset 710) before image charge collected during integration phase 705 is transferred to charge-storage area CSA (global transfer 715). The image charge transferred to charge-storage area CSA remains there until it is read out during the next frame (i.e., frame 3). While the image charges are accumulated during the integration 705, the image charges captured during the preceding frame (i.e., frame 1) are read out to the readout circuit 210 row by row (row-by-row readout 720).

FIG. 7B is a timing diagram illustrating a global pixel reset 710 and a global transfer 715, according to an embodiment of the invention. FIG. 7B illustrates one possible implementation of a global pixel reset 710 and a global transfer 715. In one embodiment, global pixel reset includes charging or discharging charge-storage area CSA to a predetermined voltage potential, such as VDD. Reset is achieved by enabling the output transistor OT by applying a negative voltage to the transfer storage transistor TS and applying a positive voltage signal to enable the reset transistor RST. Enabling output transistor OT and reset transistor RST simultaneously couples voltage rail VDD, floating diffusion region FD, and charge-storage area CSA, thereby resetting charge-storage area CSA to the voltage potential of VDD. After charge-storage area CSA is reset, the signal applied to reset transistor RST is deasserted, thereby disabling reset transistor RST and decoupling voltage rail VDD from floating diffusion FD.

Global transfer 715 occurs after global pixel reset 710, wherein image charge accumulated within photosensitive region PS during integration 705 is simultaneously transferred to charge-storage area CSA for each pixel within pixel array 205. As illustrated in fig. 7B, the transfer memory transistor TS receives a positive voltage signal via the transfer memory gate signal line TSGS. This enables transfer-storage transistor TS and transfers image charge from photosensitive region PS to charge-storage area CSA. After the transfer is completed, the transfer memory transistor TS receives the intermediate voltage signal via the transfer memory gate signal line TSGS. The intermediate voltage signal is less than the threshold voltage of transfer-storage transistor TS, thereby disabling transfer-storage transistor TS and decoupling photosensitive region PS from charge-storage area CSA. However, the intermediate voltage signal is not a negative number small enough to enable the output transistor OT. With both transfer-storage transistor TS and output transistor OT disabled, the image charge remains isolated in charge-storage area CSA. In one embodiment, the intermediate voltage signal is 0.4 volts below the threshold voltage of the output transistor OT.

Fig. 7C is a timing diagram illustrating row-by-row readout 720 according to an embodiment of the present invention. Fig. 7C is one possible implementation of row-by-row readout 720. In the illustrated embodiment, the row-by-row readout 720 is implemented using correlated double sampling ("CDS"). Before reading out image data from a row of pixels within pixel array 205, floating diffusion region FD for each pixel within a selected row is reset. Resetting includes charging or discharging the floating diffusion region FD to a predetermined voltage potential (e.g., VDD), and is accomplished by enabling the reset transistor RST. Enabling reset transistor RST couples voltage rail VDD to floating diffusion region FD.

CDS requires two readouts per pixel for readout circuitry 210: dark current read DRK and image signal read SIG. Dark current reading DRK is performed to measure the voltage potential at the floating diffusion region FD without image charge. After transferring the image charge to floating diffusion region FD, image signal read SIG is performed to measure the voltage potential at floating diffusion region FD in the presence of the image charge. Subtracting the dark current read DRK measurement from the image signal read SIG measurement results in a reduced noise value indicative of the image charge at the floating diffusion region FD.

Prior to image signal read SIG, image charge is transferred from charge-storage area CSA to floating diffusion region FD via output channel 405. To achieve this, the transfer memory transistor TS receives a negative voltage signal via the transfer memory gate signal line TSGS, which enables the output transistor OT. After the image charge is transferred to the floating diffusion region FD, the transfer storage transistor TS receives an intermediate voltage signal via a transfer storage gate signal line to disable the output transistor OT and isolate the image charge within the floating diffusion region FD. The intermediate voltage signal is applied until after the image signal read SIG is completed.

The processes explained above are described in terms of computer software and hardware. The described techniques may include machine-executable instructions embodied in a tangible or non-transitory machine (e.g., computer) readable storage medium that, when executed by a machine, cause the machine to perform the operations described. Further, the processes may be embodied within hardware, such as an application specific integrated circuit ("ASIC") or otherwise.

A tangible machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processes, etc.). For example, a machine-readable storage medium includes recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

The above description of illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Indeed, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (18)

1. An image sensor comprising an array of pixels, the image sensor comprising:

a first photosensitive region of a first pixel disposed within or on a substrate layer to accumulate image charge in response to light incident on the first pixel; and

a first pixel circuit of the first pixel disposed within or on the substrate layer, the first pixel circuit comprising:

a first transfer storage transistor coupled between the first photosensitive region and a first charge storage region to transfer the image charge from the first photosensitive region to the first charge storage region; and

a first output transistor having a channel coupled between the first charge storage region and a floating diffusion region to selectively transfer the image charge from the first charge storage region to the floating diffusion region, wherein a gate of the first output transistor is coupled to a first fixed voltage potential and selectively transfers the image charge from the first charge storage region to the floating diffusion region in response to a control signal applied to a gate of the first transfer storage transistor, wherein the first output transistor is a junction gate field effect transistor.

2. The image sensor of claim 1, wherein the first pixel circuit further comprises:

a readout transistor having a gate coupled to the floating diffusion region to generate an image signal on a bit line indicative of the image charge at the floating diffusion region; and

a reset transistor coupled between a first voltage rail and the floating diffusion region to reset the first pixel.

3. The image sensor of claim 2, further comprising a second pixel disposed adjacent to the first pixel, the second pixel comprising:

a second photosensitive region; and

a second pixel circuit of the second pixel disposed within or on the substrate layer, the second pixel circuit comprising:

a second transfer storage transistor coupled between the second photosensitive region and a second charge storage region; and a second output transistor having a channel coupled between the second charge storage region and the floating diffusion region, wherein a gate of the second output transistor is coupled to a second fixed voltage potential,

wherein the first and second pixels share the readout and reset transistors.

4. The image sensor of claim 3, further comprising:

a first global shutter transistor coupled between a second voltage rail and the first photosensitive region to reset the first photosensitive region; and

a second global shutter transistor coupled between the second voltage rail and the second photosensitive region to reset the second photosensitive region.

5. The image sensor of claim 4, wherein a gate of the first global shutter transistor and a gate of the second global shutter transistor are coupled to a global shutter signal line to reset the first and second photosensitive regions simultaneously.

6. The image sensor of claim 3, wherein the gates of the first and second output transistors are coupled to the substrate layer to ground the gates of the first and second output transistors.

7. The image sensor of claim 3, further comprising a local interconnect coupling the first output transistor to the second output transistor, wherein the local interconnect is coupled to the floating diffusion region.

8. The image sensor of claim 7, further comprising a metal stack to route signals, wherein the metal stack comprises:

a first metal layer comprising conductors, wherein a majority of the conductors are parallel to each other; and

a second metal layer comprising conductors, wherein the conductors are both parallel to each other within the second metal layer and perpendicular to a majority of the conductors within the first metal layer,

wherein the local interconnect is disposed within the metal stack such that the local interconnect is perpendicular to a majority of the conductor within the first metal layer in which the local interconnect is disposed.

9. The image sensor of claim 3, the pixel array further comprising:

a first set of conductors spanning rows of the pixel array, the first set of conductors comprising:

a first pass storage transistor gate signal line coupled to the first pass storage transistor;

a second pass storage transistor gate signal line coupled to the second pass storage transistor;

a reset signal line coupled to a gate of the reset transistor; and

the first voltage rail coupled to the gate of the reset transistor;

a second set of conductors spanning columns of the pixel array, the second set of conductors comprising:

the bit line coupled to the readout transistor to send the image signal to a readout circuit;

a second voltage rail coupled to the readout transistor and to first and second global shutter transistors;

and

a global shutter signal line coupled to gates of the first and second global shutter transistors to provide a photosensitive reset signal.

10. An image sensor comprising an array of pixels, the image sensor comprising:

a first photosensitive region of a first pixel disposed within or on a substrate layer to accumulate image charge in response to light incident on the first pixel; and

a first pixel circuit of the first pixel disposed within or on the substrate layer, the first pixel circuit comprising:

a first transfer storage transistor coupled between the first photosensitive region and a first charge storage region to transfer the image charge from the first photosensitive region to the first charge storage region; and

a first output transistor having a channel coupled between the first charge storage region and a floating diffusion region to selectively transfer the image charge from the first charge storage region to the floating diffusion region, wherein a gate of the first output transistor is coupled to a first fixed voltage potential and selectively transfers the image charge from the first charge storage region to the floating diffusion region in response to a control signal applied to a gate of the first transfer storage transistor,

wherein:

the first transfer storage transistor is coupled to transfer the image charge from the first photosensitive region to the first charge storage region in response to a first voltage level of the control signal,

the first transfer storage transistor is coupled to store the image charge within the first charge storage region in response to a second voltage level of the control signal,

the first transfer storage transistor is coupled to transfer the image charge from the first charge storage region to the floating diffusion region in response to a third voltage level of the control signal, and

the second voltage level is between the first and third voltage levels of the control signal.

11. A method of operating an image sensor, comprising:

accumulating a first image charge on a first photosensitive region of a first pixel in response to light incident on the first photosensitive region;

transferring the first image charge from the first photosensitive region to a first charge storage region by temporarily enabling a first transfer storage transistor coupled between the first photosensitive region and the first charge storage region;

storing the first image charge within the first charge storage region;

temporarily enabling a first output transistor having a gate coupled to a first fixed voltage potential by applying a first control signal to a gate of the first pass storage transistor;

transferring the first image charge from the first charge storage region to a floating diffusion region through the first output transistor while the first control signal is applied to the gate of the first transfer storage transistor, wherein the first output transistor is coupled between the first charge storage region and the floating diffusion region;

enabling the first pass storage transistor by applying a first voltage level of the first control signal to the first pass storage transistor;

storing the first image charge within the first charge storage region by applying a second voltage level of the first control signal to the first transfer storage transistor; and

enabling the first output transistor by applying a third voltage level of the first control signal to the first pass storage transistor,

wherein the second voltage level is between the first and third voltage levels.

12. The method of claim 11, further comprising:

generating a signal on a bit line indicative of the first image charge at the floating diffusion region; and

the first pixel is reset by temporarily enabling a reset transistor coupled between the floating diffusion region and a first voltage rail.

13. The method of claim 12, further comprising:

accumulating a second image charge on a second photosensitive region of a second pixel;

transferring the second image charge from the second photosensitive region to a second charge storage region;

storing the second image charge within the second charge storage region; and

temporarily enabling a second output transistor having a gate coupled to a second fixed voltage potential by applying a second control signal to the gate of the second pass storage transistor; and

transferring the second image charge from the second charge storage region to a floating diffusion region through the second output transistor while the second control signal is applied to the gate of the second transfer storage transistor, wherein the second output transistor is coupled between the second charge storage region and the floating diffusion region.

14. The method of claim 13, further comprising:

resetting the first photosensitive region by temporarily enabling a first global shutter transistor coupled between a second voltage rail and the first photosensitive region; and

resetting the second photosensitive region by temporarily enabling a second global shutter transistor coupled between the second voltage rail and the second photosensitive region.

15. The method of claim 14, further comprising resetting both the first photosensitive region and the second photosensitive region by simultaneously applying a reset signal to both a gate of the first global shutter transistor and a gate of the second global shutter transistor, wherein the gate of the first global shutter transistor is coupled to the gate of the second global shutter transistor.

16. The method of claim 13, wherein the gates of the first and second output transistors are coupled to a substrate layer to ground the gates of the first and second output transistors.

17. The method of claim 13, further comprising:

transferring a subsequent first image charge from the first charge storage region to the floating diffusion region while the first image charge is accumulated within the first photosensitive region; and

transferring a subsequent second image charge from the second charge storage region to the floating diffusion region while the second image charge is accumulated within the second photosensitive region.

18. An image sensor comprising an array of pixels, the image sensor comprising:

a first photosensitive region of a first pixel disposed within or on a substrate layer to accumulate image charge in response to light incident on the first pixel;

a first pixel circuit of the first pixel disposed within or on the substrate layer, the first pixel circuit comprising:

a first transfer storage transistor coupled between the first photosensitive region and a first charge storage region to transfer the image charge from the first photosensitive region to the first charge storage region; and

a first output transistor having a channel coupled between the first charge storage region and a floating diffusion region to selectively transfer the image charge from the first charge storage region to the floating diffusion region, wherein a gate of the first output transistor is coupled to a first fixed voltage potential and selectively transfers the image charge from the first charge storage region to the floating diffusion region in response to a control signal applied to a gate of the first transfer storage transistor;

a second pixel disposed adjacent to the first pixel, the second pixel comprising a second photosensitive region and second pixel circuitry of the second pixel, the second pixel circuitry disposed within or on the substrate layer, the second pixel circuitry comprising:

a second transfer storage transistor coupled between the second photosensitive region and a second charge storage region; and a second output transistor having a channel coupled between the second charge storage region and the floating diffusion region, wherein a gate of the second output transistor is coupled to a second fixed voltage potential, wherein the readout and reset transistors are shared by the first and second pixels;

a local interconnect coupling the first output transistor to the second output transistor, wherein the local interconnect is coupled to the floating diffusion region; and

a metal stack to route signals, wherein the metal stack comprises:

a first metal layer comprising conductors, wherein a majority of the conductors are parallel to each other; and

a second metal layer comprising conductors, wherein the conductors are both parallel to each other within the second metal layer and perpendicular to a majority of the conductors within the first metal layer,

wherein the local interconnect is disposed within the metal stack such that the local interconnect is perpendicular to a majority of the conductor within the first metal layer in which the local interconnect is disposed.