HK1191724A - Five transistor sram cell - Google Patents

Abstract

A five transistor static random-access-memory (SRAM) cell is disclosed which can be made part of an SRAM array to provide an improved reduction in size. The cell includes two cross-coupled inverters, each having two complementary transistors, and an n-channel transistor switch connected to a bit line (BL) and a word line (WL). The p-channel element of one of the inverters is connected to a power supply, and the p-channel transistor of the other inverter is coupled to a write bit line (WBL). By varying the voltage levels on the BL and WBL lines the biasing of the individual n-channel transistors of each of the inverters can be changed based on the data to be written to the cell. Various biasing systems are presented such that the SRAM cell memory state can be changed without requiring larger transistor elements to overpower the cell state.

Description

Five transistor SRAM cell

Technical Field

The present disclosure relates to a static read-write memory (SRAM) cell, and more particularly, to a five-crystal SRAM cell.

Background

Random Access Memory (RAM) cells are semiconductor memories used to store information in a single bit value. A Static Random Access Memory (SRAM) cell is a type of RAM cell that stores a bit value using a bi-stable latch circuit formed from a pair of cross-coupled inverters. The bistable latching circuit includes four transistors, but requires additional transistors such as access transistors to enable the memory controller to read the contents of the cell and write data to the cell.

SRAM cells may be connected together to form an array. In the ever shrinking modern electronic world, SRAM arrays are convenient because a large number of SRAMs can be deployed in a smaller physical space than isolated SRAM cells operating independently. SRAM arrays are typically designed with many individual SRAM cells connected in a grid with one individual SRAM cell being used as part of an addressable row and column system. Since any particular cell value can be accessed at any particular time as long as the row and column addresses are associated with a single SRAM cell, the memory controller, in conjunction with the memory driver circuitry, can read and/or write to the SRAM array in a random manner.

Because the SRAM cell has the ability to hold a bit value, changing the cell bit value may include various processes aimed at overcoming some of the latch-up circuit transistor states by utilizing the access transistor. To overcome this access transistor state, additional power is required, which results in an undesirable increase in size. The additional access transistors and the increased access transistor size limit further reductions in the physical size of the SRAM array.

Disclosure of Invention

Disclosed herein is a semiconductor memory including: a first inverter and a second inverter cross-coupled to each other; an access switch coupled to an input of the first inverter; a first control line coupled to the access switch; and a second control line coupled to the second inverter; wherein the first inverter and the second inverter are configured to be unequally biased in response to the first control line being driven above a reference voltage and the second control line being driven below the reference voltage.

Preferably, the access switch is an access transistor.

Preferably, the first inverter and the second inverter each include a first p-channel transistor and a second n-channel transistor.

Preferably, the access transistor, the first p-channel transistor and the second n-channel transistor are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

Preferably, the reference voltage is a power supply voltage of the semiconductor memory.

Preferably, the first control line is a Bit Line (BL) and the second control line is a Write Bit Line (WBL).

Preferably, the semiconductor memory further comprises: a third control line coupled to the access transistor, wherein the third control line is a Word Line (WL) configured to control a conduction mode of the access transistor.

Preferably, the first p-channel transistor of the first inverter or the second inverter is coupled to the write bit line.

Preferably, the bit line is driven above the reference voltage and the write bit line is driven substantially simultaneously below the reference voltage to facilitate the write operation.

Also disclosed herein is a semiconductor memory including: a first inverter and a second inverter cross-coupled to each other; the first inverter has a first p-channel transistor coupled to the power supply line and a first n-channel transistor; the second inverter has a second p-channel transistor coupled to the Write Bit Line (WBL) and a second n-channel transistor; the first p-channel transistor and the first n-channel transistor are both coupled to an access transistor, which is coupled to a Bit Line (BL).

Preferably, the first n-channel transistor and the second n-channel transistor are configured to be unequally biased in response to the write bit line being driven below a supply voltage and the bit line being driven above the supply voltage.

Preferably, the semiconductor memory further comprises: a third control line coupled to the access transistor, wherein the third control line is a Word Line (WL) configured to control a conduction mode of the transistor.

Preferably, the first n-channel transistor, the second n-channel transistor, the first p-channel transistor, the second p-channel transistor, and the access transistor are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

Preferably, the write bit line is driven below the supply voltage and the bit line is driven substantially simultaneously above the supply voltage to facilitate the write operation.

Also disclosed herein is a semiconductor memory including: a first inverter and a second inverter cross-coupled to each other; a first port having a plurality of control lines; a second port having a plurality of control lines; the first inverter has a first p-channel transistor and a first n-channel transistor both coupled to the first port; and a second inverter having a second p-channel transistor and a second n-channel transistor both coupled to the second port; wherein the first n-channel transistor and the second n-channel transistor are configured to be unequally biased in response to a portion of the plurality of control lines associated with the first port being driven above a supply voltage and a portion of the plurality of control lines associated with the first port being driven below the supply voltage.

Preferably, the plurality of control lines comprises: a Write Bit Line (WBL); a Bit Line (BL); and a Word Line (WL).

Preferably, each of the first port and the second port further comprises: an access transistor coupled to the respective inverter, wherein a bit line and a word line are coupled to the access transistor, the word line being configured to control a conduction mode of the access transistor.

Preferably, the write bit line is driven below the supply voltage and the bit line is driven substantially simultaneously above the supply voltage to facilitate the write operation.

Preferably, the first port and the second port are from among a plurality of ports each having a plurality of control lines, and a part of the plurality of ports share the write bit line.

Preferably, the plurality of ports are configured to enable shared access to the semiconductor memory among the plurality of devices.

Drawings

FIG. 1 shows a block diagram of a memory module according to an example embodiment of the present disclosure.

FIG. 2 shows a schematic diagram of a five transistor SRAM cell according to an exemplary embodiment of the present disclosure.

FIG. 3A illustrates a timing diagram of a five transistor SRAM cell performing a read operation in accordance with an exemplary embodiment of the present disclosure.

FIG. 3B illustrates a timing diagram for performing a write operation to a five transistor SRAM cell in accordance with an exemplary embodiment of the present disclosure.

FIG. 4 shows an array schematic of a five transistor SRAM cell according to an exemplary embodiment of the present disclosure.

FIG. 5 illustrates a graphical representation of the Static Noise Margin (SNM) of an SRAM cell in accordance with an exemplary embodiment of the present disclosure.

FIG. 6 shows a schematic diagram of a six transistor dual port bit cell according to an example embodiment of the present disclosure; and

fig. 7 shows a schematic diagram of an eight transistor four port bit cell according to an exemplary embodiment of the present disclosure.

The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.

Detailed Description

The following detailed description refers to the accompanying drawings in order to illustrate example embodiments of the disclosure. Reference in the detailed description to "one exemplary embodiment," "an exemplary embodiment of an example" or the like is intended to mean that the exemplary embodiment may include a particular feature, structure, or characteristic, but not all exemplary embodiments necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described.

The exemplary embodiments described herein are illustrative only and not limiting. Other exemplary embodiments are possible, and modifications to the exemplary embodiments are also possible within the spirit and scope of the present disclosure. Accordingly, this detailed description is not intended to limit the disclosure. Rather, the scope of the disclosure is limited only by the claims and equivalents thereof.

Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the disclosure may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include Read Only Memory (ROM); random Access Memory (RAM), magnetic disk storage media; an optical storage medium; a flash memory device; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, programs, and instructions may be described herein as performing certain actions. However, it is to be understood that such description is merely for convenience and that such action in fact results from a computing device, processor, controller, or other device executing the firmware, software, programs, instructions, etc.

The following detailed description of the exemplary embodiments will fully reveal the general nature of the disclosure so that others skilled in the art, with the benefit of this disclosure, can, by applying appropriate experimentation, readily modify and/or adapt for various applications such exemplary embodiments without undue experimentation, without departing from the spirit and scope of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning of exemplary embodiments and a number of equivalents based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings herein.

Unless otherwise indicated, the drawings provided throughout this disclosure should not be understood as being drawn to scale. More specifically, the timing diagrams may be exaggerated and/or discontinuous to provide a better depiction of example embodiments. Such exaggeration and/or non-continuity may also vary between axes, steps and/or individual elements to more clearly demonstrate the concept of the exemplary embodiments.

The logic levels and/or default voltage states are provided for exemplary purposes only. Those skilled in the art will appreciate that the logic levels may be reversed such that the assertion transistors use either an active low or active high logic scheme. Similarly, default, pull-up and/or pull-down voltage states may be modified to accommodate suitable logic implementations. The transition of a data line from one state to another should not be interpreted as the previous state being a default, standard, static, and/or unchanging state.

Although the description of the present disclosure is in terms of an SRAM, those skilled in the art will appreciate that the present disclosure is applicable to other types of memories without departing from the spirit and scope of the present disclosure. For example, although the present disclosure is described using an SRAM memory controller and an SRAM memory driver, those skilled in the art will appreciate that the functionality of these SRAM storage devices may be applied to other memory devices using additional types of memory (such as DRAM, or non-volatile memory) without departing from the spirit and scope of the present disclosure.

Exemplary memory interface

FIG. 1 shows a block diagram of a memory module according to an example embodiment of the present disclosure. The memory module 100 includes a memory controller 102, a memory interface 104, and a memory 106. For example, memory controller 102 may include a processor, CPU, Application Specific Integrated Circuit (ASIC), or priority controller. For example, the memory interface 104 may include decoder circuits, memory drivers, buffers, and/or latches configured to address, access, write, and/or read data to and from the memory 106. The memory interface 104 communicates with the memory controller 102 through the memory bus 101. For example, any, some, or all of the functions of the memory interface 104 may be integrated as part of the memory controller 102 to facilitate direct communication and control of the memory 106 from the memory controller 102.

The memory interface 104 is connected to the memory 106 using control lines 103. Based on the communication with the memory controller 102, the memory interface 104 may drive the control lines 103 to different voltage levels. The memory controller 102 and/or the memory interface 104 may dynamically change the voltage levels of any, some, or all of the control lines 103 relative to each other, or hold any, some, or all of the control lines 103 at a static, unchanging value for any length of time. The voltage level state of the control lines 103 allows the memory controller 102 to read data from the memory 106 and write data to the memory 106.

Exemplary five transistor SRAM cell

FIG. 2 shows a schematic diagram of a five transistor SRAM cell in accordance with an exemplary embodiment of the present disclosure. The five-transistor SRAM cell 200 is formed by a pair of cross-coupled inverters 202 and 204 and an access switch represented by a single N-channel access transistor N2. The individual SRAM cells 200 may represent an exemplary embodiment of the memory 106. Inverter 202 includes a P-channel transistor P0 and an N-channel transistor N0 having an input node Q and an output node QN. Inverter 204 includes a P-channel transistor P1 and an N-channel transistor N1 having an input node QN and an output node Q. Access transistor N2 controls access to node Q to read and write a data bit represented by the voltage level of node Q to node Q. Although the transistors shown in fig. 2 are represented as MOSFET transistors, it should be noted that the present disclosure is not limited thereto. The SRAM cell 200 may be implemented using various types of transistors or any other type of switching devices as would be apparent to one skilled in the art without departing from the spirit and scope of the present disclosure.

The access transistor N2 is connected to a Bit Line (BL) and a Word Line (WL). The word line is asserted to either transfer the voltage of node Q to BL for reading the Q data bit or to transfer the voltage of BL to node Q for writing the Q data bit. The transistor P0 is connected to a Write Bit Line (WBL) for performing a write operation along with WL and BL. BL, WL, and WBL may represent exemplary embodiments of control lines 103.

For example, when the gate voltage of node Q is a low voltage such as logic 0, transistor P0 is turned on, whereby, provided WBL is at a sufficiently high voltage (such as Vdd, logic 1, or a value that deviates from Vdd), the voltage of WBL is substantially transmitted to node QN, causing a drain-source current to flow through P0. For example, when the gate voltage of the node QN is a low voltage such as logic 0, the transistor P1 is turned on, and thus the power supply voltage Vdd is substantially transmitted to the node Q. Transistor N0 turns on when a positive gate voltage Q is applied to the gate, thereby discharging node QN to ground (logic 0). Transistor N1 turns on when the positive gate voltage of node QN is applied to the gate, thereby discharging node QN to ground (logic 0).

Since the voltage at node Q is transmitted to BL, access transistor N2 is connected to node Q and can read the Q data bit when WL is asserted. When WL is asserted, access transistor N2 is turned on, transmitting the BL voltage to node Q for writing the data bit. For example, when reading a Q data bit, the memory controller 102 may configure the BL as an input to the memory interface 104, and when the memory controller 102 writes a Q data bit, the memory controller 102 may configure the BL as an output to the memory interface 104. The memory interface 104 may be configured (for purposes of providing an example) as a bi-directional buffer circuit.

The WBLs can be driven independently by BL and WL. More specifically, for example, the WBL may be held at a high voltage level (such as a logic 1), i.e., substantially static for read operations. For example, the WBL may also be held at a high voltage level (such as a logic 1) when the SRAM cell 200 is in a "hold" state in which data cannot be read from or written to the SRAM cell 200. Further, for example, when the memory controller 102 performs a write operation, the WBL is driven to a voltage level that deviates from a high voltage level (such as a logic 1 or Vdd).

For example, the SRAM cell 200, the memory controller 102, and/or the memory interface 104 may be implemented as part of a single Integrated Circuit (IC), a semiconductor die, a chip, and/or integrated as part of a Printed Circuit Board (PCB) design. Further, any, some, or all of the SRAM cell 200, the memory controller 102, and/or the memory interface 104 may be implemented as separate and/or external components relative to each other.

For example, although the Q and QN data bits are described as digital values, it should be noted that there may be transitional states during state transitions where the values of nodes Q and QN will change between logic high and logic low values. The voltage levels at nodes Q and/or QN may also deviate from the power supply Vdd (logic high) and ground (logic low) to voltage levels within and outside the logic level voltage boundaries. Further, although the SRAM cell 200 is a digital memory storage system, the voltage levels of WBL, BL, WL, and/or Vdd may be analog values. Any, some, or all of WBL, BL, WL, and/or Vdd may be varied, pulsed, strobed (strobe), and/or held constant.

Timing diagram for an exemplary read operation

FIG. 3A illustrates a timing diagram for performing a read operation from a five transistor SRAM cell according to an exemplary embodiment of the present disclosure. Timing diagram 300 illustrates the timing of different voltage levels for performing a read operation from SRAM cell 200. Referring to fig. 2, the voltage levels of WL, Q data, and BL are shown. For example, the WBL lines are not shown in fig. 3A because the state of the WBL may be maintained at a substantially constant value (such as a logic 1) so as not to affect the state of the SRAM cell 200 during a read operation. More specifically, as long as the voltage of WBL remains above the threshold voltage of transistor N1 and does not drop to a level low enough that P0 is no longer conductive due to a lack of drain-source current flowing through P0, the state of SRAM cell 200 will remain stable during a read operation. For example, the WBL may be set to a default voltage level by the memory controller 102 and/or the memory interface 104 such that there is sufficient drain-to-source current at P0 when a low voltage (such as a logic 0) is provided at the gate of P0.

The data read step 302 shows the timing and voltage levels corresponding to the SRAM cell 200 having a Q data bit logic value of 0. For example, in the data read step 302, the BL line is precharged to Vdd and WL is driven to a high value such as a logic 1, which turns on the access transistor N2 for a period of time. As shown by the approximate exponential decay of the precharge voltage at BL in fig. 3A, BL discharges to ground through N2 and N1 during the time frame that access transistor N2 is turned on. After the memory controller 102 completes the data read step, the BL is precharged to Vdd in anticipation of the next data read. During the brief period of BL discharge, the Q value increases slightly before falling back to ground due to the increased voltage introduced by the precharged BL voltage.

The "data read" line represents the SRAM cell 200 data value read by the memory controller 102 during the data read step 302. For example, although the BL value may discharge in a manner that does not drop to ground, the memory controller 102 and/or the SRAM cell 200 may be configured to provide sufficient time to allow the BL to discharge sufficiently to a threshold representing a logic 0. Also for example, sense amplifiers may be used to detect differences between the Q data bit values and the reference values, thereby speeding up the ability of the memory controller 102 to detect the Q data bit values. The data read operation is represented by the transition of the "data read" line from logic 1 (Vdd) to logic 0 (GND).

The data read step 304 shows the timing and voltage levels corresponding to the SRAM cell 200 having a Q logic value of 1. In this case, WL is again driven high and BL is precharged to Vdd. However, since BL has been charged to Vdd and P1 turned on, BL briefly floats to a slightly lower voltage level representing the additional impedance introduced by turning on N2, which temporarily reduces the current through the combination of P1 and N2 from Vdd. The "data read" line reflects the value of the SRAM cell 200 as shown by the transition from logic 0 to logic 1.

Timing diagram for exemplary write operations

Fig. 3B shows a timing diagram for performing a write operation to a five transistor SRAM cell according to an example embodiment of the present disclosure. Timing diagram 350 illustrates the timing of various voltage levels for writing data to SRAM cell 200. Referring to FIG. 2, the voltage levels of WL, Q/QN data, BL, and WBL are shown.

The data write step 352 shows the timing and voltage levels corresponding to the memory controller 102 writing a 0 to the SRAM cell 200. During the data write step 352, the WL is driven to turn on N2. Assuming that the previous data value stored in the SRAM cell 200 is 1, the transistors P1 and N0 are turned on before the data write step 352, and the transistors P0 and N1 are turned off before the data write step 352.

For example, to rewrite a logic value 1 stored in the SRAM cell 200 to a logic value 0, the BL is driven to a low voltage such as logic 0 while the WL is asserted. To write a logic 0 to the SRAM cell 200, the value of the Q node must drop until transistor N0 is turned off and transistor P0 is turned on. Thus, during the data write step 352, transistors P1 and N2 compete as transistor P1 turns on pulling the voltage of the Q node up to Vdd and N2 turns on pulling the voltage of the Q node down to the BL voltage. Because the mobility of the N-channel transistor is greater than the mobility of the p-channel transistor, the voltage at node Q will drop until transistor N0 turns off. For example, as shown in fig. 3B, if the voltage of the WBL is a sufficiently high voltage (such as logic 1), the WBL voltage will be transmitted to the QN node with the turn-on of P0, turning on N1 and forcing the Q node to a low voltage (such as logic zero or ground).

The data write step 354 illustrates the timing and voltage levels corresponding to the memory controller 102 writing a 1 to the SRAM cell 200. During the data write step 354, the WL is driven to turn on N2. Assuming the previous data value stored in the SRAM cell 200 is 0, the transistors P0 and N1 are turned on before the data write step 354 and the transistors P1 and N0 are turned off before the data write step 354.

For example, to rewrite a logic value 0 stored by the SRAM cell 200 to a logic value 1, BL is driven to a high voltage such as logic 1 while WL is asserted. To write a logic 1 to the SRAM cell 200, the value of the Q node must increase until transistor N0 turns on and transistor N1 turns off. Thus, during the data write step 354, transistors N1 and N2 compete by pulling the voltage of the Q node down to ground due to the conduction of transistor N1 and up to the BL voltage due to the conduction of N2. When N-channel transistors N0 and N1 are similarly sized, both may sink and draw approximately the same current. It is undesirable to increase the size of one N-channel transistor because this would result in an increase in the size of the entire SRAM cell 200. Thus, transistors N0 and N1 are biased with different gate-to-source voltages to facilitate the data write step 354.

To change the bias of transistors N0 and N1, the voltage levels of BL and WBL are driven to different voltage levels deviating from Vdd as a pre-write step before the WL is asserted. BL is driven to a voltage level that exceeds Vdd voltage Vu. When the WL is asserted in the data write step 354, the gate of transistor N0 is provided with an increased BL voltage level Vdd + Vu. This increase in the gate-source voltage of transistor N0 reinforces the bias of transistor N0.

The voltage Vu also controls the speed at which data can be written to the SRAM cell 200, allowing the data state in the cell to be changed by a higher voltage level Vdd + Vu with a faster write step 354. The voltage Vu may vary from 0 volts to a voltage limit that is a function of the transistor specifications of the SRAM cell 200. More specifically, the voltage Vdd + Vu has an upper limit imposed by the maximum voltage handling capability of the transistors in the SRAM cell 200.

Along with the increase in the BL voltage level, the WBL voltage level is decreased before the WL is asserted. Because transistor P0 is on when the Q node is 0, a reduced voltage level Vdd-Vl is provided at the gate of transistor N1, which attenuates the bias of transistor N1. The voltage Vl is a function of the size of transistor P1, which affects the voltage at node QN. In other words, the voltage Vdd-Vl has a lower limit that is the threshold voltage required to turn on the transistor N1. Thus, when WL is active, transistors N0 and N1 are advantageously biased unequally to allow the more strongly biased transistor N0 to turn on to ground more easily and force the QN node to 0. When the QN node is forced to 0, transistor P1 is turned on and the SRAM cell settles and Q is set to 1.

Exemplary five transistor SRAM cell array

FIG. 4 shows a schematic diagram of an array of five transistor SRAM cells according to an exemplary embodiment of the present disclosure. The SRAM cell array 400 includes a connected grid pattern of individual SRAM cells 408 (denoted 408.1 through 408. k), where k denotes the number of SRAM cells in the SRAM cell array 400. The individual SRAM cells 408.1 through 408.k may each represent an exemplary embodiment of the SRAM cell 200. Although fig. 4 shows SRAM cell array 400 as a 3x3 array of SRAM cells 408.k, the true implementation of SRAM cell array 400 will typically be greater in magnitude than the 9-bit capacity shown in fig. 4.

Each of the SRAM cells 408.1 to 408.k of the SRAM cell array 400 is connected to a common Word Line (WL) 402.1 to 402.i, a common Bit Line (BL) 404.1 to 404.n, and a common Write Bit Line (WBL) 406.1 to 406. n. The word lines 402.1 to 402.i connect the SRAM cells 408.1 to 408.k, which share a row as shown by connection point 410. The total number of word lines for a given SRAM cell array 400 is represented by WL0 through WLi, where i represents the number of rows in SRAM cell array 400. Similarly, bit lines 404.1 through 404.n connect SRAM cells 408.1 through 408.k, which share all columns as shown by connection 412, and write bit lines 406.1 through 406.n also connect SRAM cells 408.1 through 408.k, which share all columns as shown by connection 414. The total number of bit lines and write bit lines for a given SRAM cell array 400 is represented by BL0 through BLn and WBL0 through WBLn, where n represents the number of columns of SRAM cell array 400. Although the word lines 402.1 to 402.i, the bit lines 404.1 to 404.n, and the write bit lines 408.1 to 408.k cross each other to connect the corresponding rows and columns of the SRAM cell array 400, the word lines 402.1 to 402.i, the bit lines 404.1 to 404.n, and the write bit lines 406.1 to 406.n are each unconnected, as indicated by the dashed lines in fig. 4.

To access a particular SRAM cell 408 of the SRAM cell array 400, the memory controller 102 and/or the memory interface 104 may be configured to access a particular SRAM cell 408 corresponding to an address of the SRAM cell 408. For example, memory controller 102 may access central SRAM cell 408 by driving WL1, BL1, and WBL1 accordingly. More specifically, memory controller 102 may drive the WL1, BL1, and/or WBL1 lines in accordance with fig. 3A-3B associated with a desired read or write function.

For example, to read the center SRAM cell 408, the WBL1 line may hold a high voltage level, such as a logic 1, because this does not affect the state of any cell in the SRAM cell array 400. Then, for example, the BL1 line is precharged to a high voltage level such as a logic 1, and the WL1 line is driven to read data in the central SRAM cell 408.

To write the center SRAM cell 408, the WL1, BL1, and WBL1 lines are driven according to FIG. 3B. Writing to a single SRAM cell 408 does not affect the state of other SRAM cells 408 in the SRAM cell array 400. When a logic 1 is written to the central SRAM cell 408 storing a 0 value, the BL1 line is increased to Vdd + Vu and the WBL1 line is decreased to Vdd-Vl. Referring back to fig. 2, the SRAM cell 408 of the SRAM cell array 400 will remain in an unchanged state as long as the voltage of WBL1 maintains node QN above the threshold voltage of transistor N1 without dropping to a low enough level to turn on P1. Because the voltage of BL1 is only transferred to static memory cell 408 when WL1 is also active, increasing the voltage on BL1 does not affect other cells 408.

Exemplary squelch margin diagrams

FIG. 5 illustrates a graphical representation of the Static Noise Margin (SNM) of an SRAM cell in accordance with an exemplary embodiment of the present disclosure. SNM is a measure of the amount of voltage noise that the SRAM cell 200 can experience at nodes Q and QN before the hold state of the voltages at Q and QN "inverts" or changes state. The SNM graph 500 shows two sets of voltage transition curves, each corresponding to an inverter of the SRAM cell 200. Voltage transition curve 501.1 corresponds to the voltage transition curve of inverter 202, and voltage transition curve 501.2 corresponds to the voltage transition curve of inverter 204. More specifically, voltage transfer curve 501.1 represents the output voltage of node QN by varying the input voltage of node Q. Likewise, voltage transition curve 501.2 represents the output voltage of node Q by varying the input voltage of node QN.

For example, as shown at transition point 503, assuming the voltage at node QN is initially 0 and the voltage at node Q is Vdd, the voltage at node QN will remain at 0 until the voltage at node Q drops low enough to turn off N0 and turn on P0. When N0 is off and P0 is on, the voltage at node QN follows the transfer curve 501.1. Similarly, assuming that the voltage at node Q is initially Vdd and the voltage at node QN is 0, the voltage at node Q will remain at Vdd until the voltage at node QN increases high enough to turn off P1 and turn on N1. When P1 is off and N1 is on, the voltage at node Q follows the transfer curve 501.2.

In fig. 5, SNM is quantified by the length of the diagonal connecting the corners of the SNM box (SNM box) 506. Referring back to fig. 4, when a high voltage level (such as a logic 1) is written to the central SRAM cell 408, the SNM box 506 represents the SNM of the other cells in the array 400 that share the same column. More specifically, for example, if a high voltage level (such as a logic 1) is written to the central SRAM cell 408, all cells 408 sharing BL1 and WBL1 (but not being written to) will assume that the SNM simultaneous write step 354 represented by SNM box 506 occurs.

For example, when a high voltage (such as a logic 1) is written to node Q of the central SRAM cell 408, WBL1 is driven to a voltage less than Vdd (such as Vdd-Vl), and BL1 is driven to a voltage higher than Vdd (such as Vdd + Vu). Thus, because each inverter of the SRAM cell 408 connected to the WBL1 and BL1 is provided with unequal voltages at their respective P0 and P1 transistors, the transfer curves 501.1 and 501.2 become skewed during a write operation of a logic 1 for those cells 408 that have not yet been written. More specifically, during a logic 1 write operation, transition curve 501.1 is shown as being bolded as transition curve 502.1, and shifted from transfer curve 501.1 by a reduced voltage Vdd-Vl representing voltage 504. Further, during a write operation of logic 1, transition curve 501.2 is shown as being bolded as transition curve 502.2 and shifted by Vdd + Vu represented by voltage 505.

Exemplary six-transistor dual-port SRAM cell

Fig. 6 shows a schematic diagram of a six transistor dual port SRAM cell according to an exemplary embodiment of the present disclosure. The two-port SRAM cell 600 has a similar structure to the SRAM cell 200, with transistors P0, P1, N0, and N1 storing bit values at nodes Q and QN, where P0 and P1 are each connected to write bit lines WBL0 and WBL1, respectively. The two-port SRAM cell 600 also has two N-channel access transistors N2 and N3 each connected to a respective bit line BL0 and BL1 and word lines WL0 and WL 1. The dual port SRAM cell 600 may be arranged in an array, each cell in the array having twice as many word lines, bit lines, and write bit lines as compared to the SRAM cell array 400.

The dual port SRAM cell 600 allows two separate memory controllers, CPUs, and/or other devices requesting SRAM resources to access the Q and QN data bits individually or simultaneously. Although the bit values shared between the two devices are complementary, this can be compensated with additional circuitry and a numbering scheme (numbering scheme) that knows the layout allocated to the ports. For example, all odd numbered ports may be reversed to recover Q from QN.

The two ports of the dual port SRAM cell 600 may be identified as port 0 and port 1. Port 0 is connected to P0, N0, N1 and N2. Port 1 is connected to P1, N0, N1 and N3. During a read operation, the WBL0 and WBL1 lines remain at a high voltage level and are not used. Then, as discussed in FIG. 3A, port 0 and port 1 can access Q and QN, respectively, according to the timing diagram of the SRAM cell 200 associated with the read operation. Because BL0 and BL1 are connected to separate data nodes Q and QN, the precharged BL values will not affect the state of the dual port SRAM cell 600 when performing a synchronous read operation.

During a write operation, as shown in fig. 3B, port 0 and port 1 can each write data to the dual port SRAM cell 600 using a priority memory controller, for example. When port 0 writes a 1 to the dual-port SRAM cell 600, N0 is more strongly biased than N1 due to the increase in BL0 voltage and the decrease in WBL0 voltage. Likewise, when port 1 writes a 1 to the dual SRAM cell 600, N1 is more strongly biased than N0.

Although only one of the dual ports P0 and P1 can write data to the dual port SRAM cell 600 at any given time, write speed performance can be improved by taking advantage of the complementary nature of the Q and QN data. In other words, in most cases, writing a 0 to the dual port SRAM cell 600 is faster than writing a 1 therein because biasing N2 and N3 unequally requires additional charging. Although the steps involved in writing a 0 or 1 to the SRAM cell 200 as shown in fig. 3B apply to port 0 and port 1, the writing of a 1 to the Q node of the dual-port SRAM cell 600 by port 0 is equivalent to the writing of a 0 to the QN node of the dual-port SRAM cell 600 by port 1. Devices sharing access to the dual port SRAM cell 600 may be configured to take advantage of this relationship by communicating the data to be written to each other. To speed write time, some or all of the steps of writing a 1 may be replaced by the steps of the complementary port writing a 0.

Exemplary eight transistor four port SRAM cell

Fig. 7 shows a schematic diagram of an eight transistor four port bit cell according to an exemplary embodiment of the present disclosure. The four-port SRAM cell 700 has a similar structure to the two-port SRAM cell 600, with transistors P0, P1, N0, and N1 storing data bits at nodes Q and QN, while P0 and P1 are each connected to write bit lines WBL 0-1 and WBL 2-3, respectively. The four-port SRAM cell 700 also has four N-channel access transistors N0, Np1, Np2, and Np3, each connected to a respective bit line BL0 and BL1 and word line WL0 and WL 1. The four-port SRAM cell 700 may also be arranged as an array, each cell of which has twice as many write bit lines and four times as many word lines and bit lines as compared to the SRAM cell array 400.

The four-port SRAM cell 700 allows four separate memory controllers, CPUs, and/or other devices requesting SRAM resources to access stored bit values Q and QN, either individually or simultaneously, in a manner similar to the dual-port SRAM cell 600.

The four ports of the four-port SRAM cell 700 may be identified as port 0, port 1, port 2, and port 3. Ports 0 to 1 are associated with P0, N0, N1, Np1 and Np 2. Ports 2-3 are associated with P1, N0, N1, Np2, and Np 3. Write bit lines WBL 0-1 and WBL 2-3 are shared between ports 0-1 and ports 2-3, respectively. For example, during a read operation, the WBL 0-1 and WBL 2-3 lines are not used and remain at a high voltage level, such as a logic 1. Then, according to the timing diagram associated with the read operation of the SRAM cell 200 as shown in FIG. 3A, ports 0 through 3 may access Q and QN, respectively, simultaneously or individually. For example, when all ports 0-3 access the four-port SRAM cell 700 simultaneously, BL 0-BL 3 are all precharged to a high voltage such as a logic 1, with BL0 and BL1 connected to the Q node and BL2 and BL3 connected to the QN node. Although the additional impedance may initially pull down a high Q or QN value, additional circuitry such as the memory controller 102 and/or the memory interface 104 may compensate for this effect to ensure data reliability.

For example, during a write operation, ports 0-3 can use a priority memory controller to separately write data to the dual port SRAM cell 600 as shown in fig. 3B. When port 0 or port 1 writes a 1 into the four-port SRAM cell 700, N0 will be more strongly biased than N1 due to the rise in voltage of BL0 or BL1 and the fall in voltage of WBL0 to 1. Likewise, when ports 2-3 write a 1 into the four-port SRAM cell 700, N1 will be more strongly biased than N0.

Although the case where four ports are provided is illustrated in fig. 7, the present disclosure is not limited thereto. It will be apparent to those skilled in the art that the concept of a four port SRAM cell 700 can be extended to implement any number of ports that can simultaneously access Q and QN data without departing from the spirit and scope of the present disclosure.

Conclusion

It is to be understood that the detailed description section, and not the abstract section, is intended to be used to interpret the claims. The abstract section may set forth one or more, but not all exemplary embodiments of the disclosure, and is therefore not intended to limit the disclosure and the appended claims in any way.

The present disclosure is described with the aid of functional building blocks illustrating the implementation of specific functions and relationships thereof. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternate boundaries may be defined so long as the specified functions and relationships are appropriately performed.

It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the spirit and scope of the disclosure. Accordingly, the present disclosure should not be limited by the above-described exemplary embodiments but should be defined only in accordance with the following claims and their equivalents.

Claims (10)

1. A semiconductor memory, comprising:

a first inverter and a second inverter cross-coupled to each other;

an access switch coupled to an input of the first inverter;

a first control line coupled to the access switch; and

a second control line coupled to the second inverter;

wherein the first and second inverters are configured to be unequally biased in response to the first control line being driven above a reference voltage and the second control line being driven below a reference voltage.

2. The semiconductor memory according to claim 1, wherein the access switch is an access transistor.

3. The semiconductor memory according to claim 2, wherein the first inverter and the second inverter each comprise a first p-channel transistor and a second n-channel transistor.

4. The semiconductor memory according to claim 3, wherein the access transistor, the first p-channel transistor, and the second n-channel transistor are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

5. The semiconductor memory according to claim 4, wherein the first control line is a Bit Line (BL), and wherein the second control line is a Write Bit Line (WBL).

6. The semiconductor memory according to claim 5, further comprising:

a third control line coupled to the access transistor, wherein the third control line is a Word Line (WL) configured to control a conduction mode of the access transistor.

7. The semiconductor memory according to claim 6, wherein the first p-channel transistor of the first inverter or the second inverter is coupled to the write bit line.

8. The semiconductor memory of claim 7, wherein the bit line is driven above the reference voltage and the write bit line is driven below the reference voltage substantially simultaneously to facilitate a write operation.

9. A semiconductor memory, comprising:

a first inverter and a second inverter cross-coupled to each other;

the first inverter has a first p-channel transistor coupled to a power supply line and a first n-channel transistor;

the second inverter has a second p-channel transistor coupled to a Write Bit Line (WBL) and a second n-channel transistor;

the first p-channel transistor and the first n-channel transistor are both coupled to an access transistor that is coupled to a Bit Line (BL).

10. A semiconductor memory, comprising:

a first inverter and a second inverter cross-coupled to each other;

a first port having a plurality of control lines;

a second port having a plurality of control lines;

the first inverter has a first p-channel transistor and a first n-channel transistor both coupled to the first port; and

the second inverter has a second p-channel transistor and a second n-channel transistor both coupled to the second port;

wherein the first and second n-channel transistors are configured to be unequally biased in response to a portion of a plurality of control lines associated with the first port being driven above a supply voltage and a portion of a plurality of control lines associated with the first port being driven below the supply voltage.