HK1188033B - Method and device with enhanced ion doping - Google Patents

Abstract

The subject application relates to a method and a device with enhanced ion doping. Techniques for providing a pixel cell which exhibits improved doping in a semiconductor substrate. In an embodiment, a first doping is performed through a backside of the semiconductor substrate. After the first doping, the semiconductor substrate is thinned to expose a front side which is opposite of the backside. In another embodiment, a second doping is performed through the exposed front side of the thinned semiconductor substrate to form at least part of a pixel cell structure.

Description

Method and apparatus with enhanced ion doping

Technical Field

The present disclosure relates generally to image sensors and more particularly, but not exclusively, to front side illumination CMOS image sensors.

Background

Image sensors have become widespread. It is widely used in digital still cameras, cellular phones, security cameras, as well as in medical, automotive and other applications. The need for higher performance has encouraged further miniaturization and integration of these image sensors. Accordingly, the technology for fabricating image sensors, such as CMOS image sensors ("CIS"), continues to increase substantially.

Front Side Illumination (FSI) image sensor devices include an imaging array fabricated on a front side of a semiconductor wafer, where light may be received at the semiconductor wafer from the same front side. In contrast, backside illuminated (BSI) image sensors include an imaging array fabricated on the front side of a semiconductor wafer but receiving light through the opposite backside of such wafer. To detect light received via the backside, the silicon wafer of the BSI pixel array may be relatively thin compared to the silicon wafer of the FSI pixel array.

Typically, a pixel array is made up of pixel cells that include doped regions of one or more semiconductor substrates. The formation of such doped regions has previously been achieved by performing diffusion and/or implantation of some dopant through the front side of the semiconductor substrate. The depth of such diffusion or implantation (as measured from the front side of the semiconductor substrate) is typically limited to not extend more than about 2 μm deep into the substrate. To date, extending the depth of such doped regions (e.g., at higher power ion implants) has been limited by other constraints of pixel cell fabrication, such as the need to simultaneously implement active masking during doping to form and/or protect the pixel cell structure.

The limited depth of such doped regions affects quantum efficiency and other measures of pixel cell performance. This is particularly true, for example, with respect to operating pixel cells to detect light having longer wavelengths (e.g., compared to the wavelength of visible light). For example, infrared radiation is absorbed deeper in the pixel cell silicon than visible light. Insufficient depth of the photodiode region formed according to conventional doping techniques results in a large amount of infrared light passing through the photodiode of a conventional pixel cell being undetected.

Disclosure of Invention

In one aspect, the invention relates to a method of fabricating a pixel cell, the method comprising: doping a substrate of the pixel cell with a first dopant through a backside of the substrate, after the doping with the first dopant, thinning the substrate to form a front side of the substrate; after said thinning said substrate: doping the substrate with a second dopant through the front side of the substrate; and forming a metal layer, wherein the front side of the substrate faces the metal layer.

In another aspect, the invention relates to a pixel array. The pixel array includes: a first pixel cell comprising a doped region formed in a semiconductor substrate, wherein a dopant concentration profile of the doped region comprises: a first portion including a first concentration gradient along a line extending between a backside of the substrate and a front side of the substrate opposite the backside, wherein the first concentration gradient is according to a first log-normal distribution curve; and a second portion including a second concentration gradient along the line extending between the backside of the substrate and the front side of the substrate, wherein the second concentration gradient is according to a second log-normal distribution curve.

In another aspect, the invention relates to an image sensor device. The image sensor device includes a pixel array and readout circuitry coupled to readout image data from the pixel array. The pixel array includes a first pixel cell including a doped region formed in a semiconductor substrate, wherein a dopant concentration profile of the doped region includes: a first portion including a first concentration gradient along a line extending between a backside of the substrate and a front side of the substrate opposite the backside, wherein the first concentration gradient is according to a first log-normal distribution curve; and a second portion including a second concentration gradient along the line extending between the backside of the substrate and the front side of the substrate, wherein the second concentration gradient is according to the second log-normal distribution curve.

Drawings

Various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

fig. 1A-1F are cross-sectional views of elements illustrating a pixel cell fabrication process, according to an embodiment.

Fig. 2 is a block diagram illustrating elements of a method for fabricating a pixel cell according to an embodiment.

Fig. 3 is a block diagram illustrating elements of a pixel cell including one or more doped regions in accordance with an embodiment.

Fig. 4 is a circuit diagram illustrating elements of a pixel circuit of two pixels in a front side illumination image sensor according to an embodiment.

FIG. 5 is a block diagram illustrating elements of a front side illuminated image sensor, according to an embodiment.

Fig. 6 is a graph of a dopant concentration profile of a pixel cell according to an embodiment.

Detailed Description

Embodiments of processes, apparatuses, and systems for improved doping of pixel cells of an imaging sensor are described herein. In an embodiment, the first doping of the semiconductor substrate of the pixel cell is performed through the backside of the semiconductor substrate. After the first doping, the semiconductor substrate may be thinned to expose the other side of the substrate, e.g., where the side just exposed will serve as the front side as opposed to the back side. After the front side is exposed by this thinning, a second doping of the semiconductor substrate can be performed through the front side, for example, to form a second portion of the pixel cell structure that also includes a doped region formed by the first doping.

FIG. 1A provides a high level view of the elements in an assembly 100a for fabricating a pixel array, according to an embodiment. For example, such an array of pixels may operate as a Front Side Illumination (FSI) image sensor, although certain embodiments are not limited in this respect.

In one embodiment, assembly 100a includes a substrate 105 comprising any of a variety of combinations of one or more known semiconductor materials for use as a substrate for a pixel array. By way of illustration and not limitation, the substrate 105 may include one or more of a p-type semiconductor, an n-type semiconductor, an undoped (i.e., neither p-type nor n-type) semiconductor, and/or some combination thereof. In one embodiment, substrate 105 comprises a p-type epitaxial silicon substrate. The substrate 105 may include a side (represented by the illustrative backside 115) that will serve as a backside of the substrate 105 relative to a path along which light will be received by the substrate 105. For example, an FSI pixel array may be fabricated from assembly 100a, wherein light received by such FSI pixel array during its operation will enter a certain front side (not shown) of substrate 105 (which is the opposite side relative to backside 115). In an alternative embodiment, an array of BSI pixels can be fabricated from the assembly 100a, wherein light received by such an array of BSI pixels will enter the substrate 105 via the backside 115.

In an embodiment, the substrate 105 includes one or more doped regions each having a doping substantially different from the substrate 105. Such one or more doped regions of the substrate 105 may include, for example, one or more diffusion regions formed by a diffusion process and/or one or more implant regions formed by an implantation process. To avoid obscuring certain features of the various embodiments, such doped regions are discussed herein with respect to one or more implant regions and/or the implant process used to form such one or more implant regions. However, in different embodiments, this discussion may be extended to additionally or alternatively apply to one or more diffusion regions and/or diffusion processes for achieving such one or more diffusion regions.

By way of illustration and not limitation, one or more assemblies 100a may include one or more implant regions 110a formed in a substrate 105. Fabrication of the assembly 100a may include performing one or more implantation processes to variably implant dopants through the backside 115 into the substrate 105, e.g., for forming one or more implant regions 110 a. The number and corresponding shape and size of the one or more implant regions 110a is merely illustrative of one embodiment and not limiting of certain other embodiments. For example, the assembly 100a may include any of a variety of additional or alternative implant regions formed by implantation through the backside 115.

Features of various embodiments are discussed herein with respect to an illustrative first implant region 112a of one or more implant regions 110 a. However, this discussion may be extended to variously apply to one or more additional or alternative implant regions formed by implanting dopants into the substrate 105 through the backside 115. In an embodiment, the first implant region 112a ultimately serves as at least a portion of some of the pixel cells or structures between pixel cells of the pixel array formed by the assembly 100 a. By way of illustration and not limitation, the first implanted region 112a may ultimately serve as at least a portion of a circuit element (e.g., such a photodiode of a pixel cell), for example, where the substrate 105 is a p-type silicon substrate and the first implanted region 112a is at least a portion of an n-type doped photodiode region in the substrate 105. In another embodiment, the first implanted region 112a may ultimately serve as at least a portion of a diffusion well (e.g., a p-type well) in the pixel array formed by the assembly 100 a. In yet another embodiment, the first implanted region 112a may ultimately be used as part of an isolation structure to electrically isolate different circuit elements of a pixel cell from each other and/or to electrically isolate different pixel cells from each other. However, certain embodiments are not limited to a particular type of pixel cell structure that may ultimately include the first implant region 112 a. In some embodiments, one or more pixel cell structures may be subsequently formed in the first implant region 112a as part of the fabrication of the finally formed pixel cell.

For example, forming the first implant region 112a may include implanting dopants through openings in a photoresist mask layer (not shown) disposed on the surface of the backside 115. Such an opening in the photoresist mask layer may expose a portion of the surface of the backside 115 corresponding to the desired shape of the first implant region 112 a. For example, the photoresist mask may limit the extension of the first implant region 112a in some or all directions along the surface of the backside 105. In certain embodiments, conventional techniques for applying photoresist material to a semiconductor substrate are suitable for forming such a photoresist mask layer on the backside 115. By way of illustration and not limitation, the photoresist layer used to form the first implant region 112a may be based, at least in part, on the inversion of the mask layer used to form conventional pixel cell structures by implantation through the front side of the semiconductor substrate.

At some point during the fabrication of the assembly 100a, the substrate 105 may have some thickness t0, e.g., as measured from the surface of the backside 115 to some other side opposite the backside 115. For example, the substrate 105 may have a thickness t0 before and/or after the implantation process to form the one or more implant regions 110 a. By way of illustration and not limitation, thickness t0 may be 725 μm (which is typical for a 200mm diameter wafer) or 775 μm (which is typical for a 300mm diameter wafer). Certain embodiments are not limited to a particular thickness t0 of substrate 105.

FIG. 1B provides a high level view of the elements in an assembly 100B for fabricating a pixel array, according to an embodiment. For example, the assembly 100b may be generated from additional processing subsequent to the processing used to form the assembly 100 a.

In an embodiment, after the one or more implant regions 110a have been implanted through the backside 115, the substrate 105 may be prepared for additional implant processing, such as implanting dopants through a side of the substrate 105 different from the backside 115. Preparing for such additional processing may include attaching a carrier wafer 130, also known as a handling wafer, directly or indirectly to the substrate 105.

For example, the carrier wafer 130 may be attached to the backside 115 of the substrate 105 to provide physical support (e.g., to buffer and/or absorb stress) so that the substrate 105 and/or structures therein are not damaged by forces applied to the assembly 100b during subsequent fabrication processing. In certain embodiments, the carrier wafer 130 may be comprised of one or more materials, including but not limited to dielectric materials, semiconductor materials, metals or other conductors, and/or the like. In embodiments where the assembly 100b is used to fabricate an FSI pixel array, the carrier wafer 130 may remain permanently attached to the substrate 105, if necessary, but in embodiments where the assembly 100b is used to fabricate a BSI pixel array, the carrier wafer 130 may be removed after fabrication of the BSI pixel array is complete.

In an embodiment, the carrier wafer 130 may be attached to the backside 115 via a bonding layer 125, for example, where the bonding layer 125 comprises a layer of an oxide material. For example, such an oxide material may be deposited onto the backside 115 prior to positioning the carrier wafer 130 to the bonding layer 125. Additionally or alternatively, an oxide material may be coated to the carrier wafer 130 for adhesion to the backside 115 and/or any oxide material deposited thereon.

Bonding layer 125 may be composed of multiple component layers (not shown), although certain embodiments are not limited in this regard. For example, the bonding layer 125 may include a component layer formed of polysilicon, e.g., to be used as an electrode for use in later fabrication processes. This polysilicon layer of the bonding layer 125 may provide a voltage application to this polysilicon, for example, to affect the behavior of the carrier in the first implanted region 112 a. The bonding layer 125 can have additional functions, such as acting as an infrared absorbing layer to prevent reflection of infrared radiation or as an infrared reflecting layer to reflect infrared radiation back to the photosensitive region for additional signal collection.

FIG. 1C provides a high level view of the elements in an assembly 100C for fabricating a pixel array, according to an embodiment. For example, the assembly 100c may be generated according to additional processing subsequent to the processing used to form the assembly 100 b.

In an embodiment, after adhering the carrier wafer 130 to the backside 115 of the substrate 105, the thickness t0 of the substrate 105 may be reduced to a smaller thickness t1 by removing material from the substrate 105. Thinning the substrate 105 from its initial thickness t0 to a smaller thickness t1 may form (e.g., expose) the other side (represented by illustrative front side 115) that will serve as the front side of the substrate 105 relative to a path along which light will be received by the substrate 105 during operation of the pixel array. Thinning the substrate 105 may allow for additional ion implantation, for example, to extend the doping depth beyond the depth of some or all of the one or more implant regions 100 a.

Reducing the thickness of the substrate 105 from t0 to t1 may be accomplished by removing substrate material using mechanical techniques, such as grinding or Chemical Mechanical Polishing (CMP). In yet another embodiment, other techniques, such as wet chemical etching or dry chemical etching, may be used to remove this material to expose the front side 120. In other embodiments, a combination of mechanical and chemical techniques or a combination of different chemical techniques may be used to remove this material.

FIG. 1D provides a high level view of the elements in an assembly 100D for fabricating a pixel array, according to an embodiment. For example, the assembly 100d may be the result of changing the orientation (e.g., inverting) of the assembly 100c in one or more subsequent manufacturing processes. In an embodiment, such orientation of assembly 100d may have front side 120 facing in an upward direction to facilitate implantation, diffusion, or other ion doping processes.

FIG. 1E provides a high level view of the elements in an assembly 100E for fabricating a pixel array, according to an embodiment. For example, the assembly 100e may be generated according to additional processing subsequent to the processing used to form the assembly 100 d.

In an embodiment, the assembly 100e includes one or more implant regions 110 b. Fabrication of the assembly 100e may include performing one or more implantation processes to variably implant dopants into the substrate 105 through the front side 120, e.g., for forming one or more implant regions 110 b. The number and corresponding shape, size, etc. of the one or more implant regions 110b is merely illustrative of one embodiment and not limiting of certain other embodiments. For example, the assembly 100e may include any of a variety of additional or alternative implant regions formed by implantation through the anterior side 120.

In an embodiment, some or all of the one or more implant regions 110b are each aligned with a respective one of the one or more implant regions 110 a. By way of illustration and not limitation, the infrared aligner detects with the sensor light which infrared lamp signals through the partially implanted substrate 105 of the assembly 100 d. Based on sensing this infrared light, the infrared aligner may determine the location of one or more implant regions 100a in the substrate 105. Based on the determined locations of the one or more implant regions 110a, the aligner may determine how to position the one or more implant regions 110 b. For example, the aligner may determine how to form a photoresist mask layer (not shown) on the front side 120 for forming one or more implant regions 110a according to the location of the one or more implant regions 110 a.

Features of various embodiments are discussed herein with respect to an illustrative second implant region 112b of one or more implant regions 110 b. However, this discussion may be extended to variably apply to one or more additional or alternative implant regions formed by implanting dopants into the substrate 105 through the front side 120. In an embodiment, the second implant region 112b ultimately serves as at least a portion of some of the pixel cells or structures between pixel cells of the pixel array formed by the assembly 100 e. By way of illustration and not limitation, the second implanted region 112b may ultimately serve as at least a portion of a photodiode or other circuit element, a diffusion well, an isolation structure, and/or the like. For example, the pixel structure may include a first implant region 112a and a second implant region 112b, e.g., where the first implant region 112a and the second implant region 112b are connected to each other. However, certain embodiments are not limited to a particular type of pixel cell structure that may ultimately include the second implanted region 112 b. In some embodiments, one or more pixel cell structures may be subsequently formed within the second implant region 112b as part of the fabrication of the finally formed pixel cell.

For example, implanting the second implant region 112b into the substrate 105 through the front side 120 may include performing ion implantation through an opening in a mask layer (not shown) disposed on a surface of the front side 120. For example, such a mask may limit the extension of the second implant region 112b in some or all directions along the surface of the front side 120, e.g., for shaping at least a portion of a final pixel structure including the second implant region 112 b. In an embodiment, masking and/or doping techniques may be applied for defining one or more edges of the second implant region 112b that are each aligned with a respective edge of the first implant region 112 a. Alternatively or in addition, the fabrication of the second implant region 112b may result in the second implant region 112b being connected to the first implant region 112 a.

Fig. 1F provides a high level view of the elements of a pixel array 100F according to an embodiment. For example, the pixel array 100f may be generated according to additional processing after the processing used to form the assembly 100 e.

In an embodiment, one or more implant regions 110a and one or more implant regions 110b may form circuit elements or other pixel cell structures in pixel array 100 f. By way of illustration and not limitation, the first and second implant regions 112a, 112b may form some or all of the pixel cell structure 112 c. The pixel cell structure 112c may be used as at least a portion of a circuit element of a pixel cell or as a structure for assisting the operation of such a pixel cell circuit element. For example, the pixel cell structure 112c may include a photodiode, a diffusion well, an isolation structure, and/or the like.

Fabrication of the pixel array 100f can include forming one or more additional pixel cell structures in and/or on the substrate 105 of the assembly 100 e. By way of illustration and not limitation, fabrication of pixel array 100f can include forming one or more metal layers (represented by illustrative metal stack 135). In an embodiment, the front side 120 of the substrate 105 faces one or more metal layers of the metal stack 135. Fabrication of pixel array 100f may further include forming filters 140 and/or microlenses 145 on metal stack 135, although certain embodiments are not limited in this respect. The formation of some or all of metal stack 135, filter 140, and microlens 145 may be in accordance with conventional pixel cell fabrication techniques. Certain embodiments are not limited to additional pixel cell structures, e.g., microlenses, filters, metal layers, and/or other structures, of a particular type, number, kind, etc., that may be added to an assembly, e.g., assembly 100 e.

Fig. 2 illustrates elements of a method 200 for fabricating a pixel cell according to an embodiment. For example, the method 200 may fabricate a structure having some or all of the features discussed with respect to fig. 1A-1F.

The method 200 can include doping the substrate with a first dopant through a backside of the substrate at 210. For example, doping with a first dopant can form at least a portion of a pixel structure of a front side lighting pixel cell. In one embodiment, the first dopant comprises a p-type dopant (e.g., boron, aluminum, gallium, indium, and/or thallium), although certain embodiments are not limited in this respect. In an alternative embodiment, the first dopant comprises an n-type dopant (e.g., phosphorus, antimony, and/or the like). Certain embodiments are not limited to doping a particular type (e.g., n-type or p-type) of dopant into a particular type (e.g., n-type or p-type) of substrate region.

Following the doping at 210, the method 200 may further include performing a thinning of the substrate to form a front side of the substrate at 220. For example, thinning the substrate may include one or more processes including, but not limited to, grinding, Chemical Mechanical Polishing (CMP), wet chemical etching, dry chemical etching, and/or the like. In certain embodiments, the carrier layer is bonded to the back side of the substrate after doping at 210 (e.g., before thinning at 220). Such a carrier layer may be bonded to protect the substrate from stresses imposed by the thinning of the substrate at 220 and/or by later orientation or processing of the thinned substrate.

After thinning the substrate, the method 200 may include doping the substrate with a second dopant through the front side of the substrate at 230. In one embodiment, the second dopant is of the same dopant type as the first dopant, e.g., where both the first and second dopants are p-type. In one embodiment, a first doped region in the substrate is formed with a first dopant doping, wherein a second doped region in the substrate adjacent to the first doped region is formed with a second dopant doping.

The circuit element or other structure of the pixel unit can be composed of a first doping area and a second doping area. Such a circuit element or structure may itself be considered a doped region, e.g., wherein the first doped region and the second doped region are each sub-regions of such a doped region. For example, the first doped region and the adjoining second doped region may together function as a photodiode, a diffusion well, an isolation structure, and/or the like. Doping from the front and back sides of the substrate may allow for the formation of a continuous, polymerized doped region having twice the thickness of the region doped according to conventional techniques. For example, the doped region may extend beyond a typical limit of 2 microns, for example, where in one embodiment the doped region has a depth (also referred to herein as thickness) of at least 3 microns.

Doping the substrate with the second dopant at 230 can include performing an alignment to ensure that the one or more doped regions resulting from the doping at 230 are correctly positioned relative to the one or more doped regions resulting from the doping at 210. By way of illustration and not limitation, an infrared aligner may be used to determine the location of one or more doped regions that have been located in a substrate. Based on the determined location of the previously doped region, the aligner may determine how to position a photoresist mask layer on the front side of the substrate to mask doping with the second dopant.

After doping with the second dopant at 230, the substrate (e.g., along with any carrier layer bonded to the backside of the substrate) may be provided for additional processing. For example, the method 200 may further include one or more additional operations (not shown) for fabricating any of a variety of additional pixel cell structures in and/or on the substrate. Additionally or alternatively, a metal layer may be formed directly or indirectly on the front side of the substrate, e.g., the metal layer includes one or more metal traces for operation of the pixel array. Additionally or alternatively, one or more color filters, microlenses, and/or other structures may be formed directly or indirectly on such a metal layer. The formation of such additional pixel cell structures may be according to any of a variety of conventional techniques and may not limit certain embodiments.

FIG. 3 is a cross-sectional view of elements in a pixel cell 300 of a front side illumination ("FSI") CMOS image sensor ("CIS") according to an embodiment. For example, the pixel cell 300 may be fabricated according to a process that includes some or all of the features of the method 200.

In an embodiment, the pixel cell 300 may include a substrate 320 having a front side 350 and a back side 355, wherein various structures of the pixel cell 300 are formed in or on the front side 350, and wherein the metal stack 305 is formed directly or indirectly on the front side 350. The metal stack 305 may include one or more metal layers (represented by illustrative metal layers M1, M2, and M3) patterned to allow light incident on the pixel cell 300 (indicated by dashed arrows 306), e.g., through the microlens 308 to the photodiode region PD 310. In one embodiment, the PD310 is configured to respond primarily to infrared light. Pixel cell 300 may further include a color filter 312 disposed below microlens 308, although certain embodiments are not limited in this respect.

One or more circuit elements or other structures of the pixel cell 300 can be variously formed in and/or on the substrate 320. By way of illustration and not limitation, the substrate 320 may include a p-type epitaxial layer or other suitable semiconductor material in which the PD310 is formed, a p-type pinning layer 316 on the PD310, a floating diffusion ("FD") region 325 disposed in a p-well 330, and a shallow trench isolation ("STI") 335. A transfer transistor TX340 (not fully illustrated) may be disposed between PD310 and FD region 325 for transferring a signal output by PD310 to FD region 325. The pixel array may include one or more additional structures, such as STI337 in p-well 338, to electrically isolate pixel cell 300 from adjacent pixel cells (not shown).

In one embodiment, the pixel cell 300 may operate as follows. During the integration period (also referred to as the exposure or accumulation period), light 306 is incident on the PD 310. The PD310 generates charge in response to incident light 306. The charge is retained in the PD 310. At this stage, TX340 may turn off (e.g., block the flow of electrons between PD310 and FD region 325) due to a bias on the gate of TX340 that is less than the threshold voltage of TX 340. After the integration period, TX340 may turn on to read out the signal corresponding to the generated charge from PD 310. For example, a positive bias may be applied to the gate of TX340 to assist in charge transfer from PD310 to FD region 325. After the electrical signal in PD310 has been transferred to FD region 325, TX340 may be turned off in preparation for the next integration period. Based on the charge transferred from PD310 to FD325, additional circuitry 345 of pixel cell 300 may operate to generate an analog signal that pixel cell 300 will output via a trace in metal stack 305.

In one embodiment, a given doped region (e.g., PD310) in the substrate 320 includes a first sub-region and a second sub-region (e.g., first doped sub-region 360 and second doped sub-region 365, respectively) that are adjacent to each other. For example, the first sub-region 360 may be formed at least in part by doping performed through the backside 355 (e.g., as per operation 210). Additionally or alternatively, the second sub-region 365 may be formed at least in part by doping through the front side 350 (e.g., as per operation 220). Such two-sided doping can provide the PD310 with a longer extension into the substrate 320 than the depth of the photodiode region formed according to conventional (e.g., one-sided) doping techniques. The additional extension of the PD310 deep into the substrate 320 may improve the sensitivity, e.g., infrared sensitivity, of the pixel cell 300.

The PD310 or any other doped region may be characterized by a particular dopant concentration profile. As used herein, "dopant concentration profile" refers to a collection of dopant concentrations of various degrees for different respective locations in a doped region, e.g., where the locations are along a line extending between a backside of the substrate and a front side of the substrate. Fig. 6 is an illustrative graph of a dopant concentration profile 600 for one type of doped region in a pixel cell in accordance with an embodiment. However, the doped region may have any of a variety of alternative dopant concentration profiles, according to different embodiments. The particular concentration values shown in fig. 6 are merely illustrative and not limiting of the various embodiments.

The features of the dopant concentration profile 600 are discussed herein with reference to the pixel cell 300. However, this discussion can be extended to apply variably to any of a variety of other dopant concentration profiles and/or any of a variety of pixel cells according to different embodiments. In an embodiment, the doping through the backside 355 to form the first sub-region may contribute a first concentration component 610 to the dopant concentration profile 600 for the entire doped region. The first concentration component 610 may include its own respective dopant that exhibits a concentration gradient according to (e.g., conforms to) a particular curve, such as a first log-normal distribution curve. Additionally or alternatively, the doping through the front side 350 of the substrate 320 for forming the second sub-region may contribute a second concentration component 620 to the dopant concentration profile 600 for the entire doped region. The second concentration component 620 may include its own respective dopant that exhibits a concentration gradient according to another curve (e.g., according to a second log-normal distribution curve). To aid in illustrating the features of various embodiments, the concentration levels of the dopant concentration profile 600 are shown on a logarithmic scale. Either or both of the concentration components 610, 620 may variably exhibit one or more different lognormal distribution characteristics (e.g., skew, mean, standard deviation, and/or the like) according to different embodiments.

The respective concentration profiles of the concentration components 610, 620 may deviate from each other in the substrate 320, for example, because they correspond to doping through opposite respective sides of the substrate 320. Thus, the dopant concentration profile 600 of the entire doped region may comprise a first portion 630, wherein the first concentration component 610 is dominant and wherein the second concentration component 620 may be negligible or even undetectable. For example, such a first portion 630 may be positioned adjacent to the backside 355 with doping performed through the backside 355 to form a first sub-region. Additionally or alternatively, the dopant concentration profile 600 of the entire doped region may comprise a second portion 650, wherein the second concentration component 620 is dominant and wherein the first concentration component 610 may be negligible or even undetectable. For example, such a second portion 650 may be positioned adjacent to the front side 350, with doping being performed through the front side 350 to form a second sub-region.

Accordingly, various embodiments include or otherwise provide a pixel cell including a doped region having a dopant concentration profile 600, the dopant concentration profile 600 including a first portion 630 exhibiting a first concentration gradient according to a first log-normal distribution curve and a second portion 650 exhibiting a second concentration gradient according to a second log-normal distribution curve. The first portion 630 and the second portion 650 may correspond to a first sub-region and a second sub-region adjacent to the first sub-region, respectively. In an embodiment, the third portion 640 of the dopant concentration profile 600 is positioned between the first portion 630 and the second portion 650. The third section 640 may exhibit a concentration gradient according not only to the first log-normal distribution curve but also to the second log-normal distribution curve. By way of illustration and not limitation, the concentration gradient of the third portion 640 can be according to a sum of curves including a first log-normal distribution curve and a second log-normal distribution curve. In an embodiment, the dopant concentration profile 600 includes two or more local concentration maxima, for example, where one of the local maxima is substantially equal to a maximum of the first log-normal distribution curve and/or where another local maximum is substantially equal to a maximum of the second log-normal distribution curve.

FIG. 4 is a circuit diagram of a pixel circuit 400 illustrating two four-transistor ("4T") pixels Pa410 and Pb420 within an FSI imaging array, according to an embodiment of the invention. Pixel circuit 400 is one possible pixel circuit architecture for implementing a pixel formed in accordance with the techniques discussed with respect to fig. 1A-1F. However, it should be understood that such embodiments are not limited to 4T pixel architectures; rather, persons of ordinary skill in the art having benefit of the present disclosure will appreciate that the present teachings are also applicable to 3T designs, 5T designs, and a variety of other pixel architectures. In fig. 4, pixels Pa410 and Pb420 are arranged in two rows and one column. In the illustrated embodiment, each of the pixels Pa410 and Pb420 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source follower ("SF") transistor T3, and a select transistor T4. In one embodiment, the PD is configured to respond primarily to infrared light. During operation, the transfer transistor T1 may receive a transfer signal TX, which transfers charge accumulated in the photodiode PD to the floating diffusion node FD. In one embodiment, the floating diffusion node FD may be coupled to a storage capacitor for temporarily storing image charge. A reset transistor T2 may be coupled between power rail VDD and floating diffusion node FD to reset (e.g., discharge or charge FD to a preset voltage) under control of a reset signal RST. Floating diffusion node FD may be coupled to the gate of SF transistor T3. SF transistor T3 may be coupled between power rail VDD and select transistor T4. SF transistor T3 may operate as a source follower providing a high impedance output from the pixel. Finally, select transistor T4 may selectively couple the output of pixel circuit 400 to a readout column line under control of a select signal SEL. In one embodiment, the TX signal, the RST signal, and the SEL signal are variably generated by a control circuit (not shown).

FIG. 5 illustrates elements of an imaging system 500 according to an embodiment. Imaging system 500 may include optics 501, an image sensor 502 for receiving light via optics 501, and circuitry for receiving and processing signals generated by image sensor 502 based on such received light. In imaging system 500, circuitry for receiving and processing signals generated by image sensor 502 is represented as including one or more of an illustrative signal conditioner 512, an analog-to-digital converter 514, a digital signal processor 516, a storage device 518, and a display 520. However, any of a variety of combinations of one or more additional or alternative components for receiving and processing such signals may be provided, according to different embodiments.

Optics 501 (which may include refractive, diffractive, or reflective optics, or a combination thereof) may be coupled to image sensor 502 to focus an image onto pixels in pixel array 504 of the image sensor. The pixel array 504 may capture the image and the remainder of the imaging system 500 may process the resulting pixel data to represent the image.

For example, image sensor 502 may include a pixel array 504 and a signal reading and processing circuit 510. The pixel array 504 may include a plurality of pixels arranged in rows 506 and columns 508. During operation of pixel array 504 to capture an image, some or all of the pixels in pixel array 504 may capture incident light (i.e., photons) during some exposure period and convert the collected photons into electrical charge. The respective charges generated by such pixels may each be read out as a corresponding analog signal, where a characteristic of such analog signal (e.g., its charge, voltage, or current) is representative of the intensity of light incident on the pixel during the exposure period.

The illustrated pixel array 504 is regularly shaped, but in other embodiments the array may have a different regular or irregular arrangement than shown and may include more or fewer pixels, rows, and columns than shown. Additionally or alternatively, pixel array 504 can be a color image sensor (e.g., including red, green, and blue pixels designed to capture images in the visible portion of the spectrum), a black and white image sensor, and/or an image sensor designed to capture images in the non-visible portion of the spectrum (e.g., infrared or ultraviolet).

Image sensor 502 may include a signal reading and processing circuit 510 having logic to methodically read analog signals from some or all of the pixels of pixel array 504 and further provide processing in an embodiment (e.g., to filter such signals, correct defective pixels, provide white balance, and/or the like). In an embodiment, the circuit 510 may perform only some signal processing, e.g., where other signal processing is performed by one or more other components, such as the signal conditioner 512 or the DSP 516. Although shown in the drawings as a separate element from the pixel array 504, in some embodiments the reading and processing circuitry 510 may be integrated with the pixel array 504, e.g., on the same silicon substrate, and/or otherwise include circuit logic embedded within the pixel array 504. In other embodiments, the reading and processing circuitry 510 may be an element that is not only external to the pixel array 504 but also external to the image sensor 502.

Signal conditioner 512 may be coupled to image sensor 502 to receive and condition analog signals from pixel array 504 and read and processing circuit 510. In different embodiments, signal conditioner 512 may include a variety of components for conditioning analog signals. Examples of components that may be found in signal conditioner 512 include filters, amplifiers, offset circuits, automatic gain control, and so forth. An analog-to-digital converter (ADC)514 may be coupled to the signal conditioner 512 to receive the conditioned analog signals corresponding to each pixel in the pixel array 504 from the signal conditioner 512 and convert these analog signals to digital values.

A Digital Signal Processor (DSP)516 may be coupled to the analog-to-digital converter 514 to receive the digitized pixel data from the ADC514 and process the digital data to generate a final digital image. For example, the DSP516 may include a processor and an internal memory in which the DSP516 may store and retrieve data. After the image is processed by the DSP516, it may be output to one or both of a storage unit 518, such as a flash memory or optical or magnetic storage unit, and a display unit 520, such as an LCD screen.

Techniques and architectures for pixel cell fabrication and operation are described herein. In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the description.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

Some portions of the detailed descriptions herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be noted, however, that all of these terms and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Certain embodiments also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the desired purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs) such as dynamic RAM (dram), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The desired structure for a number of these systems will appear from the description herein. Moreover, certain embodiments are not described with reference to any particular programming language. It should be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.

Based on what is described herein, various modifications may be made to the disclosed embodiments and implementations of the invention without departing from the scope thereof. The specification and examples herein are, therefore, to be regarded in an illustrative rather than a restrictive sense. Reference should be made solely to the appended claims for purposes of measuring the scope of the present invention.

Claims (19)

1. A method of fabricating a pixel cell, the method comprising:

doping a substrate of the pixel cell with a first dopant through a backside of the substrate;

thinning the substrate to form a front side of the substrate after doping with the first dopant;

after said thinning said substrate:

doping the substrate with a second dopant through the front side of the substrate; and

forming a metal layer, wherein the front side of the substrate faces the metal layer, and wherein light enters the substrate via the front side;

wherein doping with the first dopant forms a first doped region of a photodiode and doping with the second dopant forms a second doped region of the photodiode.

2. The method of claim 1, further comprising bonding a carrier layer to the backside of the substrate after doping with the first dopant.

3. The method of claim 2, wherein said thinning said substrate is performed while bonding said carrier layer to said backside of said substrate.

4. The method of claim 1, wherein each of the first and second dopants comprises a respective n-type dopant.

5. The method of claim 1, wherein the doping with the first dopant is to form one or more pixel structures of a front side lighting pixel cell.

6. The method of claim 1, wherein the first doped region abuts the second doped region.

7. The method of claim 6, wherein a first pixel structure of the pixel cell comprises the first doped region and the second doped region.

8. The method of claim 7, wherein the first pixel structure further comprises a diffusion well and an isolation structure.

9. The method of claim 7, wherein a thickness of the substrate between the front side and the back side is at least three microns.

10. A pixel array, comprising:

a first pixel cell comprising a doped region formed in a semiconductor substrate, wherein a dopant concentration profile of the doped region comprises:

a first portion formed by doping from a front side of the substrate, wherein the first portion forms a first doped region of a photodiode and includes a first concentration gradient along a line extending between a back side of the substrate and a front side of the substrate opposite the back side, and wherein the first concentration gradient is according to a first log-normal distribution curve; and

a second portion formed by doping from the backside of the substrate, wherein the second portion forms a second doped region of the photodiode and includes a second concentration gradient along the line extending between the backside of the substrate and the front side of the substrate, wherein the second concentration gradient is according to a second log-normal distribution curve, and wherein light enters the substrate via the front side.

11. The pixel array of claim 10, wherein the dopant concentration profile further comprises:

a third portion positioned between the first portion and the second portion, wherein the third portion comprises a concentration gradient according to a third curve that is not only according to the first log-normal distribution curve but not only according to the second log-normal distribution curve.

12. The pixel array of claim 11, wherein the concentration gradient of the third portion is according to a sum of curves including the first and second log-normal distribution curves.

13. The pixel array of claim 10, wherein the dopant concentration profile of the doped region includes two or more local dopant concentration maxima.

14. The pixel array of claim 13, wherein one of the two or more local maxima is substantially equal to a maximum of the first log normal distribution curve.

15. An image sensor device, comprising:

a pixel array, comprising:

a first pixel cell comprising a doped region formed in a semiconductor substrate, wherein a dopant concentration profile of the doped region comprises:

a first portion formed by doping from a front side of the substrate, wherein the first portion forms a first doped region of a photodiode and includes a first concentration gradient along a line extending between a back side of the substrate and a front side of the substrate opposite the back side, and wherein the first concentration gradient is according to a first log-normal distribution curve; and

a second portion formed by doping from the backside of the substrate, wherein the second portion forms a second doped region of the photodiode and includes a second concentration gradient along the line extending between the backside of the substrate and the front side of the substrate, wherein the second concentration gradient is according to a second log-normal distribution curve, and wherein light enters the substrate via the front side; and

readout circuitry coupled to readout image data from the pixel array.

16. The image sensor device of claim 15, wherein the dopant concentration profile further comprises:

a third portion positioned between the first portion and the second portion, wherein the third portion comprises a concentration gradient according to a third curve that is not only according to the first log-normal distribution curve but not only according to the second log-normal distribution curve.

17. The image sensor device of claim 16, wherein the concentration gradient of the third portion is according to a sum of curves including the first and second log-normal distribution curves.

18. The image sensor device of claim 15, wherein the dopant concentration profile of the doped region includes two or more local dopant concentration maxima.

19. The image sensor device of claim 18, wherein one of the two or more local maxima is substantially equal to a maximum of the first log normal distribution curve.