HK1180863B - Multilevel reset voltage for multi-conversion gain image sensor - Google Patents

Description

Multi-level reset voltage for multiple conversion gain image sensor

Technical Field

The present disclosure relates generally to image sensors, and particularly, but not exclusively, to complementary metal oxide semiconductor ("CMOS") image sensors.

Background

Image sensors have become ubiquitous. They are widely used in digital cameras, cellular phones, security cameras, and medical, automotive and other applications. The technology for fabricating image sensors, and in particular for fabricating complementary metal oxide semiconductor ("CMOS") image sensors, continues to advance at a great pace. For example, the demand for higher resolution and lower power consumption has encouraged further miniaturization and integration of these image sensors.

Fig. 1A is a circuit diagram illustrating a pixel circuit of a four transistor ("4T") pixel cell 100 within an image sensor array. The pixel cells 100 may be repeated and organized into rows and columns of an image sensor array. The pixel cell 100 includes a photodiode 101, a transfer transistor 102, a reset transistor 103, a source follower ("SF") transistor 104, a row select ("RS") transistor 105, and a floating diffusion ("FD") node 106.

During operation, transfer transistor 102 receives a transfer signal TX, which causes transfer transistor 102 to transfer charge accumulated in photodiode 101 to FD node 106. Reset transistor 103 is coupled between power rail VDD and FD node 106 to reset the pixel cell (e.g., discharge or charge FD node 106 and photodiode 101 to a preset voltage) under control of reset signal RST. Floating diffusion node 106 is coupled to the gate terminal of SF transistor 104. SF transistor 104 has its channel coupled between power rail VDD and RS transistor 105. SF transistor 104 operates as a source follower providing a high impedance connection to FD node 106. The RS transistor 105 selectively couples the output of the pixel cell 100 to a bit line 107 (also referred to as a column readout line) under control of a signal RS.

Fig. 1B is a timing diagram 110 of the pixel cell 100 of fig. 1A during normal operation. In normal operationThe photodiode 101 and FD node 106 are reset during the reset phase by temporarily asserting the reset signal RST and the transmission signal TX. As can be seen in fig. 1B, after the reset phase, the integration phase begins by deasserting the transmit signal TX and the reset signal RST, and allowing incident light to charge the photodiode 101. The voltage or charge of the photodiode 101 is indicative of the intensity of the incident light of the photodiode 101 during the integration period. Resetting FD node 106 to a reset voltage V by asserting a reset signal RST_RSTThe readout phase starts before the integration phase ends. V_RSTApproximately equal to power rail VDD minus the threshold voltage V of reset transistor 103_TH. After the floating diffusion node 106 has been reset, the row select signal RS and the sample signal SHR (sample-hold-reset) are asserted, which couples the FD node 106 to a sample-and-hold circuit (not shown) through the RS transistor 105 and the bit line 107. Reset voltage V_RSTAfter sampling, the sampling signal SHR is deasserted. The end of the integration phase occurs after deasserting the sampling signal SHR. A transfer signal TX is then asserted to couple photodiode 101 to floating diffusion node 106 and the gate terminal of SF transistor 104. As photogenerated charge carriers (e.g., electrons) accumulated on photodiode 101 are transferred to FD node 106, the voltage at FD node 106 decreases since the electrons are negative charge carriers. After the charge transfer is complete, the transfer signal TX is deasserted. After the transmission signal TX is deasserted, the sampling signal SHS (sample-and-hold signal) is asserted and the voltage V at the FD node 106 is_SIGIs sampled.

When the reset signal RST is asserted, the channel region of the reset transistor 103 is inverted and electrons are injected into the channel during the reset phase and at the beginning of the readout phase. When reset signal RST is deasserted, some charge within the channel will be injected to the terminal coupled to power rail VDD and other charge will be injected to the terminal coupled to FD node 106. The injection of charge to the FD node 106 lowers the potential of the FD node 106.

Fig. 1C is a graph 150 illustrating the voltage at FD node 106 during the time period illustrated in fig. 1B. Reset phase period (andthe beginning of the readout phase when the reset voltage is sampled by a sample and hold circuit (not shown), reset signal RST is asserted and FD node 106 is reset to reset voltage V_RST. As can be seen in fig. 1C, when the reset signal RST is deasserted, the voltage at FD node 106 drops to the charge injection voltage V_CI. Reset voltage V_RSTAnd a charge injection voltage V_CIThe difference between is Δ V. An increase in the voltage level of the reset signal RST may cause an increase in Δ V. The drop in potential of the FD node 106 reduces the floating diffusion voltage swing and thus the conversion gain of the pixel cell 100. Charge injection in the reset transistor can be reduced by increasing the channel length of the reset transistor; however, this increases the size of the pixel cell 100 or reduces the fill factor of the pixel cell 100. The detrimental effects of charge injection can also be reduced by reducing clock speed; however, this results in a lower speed image sensor.

The conversion gain of the image cell 100 is defined as the ratio of the change in voltage of the FD node 106 to the change in charge transferred to the FD node 106 during charge transfer. The conversion gain is inversely proportional to the capacitance of the FD node 106. High conversion gain may be advantageous for improving low light sensitivity. For a conventional image sensor, the conversion gain may be increased by reducing the capacitance of FD node 106; however, as the pixel cell continues to shrink, pixel saturation or overexposure in bright environments becomes more severe.

Disclosure of Invention

In one aspect, the invention relates to a method of operating an image sensor, the method comprising: adjusting a capacitance coupled to a circuit node within a pixel cell, wherein the circuit node is coupled to selectively receive image charge obtained by a photosensor of the pixel cell, wherein a conversion gain is selected from a plurality of conversion gains for the pixel cell by adjusting the capacitance; selecting a voltage level from a plurality of voltage levels to be used as a reset signal when the reset signal is asserted, wherein the reset signal controls a reset of the circuit node during operation of the pixel cell, wherein the voltage level is selected dependent on which of the plurality of conversion gains is selected by adjusting the capacitance; asserting the reset signal to reset a voltage at the circuit node. The method further includes obtaining an image charge at the photosensor; transferring the image charge to the circuit node to thereby change the voltage at the circuit node; and reading out image data indicative of the voltage at the circuit node.

In another aspect, the invention relates to an image sensor system comprising: a pixel array comprising a given pixel cell, the given pixel cell comprising: a photosensor for capturing image charge; a floating diffusion ("FD") node coupled to receive the image charge from the photosensor; an adjustable capacitance coupled to the FD node to change a conversion gain of the given pixel cell in response to a conversion gain signal; and a reset transistor coupled to reset a voltage at the FD node in response to a reset signal applied to a gate terminal of the reset transistor; and a control unit coupled to the pixel array. The control unit includes logic that, when executed by the control unit, causes the control unit to perform operations including: setting the conversion gain signal to change the adjustable capacitance; selecting a voltage level for the reset signal when the reset signal is asserted to reset the FD node, wherein the voltage level is selected in dependence on a value selected for the adjustable capacitance; and asserting the reset signal to reset the FD node.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Fig. 1A (prior art) is a circuit diagram illustrating a pixel circuit of a four transistor ("4T") pixel cell.

Fig. 1B (prior art) is a timing diagram explaining control signals during operation of the pixel cell in fig. 1A.

Fig. 1C (prior art) is a graph illustrating the voltage at the floating diffusion node during operation of the pixel cell illustrated in fig. 1B.

Fig. 2 is a functional block diagram explaining an image sensor system according to an embodiment of the present invention.

Fig. 3 is a circuit diagram explaining a circuit for implementing a double conversion gain within an image sensor according to an embodiment of the present invention.

FIG. 4 is a timing diagram illustrating the operation of an image sensor during low conversion gain operation in a bright ambient environment in accordance with an embodiment of the present invention.

FIG. 5 is a timing diagram explaining the operation of the image sensor during high conversion gain operation in a dim ambient environment, according to an embodiment of the present invention.

FIG. 6 is a block diagram illustrating a black day circuit coupled to each bit line of a pixel array, in accordance with an embodiment of the present invention.

Detailed Description

Embodiments of apparatus and methods of operation of a pixel cell with an improved reset gate voltage for dual conversion gain ("DCG") are described herein. In the following description, numerous specific details are described to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described, but are nonetheless encompassed within the scope of the invention.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. However, they are also not necessarily mutually exclusive.

Fig. 2 is a block diagram explaining an image sensor system 200 according to an embodiment of the present invention. The illustrated embodiment of image sensor system 200 includes pixel array 205, readout circuitry 210, functional logic 215, and control circuitry 220.

Pixel array 205 is a two-dimensional array of imaging sensor cells or pixel cells (e.g., pixels P1, P2,. Pn). In one embodiment, each pixel is a complementary metal oxide semiconductor ("CMOS") imaging pixel. Pixel array 205 may be implemented as a front-side illuminated image sensor or a back-side illuminated image sensor. As illustrated, each pixel is arranged in rows (e.g., rows R1-Ry) and columns (e.g., C1-Cx) to obtain image data of a person, location, or object, which can then be used to render an image of the person, location, or object.

After each pixel has acquired its image data or image charge, the image data is read out by readout circuitry 210 and then transferred to functional logic 215. The readout circuit 210 may include an amplification circuit, an analog-to-digital ("ADC") circuit, or other circuits. Function logic 215 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 210 may read out a row of image data at a time along the bit lines, or may read out the image data using many other techniques (not illustrated) such as serial readout, column readout along readout row lines, all pixels simultaneously all in parallel readout, or other techniques.

Control circuitry 220 is coupled to pixel array 205 and includes logic for controlling operating characteristics of pixel array 205. For example, reset, row select, and transfer signals may be generated by control circuitry 220. In addition, a dual conversion gain ("DCG") signal may also be generated by the control circuit 220. The control circuit 220 includes logic for determining when various control signals are to be asserted and deasserted. In one embodiment, the control circuitry includes a light sensing circuit 225 for measuring the intensity or brightness of ambient light incident on the pixel array 205 and adjusting the control signal accordingly to provide the DCG feature adjusted based on the ambient brightness.

Fig. 3 is a circuit diagram illustrating a circuit 300 implementing a DCG function within the image sensor system 200 according to an embodiment of the invention. The illustrated embodiment of circuit 300 includes pixel cells 306 (only the internal components of one pixel cell 306 are illustrated) and a reset generator 310. Pixel cell 306 represents one possible pixel circuit architecture for implementing each pixel cell in pixel array 205 of fig. 2. However, it should be understood that the teachings disclosed herein are not limited to 4T pixel architectures; rather, those skilled in the art, having the benefit of this disclosure, will appreciate that the present teachings are applicable to a variety of other pixel architectures as well.

In the illustrated embodiment, the reset generator 310 is shared by a row of pixel cells 306, while each row of pixel array 205 is coupled to its own reset generator 310. In other embodiments, the reset generator 310 may be shared by a column of pixel cells, by a group of pixel cells (e.g., all pixels having a common color), by all pixel cells within the pixel array 205, or otherwise. The reset generator 310 may be included within the control circuit 220 illustrated in fig. 2.

The illustrated embodiment of pixel cell 306 includes components similar to pixel cell 100 in fig. 1, but further includes an adjustable capacitor or transistor 307 coupled to floating diffusion node 106 to implement dual conversion gain. In the present embodiment, the transistor 307 has a gate terminal coupled to the floating diffusion node 106 and source and drain terminals coupled together to receive a DCG signal (DCG _ SIG). As such, the transistor 307 is configured as a MOS capacitor.

An illustrative embodiment of the reset generator 310 includes powerA level shifter 320 and switches 330 and 340. Level shifter 320 includes cross-coupled transistors 321 and 322 and pull-down path 323. Transistors 321 and 322 are coupled between level-shifted power supply LVL _ VDD and pull-down path 323. The gate and source terminals of transistors 321 and 322 are cross-coupled. Switches 330 and 340 selectively reset the high conversion gain supply (V) under the control of select signals SEL _ HCG and SEL _ LCG, respectively_{RST_HCG}) And low conversion gain reset power supply (V)_{RST_LCG}) Coupled directly to the drain terminals of transistors 321 and 322 as LVL _ VDD.

On-chip circuitry (e.g., the photosensitive circuit 225) or off-chip circuitry may be used to determine the intensity of light incident on the photodiode 101 and associated logic for determining whether a low conversion gain mode or a high conversion gain mode should be used to capture an image. This can be done in a number of ways. For example, a dedicated photosensitive device (e.g., photosensitive circuit 225) outside the imaging area of the image sensor may be used to monitor the amount of light incident on the image sensor. A brightness threshold may be programmed into the light sensitive circuit to determine whether the ambient environment is determined to be light or dark.

In bright light conditions (bright environments), a low conversion gain ("LCG") mode is used to obtain higher full well capacity and wider dynamic range. In the LCG mode, DCG SIG may be deasserted by placing DCG SIG at a low voltage setting (e.g., ground, logic low, etc.), which is applied to the channel (e.g., both source and drain) of transistor 307, as seen in fig. 3 and 4. Deasserting DCG SIG places transistor 307 in the inversion mode and its inversion capacitance added to floating diffusion node 106 to increase the overall voltage of floating diffusion node 106, thus reducing the conversion gain of pixel cell 306. Transistor 307 may have dimensions selected such that the combined capacitance at FD node 106 is 4-5 times greater when transistor 307 is operating in its inversion mode than when transistor 307 is operating in its depletion mode.

When the capacitance of the FD node 106 is increased, charge injection of the reset transistor 103 and for completely resetting the floating diffusion node 106 to reset the voltage V_RSTThe voltage level of (2) increases. This is thatResetting power supply V with low conversion gain by enabling selection signal SEL _ LCG_{RST_LCG}Coupling to the level shifter power source LVL _ VDD attains, thus increasing the voltage level of the reset signal RST. In one embodiment, the select signal SEL _ LCG is asserted simultaneously with the reset signal RST at the start of the reset phase and the start of the readout phase and deasserted when the reset signal RST is deasserted.

In low light conditions (dim environments), a high conversion gain ("HCG") mode is used to improve low light sensitivity. As seen in fig. 5, the conversion gain of pixel cell 306 may be increased by asserting DCG SIG (e.g., setting DCG SIG equal to VDD, a high logic level, or otherwise). By applying a high potential to the source and drain terminals of the transistor 307, the transistor 307 is placed into a depletion mode of operation. The capacitance of the transistor 307 operating in depletion mode is smaller than the capacitance of the transistor 307 operating in inversion mode, which is beneficial for low light conditions due to the increased conversion gain.

The capacitance of the floating diffusion node 106 in the HCG mode is less than the capacitance in the LCG mode, so that the voltage level used to completely reset the floating diffusion node 106 is relatively less than the LCG mode in the HCG mode. This is accomplished by enabling the select signal SEL _ HCG and resetting the high conversion gain power supply V_{RST_HCG}By switch 330 to level shifter power supply LVL VDD. The resulting voltage level of the reset signal RST in the LCG mode is lower than the voltage level of the reset signal RST in the HCG mode. As such, the reset voltage applied to the gate of the reset transistor 103 is adjusted depending on the selected capacitance at the FD node 106. Compensating the reset voltage when adjusting the conversion gain capacitance improves the achievable voltage swing at FD node 106, thus increasing the full well capacity and dynamic range of pixel cell 306.

The dual conversion gain feature disclosed herein provides a larger FD voltage swing and thus a greater dynamic range. When operating in the low conversion gain mode, a larger reset voltage applied to the reset transistor 103 increases the voltage across the transfer transistor 102, which improves charge transfer efficiency to allow for a faster frame rate in the video mode.

In fig. 4 and 5, signals SEL _ LCG and SEL _ HCG are asserted substantially simultaneously with reset signal RST. In other embodiments, depending on the desired conversion gain, the select signal SEL _ LCG or SEL _ HCG may be asserted before the reset signal RST is asserted. In one embodiment, this early assertion merely illustrates a signal propagation delay from the switch 330 or 340 through the reset generator 310 to the gate of the reset transistor 103. In one embodiment, this early assertion may be used to precharge the internal nodes of the reset generator 310, and may include an additional switch that isolates the reset generator 310 from the pixel cell 306. In the illustrated embodiment, reset transistor 103 is coupled to power rail VDD; however, in other embodiments, the reset transistor 103 may be coupled to a power supply rail RST _ VDD (e.g., 3.0V), which may have a higher voltage level than a logic level power supply rail VDD (e.g., 2.8V) coupled to other portions of the pixel circuit.

In the illustrated embodiment, two different power supplies V_{RST_LCG}And V_{RST_HCG}Is used to derive two different reset voltage levels of RST, one of which has a higher voltage level than the other. However, multiple conversion gain image sensors are contemplated herein, wherein three or more different power supply voltages may be used to provide three or more reset voltage levels to distinguish between conversion gains. In the illustrated embodiment, transistor 307 is configured as a single MOS capacitor coupled to one DCG signal to provide an adjustable capacitance to FD node 106. In other embodiments, multiple MOS capacitors may be coupled in parallel to FD node 106 and multiple DCG signals may be used to control the adjustable capacitance coupled to FD node 106. Other adjustable capacitance structures (e.g., metal-to-metal capacitors of switchable connection) may also be used.

In the present embodiment, a low conversion gain is used for a strong light condition (bright environment) and a high conversion gain is used for a weak light condition (dim environment). In other embodiments, two (or more) images of the same scene are taken in rapid succession or simultaneously, each using a different conversion gain, and the two images are combined into a composite image using on-chip or off-chip circuitry to obtain an image with a higher dynamic range. A composite image may be generated by using a low conversion gain image for bright regions in a scene while using a high conversion gain image for dark regions in the scene. For example, a user may select a high dynamic range setting for the image sensor, and thereafter the image sensor will automatically obtain the two images of a given scene in rapid succession, with the image sensor configured in low and high conversion gain modes.

In one embodiment, the threshold voltage of the transistor shown in FIG. 3 is 0.3V, V_{RST_LCG}Is 3.6V, V_{RST_HCG}Is 3.3V, RST _ VDD is 3.0V and VDD is 2.8V. Of course, other voltage level combinations may be used.

FIG. 6 is a block diagram illustrating a black day circuit 601 coupled to each bit line of a pixel array, according to an embodiment of the invention. The illustrated embodiment of the black day circuit 601 includes a reset transistor 603, a source follower transistor 604, a bit line select transistor 605, and an adjustable capacitance 607 (e.g., a MOS capacitor).

In the illustrated embodiment, each bit line is coupled to a column of pixel cells 306 to readout image data (in the form of image voltages) to readout circuitry 210. Each bit line is further coupled to a comparator 602, the comparator 602 comparing the image voltage to a black day threshold voltage (Vy)_BSTH) And (6) comparing. If the voltage on the corresponding bit line exceeds V_BSTHThen comparator 602 triggers operation of its corresponding black day circuit 601 by enabling bit line select transistor 605 via a bit line select control signal (e.g., BS1, BS2, etc.).

The black day circuit 601 operates to reduce or eliminate black dots that appear in bright portions of an image due to oversaturation of a given pixel and the resulting voltage collapse at FD node 106. Comparator 602 operates by threshold comparison to detect these dark day points in the image. Once the black-out point is determined to exist, the voltage on the corresponding bit line is reset to a default value by the black-out circuit 601. Since pixel cell 306 is a dual conversion gain (or even multiple conversion gain) pixel cell, black day circuit 601 resets the bit line to a selectable voltage depending on the currently selected conversion gain mode of pixel cell 306. To do so, each black day circuit 601 includes a structure similar to the pixel cell 306, but omits the photosensor and transfer transistor. As such, the black day circuit 601 is coupled to receive the multi-level reset signal RST from the reset generator 310 and the dual conversion gain signal DCG SIG also coupled into the pixel cell 306. Although fig. 6 illustrates the black day circuit 601 as a dual conversion gain circuit, it should be appreciated that other embodiments may implement a multiple conversion gain image sensor using more than two voltage levels for the RST signal and the DCG SIG.

The above explained process/operation may be described in terms of computer software and hardware. The described techniques may constitute machine-executable instructions embodied within a tangible machine (e.g., computer, image sensor) readable storage medium, that when executed by a machine, cause the machine to perform the described operations. Additionally, the processes/operations may be embodied in hardware, such as an application specific integrated circuit ("ASIC") or the like.

A tangible machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, image sensor, any device with a set of one or more processors, etc.). For example, a machine-readable storage medium includes recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

The foregoing description of illustrated embodiments of the invention, including what is described in the abstract, is not necessarily exhaustive or limited to the invention in the precise form disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (19)

1. A method of operating an image sensor, the method comprising:

adjusting a capacitance coupled to a circuit node within a pixel cell, wherein the circuit node is coupled to selectively receive image charge obtained by a photosensor of the pixel cell, wherein a conversion gain is selected from a plurality of conversion gains for the pixel cell by adjusting the capacitance;

selecting a voltage level from a plurality of voltage levels to be used as a reset signal when the reset signal is asserted, wherein the reset signal controls a reset of the circuit node during operation of the pixel cell, wherein the voltage level is selected in dependence on which of the plurality of conversion gains is selected by adjusting the capacitance;

asserting the reset signal to reset a voltage at the circuit node;

obtaining image charge at the photosensor;

transferring the image charge to the circuit node to thereby change the voltage at the circuit node; and

reading out image data indicative of the voltage at the circuit node.

2. The method of claim 1, wherein the circuit node comprises a Floating Diffusion (FD) node.

3. The method of claim 1, wherein adjusting the capacitance coupled to the circuit node comprises:

asserting a conversion gain signal coupled to a channel of a conversion gain transistor, wherein a gate of the conversion gain transistor is coupled to the circuit node.

4. The method of claim 3, wherein sources and drains of the channels of the conversion gain transistors are coupled together to receive the conversion gain signals together.

5. The method of claim 3, wherein establishing the conversion gain signal comprises:

setting the conversion gain signal to a high voltage level when the pixel cell is configured to a low conversion gain mode; and

setting the conversion gain signal to a low voltage level when the pixel cell is configured to a high conversion gain mode.

6. The method of claim 1, wherein the reset signal is coupled to a gate terminal of a reset transistor having a channel coupled between a high voltage rail and the circuit node.

7. The method of claim 6, wherein selecting the voltage level from a plurality of voltage levels to use as the reset signal when the reset signal is asserted comprises:

selecting the voltage level as a first voltage level when the pixel cell is configured to a low conversion gain mode; or

Selecting the voltage level as a second voltage level when configuring the pixel cell to a high conversion gain mode, wherein the first voltage level is higher than the second voltage level.

8. The method of claim 7, wherein the first and second voltage levels are higher than the high voltage rail to which the channel of the reset transistor is coupled.

9. The method of claim 7, wherein transferring the image charge to the circuit node comprises:

asserting a pass signal coupled to a gate of a pass transistor coupled between the circuit node and the photosensor,

wherein selecting the voltage level from a plurality of voltage levels is performed simultaneously with or prior to each assertion of the reset signal.

10. The method of claim 7, further comprising:

monitoring the surroundings of the image sensor in real time during operation of the image sensor;

selecting the low conversion gain mode when the ambient environment is considered bright; and

the high conversion gain mode is selected when the ambient environment is deemed to be dim.

11. The method of claim 1, further comprising:

configuring the image sensor to a first one of a low or high conversion gain mode;

obtaining a first image of a scene while the image sensor is in the first one of the low or high conversion gain modes;

automatically configuring the image sensor to a second one of the low or high conversion gain modes;

automatically obtaining a second image of the scene when the image sensor is in the second one of the low or high conversion gain modes; and

combining the first and second images into a composite image having a dynamic range individually greater than either of the first or second images.

12. The method of claim 1, further comprising:

outputting the image data as an image voltage on a bit line coupled to the pixel cell;

comparing the image voltage to a black day threshold voltage using a black day circuit coupled to the bit line; and

selectively resetting the bit line to a reset value based on the comparison,

wherein the black day circuit comprises:

a reset transistor having a gate terminal coupled to receive the reset signal; and

an adjustable capacitance that changes when the capacitance coupled to the circuit node within the pixel cell is adjusted.

13. An image sensor system, comprising:

a pixel array comprising a given pixel cell, the given pixel cell comprising:

a photosensor for capturing image charge;

a floating diffusion "FD" node coupled to receive the image charge from the photosensor;

an adjustable capacitance coupled to the FD node to change a conversion gain of the given pixel cell in response to a conversion gain signal; and

a reset transistor coupled to reset a voltage at the FD node in response to a reset signal applied to a gate terminal of the reset transistor; and

a control unit coupled to the pixel array, the control unit including logic that, when executed by the control unit, causes the control unit to perform operations including:

setting the conversion gain signal to change the adjustable capacitance;

selecting a voltage level for the reset signal when the reset signal is asserted to reset the FD node, wherein the voltage level is selected in dependence on a value selected for the adjustable capacitance; and

asserting the reset signal to reset the FD node.

14. The image sensor system of claim 13, wherein setting the conversion gain signal comprises:

setting the conversion gain signal to a high voltage level when the given pixel cell is configured to a low conversion gain mode; and

setting the conversion gain signal to a low voltage level when the given pixel cell is configured to a high conversion gain mode.

15. The image sensor system of claim 13, wherein the reset transistor comprises a channel coupled between a high voltage rail and the FD node.

16. The image sensor system of claim 15, wherein selecting the voltage level for the reset signal when the reset signal is asserted comprises:

selecting the voltage level as a first voltage level when the given pixel cell is configured to a low conversion gain mode; or

Selecting the voltage level as a second voltage level when the given pixel cell is configured to a high conversion gain mode, wherein the first voltage level is higher than the second voltage level.

17. The image sensor system of claim 16, wherein the first and second voltage levels are higher than the high voltage rail to which the channel of the reset transistor is coupled.

18. The image sensor system of claim 17, wherein selecting the voltage level from a plurality of voltage levels is performed at the same time or prior to each assertion of the reset signal.

19. The image sensor system of claim 13, further comprising:

a bit line coupled to the given pixel cell to output an image voltage from the given pixel cell;

a comparator coupled to the bit line to compare the image voltage to a black day threshold voltage; and

a black day circuit that couples the bit line and resets the bit line in response to an output of the comparator, the black day circuit including:

another reset transistor having a gate terminal coupled to receive the reset signal; and

another adjustable capacitance that changes in response to the conversion gain signal.