HK1179757B - Image sensor with doped transfer gate - Google Patents

Description

Image sensor with doped transfer gate

Technical Field

The present disclosure relates generally to image sensors, and more particularly, to image sensors having an implant region formed only in a portion of the transfer gate during implantation of the source/drain regions.

Background

Fig. 1 is a cross-sectional view of a portion of an image sensor according to the prior art. The image sensor 100 includes a substrate 102 having a photodetector 104, a threshold implant 106, a well 108, a Lightly Doped Drain (LDD)110, and a heavy source/drain implant region 112 formed therein. The combination of the well 108, LDD 110, and source/drain implant regions 112 act as charge/voltage conversion regions 114. The well 108 also operates as an anti-punch through region between the LDD 100 or source/drain implant region 112 to the photodetector 104.

The threshold implants 106 and wells 108 are formed prior to establishing the transfer gate 116, while the photodetector 104 and LDD 110 are formed after forming the transfer gate 116. Because the photodetector 104 and the LDD 110 are built after the transfer gate 116, the photodetector 104 and the LDD 110 are self-aligned to the edge of the transfer gate 116.

The source/drain implant regions 112 are implanted into the well 108 after forming sidewall spacers 118 along the outside of the transfer gate 116. Source/drain implant regions 112 are formed when other source/drain implant regions (e.g., source/drain implant regions of a transistor) are formed in the image sensor. Source/drain implant regions 112 are disposed below contacts 120 and extend from contacts 120 into well 108. At least a portion of each transfer gate 116 is also implanted with a dopant during the source/drain implant to form a doped region 122. The doped region 122 advantageously affects the transfer gate 116 work function and increases the transfer gate conductivity.

The doping level of the source/drain implant regions, including source/drain implant region 112, is typically high to maintain high conductivity. Because of the very high doping level, the implant completely destroys the lattice structure and converts the single crystalline structure of the well 108, LDD 110, and substrate layer 102 into an amorphous structure. The amorphous structure requires a subsequent heat treatment step to rearrange back to a single crystal structure. However, as technology advances, the post source/drain implant thermal budget is significantly reduced to reduce dopant lateral diffusion, so the implant damage cannot be fully repaired by subsequent thermal processing.

One consequence of lattice damage or defects is the extremely high rate of dark current generation. Lattice damage also serves as an adsorption site for metal contaminants, which is undesirable because metal contaminants are also known to produce extremely high dark currents. To avoid damage to the substrate, heavy source/drain implants in the charge-to-voltage conversion region are not performed during the fabrication of some image sensors. However, as previously described, the heavy source/drain implant forms a doped region 122 in the transfer gate 116. Removing the doped region 122 will change the transfer gate 116 workfunction and may negatively affect the electrical operation of the transfer gate.

Disclosure of Invention

An image sensor includes an array of pixels, and at least one pixel includes a photodetector formed in a substrate layer, a transfer gate disposed adjacent to the photodetector, and a charge-to-voltage conversion region disposed adjacent to the transfer gate. The charge-to-voltage conversion region may be created by a combination of a well and a Lightly Doped Drain (LDD). In one embodiment according to the present invention, a single photodetector transfers the collected charge to a single charge-to-voltage conversion region. In another embodiment in accordance with the invention, a plurality of photodetectors transfer the collected charge to a common charge-to-voltage conversion region shared by the photodetectors.

When dopants are implanted into the substrate layer to form source/drain implant regions, the implant regions are formed in only a portion of each transfer gate. The implant region is not formed within the charge/voltage region. Each charge-to-voltage conversion region is substantially free of the implanted region. Embodiments in accordance with the invention can include source/drain implants under physical contacts to the charge-to-voltage conversion region.

A method for fabricating an image sensor having an array of pixels, at least one pixel including a photodetector, and two or more adjacent pixels sharing a common charge-to-voltage conversion region, includes forming a plurality of transfer gates over a surface of a substrate layer. Transfer gates are disposed between respective shared charge-to-voltage conversion regions and photodetectors associated with the shared charge-to-voltage conversion regions. The transfer gates associated with each shared charge-to-voltage conversion region are spaced apart by a predetermined distance to form a conversion region gap. The charge-to-voltage conversion region may be formed with a Lightly Doped Drain (LDD) formed.

A masking conformal dielectric layer is then deposited over the image sensor, and the masking conformal dielectric layer covers the transfer gate and fills the transfer region gaps. The masking conformal dielectric layer is etched to form sidewall spacers along outer edges of the respective transfer gates. After the etching, a portion of the masking conformal dielectric layer remains in each transfer region gap and is disposed over a surface of the substrate layer in each transfer region gap. Performing a heavily doped source/drain implant to form source/drain implant regions in the image sensor and implant regions only in the transfer gate. A masking conformal dielectric layer in each transfer region gap masks the source/drain implants such that each charge/voltage transfer region is substantially free of the implant regions.

Drawings

Embodiments of the invention may be better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale.

FIG. 1 is a cross-sectional view of a portion of an image sensor according to the prior art;

FIG. 2 is a simplified block diagram of an image capture device in an embodiment in accordance with the invention;

FIG. 3 is a block diagram of a top view of an image sensor suitable for use as image sensor 206 in an embodiment in accordance with the invention;

FIG. 4 is a schematic diagram of an active pixel suitable for use as pixel 302 in embodiments in accordance with the invention;

FIG. 5 is a cross-sectional view of a row select transistor 414 in an embodiment in accordance with the invention;

FIG. 6 is a simplified block diagram of a top view of a portion of a pixel suitable for use in image sensor 206 in an embodiment in accordance with the invention;

FIG. 7 is a simplified block diagram of a top view of a two by two shared pixel arrangement suitable for use in image sensor 206 in an embodiment in accordance with the invention;

FIG. 8 is a simplified block diagram of a top view of a two by two shared pixel arrangement suitable for use in image sensor 206 in an embodiment in accordance with the invention;

FIGS. 9-15 are cross-sectional views of a portion of an image sensor in an embodiment in accordance with the invention for depicting a first method for forming an implant region in only a portion of a transfer gate during implantation of source/drain regions;

16-19 are cross-sectional views of a portion of an image sensor in an embodiment in accordance with the invention to illustrate a second method for forming an implant region in only a portion of a transfer gate during implantation of source/drain regions;

FIG. 20 is a cross-sectional view of a portion of an image sensor fabricated in a third method for forming an implant region in only a portion of a transfer gate during implantation of source/drain regions in accordance with an embodiment of the present invention; and

fig. 21-23 are cross-sectional views of a portion of an image sensor in an embodiment in accordance with the invention to illustrate a fourth method for forming an implant region in only a portion of the transfer gate during implantation of source/drain regions.

Detailed Description

In the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of "a" and "the" includes plural references, the meaning of "in …" includes "in …" and "on …". The term "couple" means either a direct electrical connection between the items coupled, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" means a single component or multiple components (active or passive) that are connected together to provide a desired function. The term "signal" means at least one charge packet, current, voltage, or data signal.

Furthermore, directional terminology, such as "on … …," "over … …," "top," "bottom," is used with reference to the orientation of the figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. The directional terms, when used in connection with layers of an image sensor wafer or a corresponding image sensor, are intended to be broadly interpreted, and thus should not be interpreted to exclude the presence of one or more intervening layers or other intervening image sensor features or elements. Thus, a given layer described herein as being formed on or over another layer may be separated from the other layer by one or more additional layers.

And finally, the term "substrate layer" should be understood to mean a semiconductor-based material including, but not limited to, silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers formed on semiconductor substrates, well regions or buried layers formed in semiconductor substrates, and other semiconductor structures.

Referring to the drawings, like numbers indicate like parts throughout the views.

FIG. 2 is a simplified block diagram of an image capture device in an embodiment in accordance with the invention. In fig. 2, the image capture device 200 is implemented as a digital camera. Those skilled in the art will recognize that a digital camera is but one example of an image capture device that may be utilized and have the image sensor of the present invention. Other types of image capture devices, such as cell phone cameras, scanners, and digital video cameras, for example, may be used with the present invention.

In digital camera 200, light 202 from a subject scene is input to an imaging stage 204. The imaging stage 204 may include conventional elements such as lenses, neutral density filters, apertures, and shutters. Light 202 is focused by imaging stage 204 to form an image on image sensor 206. The image sensor 206 captures one or more images by converting incident light into electrical signals. The digital camera 200 further includes a processor 208, memory 210, a display 212, and one or more additional input/output (I/O) elements 214. Although shown as separate elements in the embodiment of fig. 2, imaging stage 204 may be integrated with image sensor 206 and possibly with one or more additional elements of digital camera 200 to form a camera module. For example, a processor or memory may be integrated with the image sensor 206 in the camera module in an embodiment in accordance with the invention.

For example, the processor 208 may be implemented as a microprocessor, Central Processing Unit (CPU), Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), or other processing device or a combination of multiple such devices. The various elements of imaging stage 204 and image sensor 206 may be controlled by timing signals or other signals supplied from processor 208.

The memory 210 may be configured as any type of memory, such as, for example, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, disk-based memory, removable memory, or other types of storage elements, in any combination. A given image captured by the image sensor 206 may be stored by the processor 208 in the memory 210 and presented on the display 212. The display 212 is typically an active matrix color Liquid Crystal Display (LCD), although other types of displays may be used. The additional I/O elements 214 may include, for example, various on-screen controls, buttons or other user interfaces, network interfaces, or memory card interfaces.

It should be understood that the digital camera shown in fig. 2 may include additional or alternative elements of the type known to those skilled in the art. Elements not specifically shown or described herein may be selected from elements known in the art. As previously mentioned, the present invention may be implemented in a wide variety of image capture devices. Moreover, certain aspects of the embodiments described herein may be implemented, at least in part, in the form of software executed by one or more processing elements of an image capture device. It will be apparent to those skilled in the art that such software may be implemented in a simple manner in view of the teachings provided herein.

Referring now to FIG. 3, a block diagram of a top view of an image sensor suitable for use as image sensor 206 in an embodiment in accordance with the invention is shown. Image sensor 300 includes a plurality of pixels 302, typically arranged in rows and columns, that form an imaging region 304. In an embodiment in accordance with the invention, each pixel 302 includes a photosensitive region (not shown).

Image sensor 300 further includes a column decoder 306, a row decoder 308, digital logic 310, a plurality of analog or digital output circuits 312, and a timing generator 314. Each column of pixels in imaging area 304 is electrically connected to output circuit 312. Timing generator 314 may be used to generate signals (including signals needed to read out signals from imaging area 304) for operating image sensor 300.

In an embodiment in accordance with the invention, image sensor 300 is implemented as an x-y addressable image sensor, such as, for example, a Complementary Metal Oxide Semiconductor (CMOS) image sensor. Thus, column decoder 306, row decoder 308, digital logic 310, analog or digital output channel 312, and timing generator 314 are implemented as standard CMOS electronic circuits operatively connected to imaging area 304.

The functionality associated with the sampling and readout of the imaging region 304 and the processing of the corresponding image data may be implemented, at least in part, in the form of software stored in the memory 210 (see fig. 2) and executed by the processor 208. Portions of the sampling and readout circuitry may be arranged external to image sensor 300, or integrally formed with imaging region 304 on a common integrated circuit having, for example, a photodetector and other elements of the imaging region. Those skilled in the art will recognize that other peripheral circuit configurations or architectures may be implemented in other embodiments in accordance with the invention.

Referring now to fig. 4, a schematic diagram of an active pixel suitable for use as pixel 302 in an embodiment in accordance with the invention is shown. Active pixel 400 includes photodetector 402, transfer gate 404, charge-to-voltage conversion mechanism 406, reset transistor 408, potential V_DD410. An amplifier transistor 412 and a row select transistor 414. The reset transistor 408, the amplifier transistor 412, and the row select transistor 414 are implemented as field effect transistors in an embodiment in accordance with the invention. The source/drain terminal 416 of the row select transistor 414 is connected to the source/drain terminal 418 of the amplifier transistor 412, while the source/drain terminal 420 is connected to the output 422. The source/drain terminal 424 of the reset transistor 408 and the source/drain terminal 426 of the amplifier transistor 414 are connected to a potential V_DD410. The source/drain terminal 428 of the reset transistor 408 and the gate 430 of the amplifier transistor 412 are connected to the charge-to-voltage conversion mechanism 406.

Fig. 5 is a cross-sectional view of a row select transistor 414 in an embodiment in accordance with the invention. Source/drain implant regions 500, 502 are formed in the substrate layer 504 during the source/drain implant process. The source/drain implants 500 and contacts 506 form one source/drain terminal (418 or 420) of the row select transistor 414, while the source/drain implants 502 and contacts 508 form the other source/drain terminal (420 or 418) of the row select transistor 414. An electrode 510 is formed between the source/drain implant regions 500, 502. Electrode 510 and contact 512 form the gate of row select transistor 414. Other transistors in the image sensor include source/drain implant regions formed during source/drain implants.

When one or more dopants are implanted within the substrate layer 504 to form source/drain implant regions (e.g., source/drain implant regions 500, 502) in an image sensor, embodiments of the invention create at least one implant region in a portion of the upper surface of the transfer gate. Dopant implantation of source/drain regions does not create implanted regions within the charge-to-voltage conversion region. The charge-to-voltage conversion region remains substantially free of the implanted region. Note that in some embodiments according to the invention, the charge-to-voltage conversion region may include an implant region to the charge-to-voltage conversion region under the contact (see, e.g., implant region 714 under contact 712 in fig. 7). Such a contact implant region may be created during dopant implantation of the source/drain regions by patterning a masking layer to define openings in which contact regions are to be formed while masking regions of the charge/voltage conversion region that do not have the contacts. The implanted region under the contact does not substantially extend outside the area for the contact. One advantage of including source/drain implant regions under the contacts is that the implant regions can reduce contact resistance.

Thus, as used herein, the term "implant region" is defined as a region formed in the transfer gate when the one or more dopants are implanted within the substrate layer to form source/drain implant regions in the image sensor.

Referring now to FIG. 6, a simplified block diagram of a top view of a portion of a pixel suitable for use in image sensor 206 in an embodiment in accordance with the invention is shown. Pixel 600 includes a photodetector 602, a transfer gate 604, and a charge-to-voltage conversion region 606. The charge-to-voltage conversion region 606 includes a contact 608. In an embodiment in accordance with the invention, the photodetector 602 is implemented as a photodiode or pinned photodiode and the charge-to-voltage conversion region 606 is implemented as a floating diffusion.

As previously discussed, pixel 600 may also include a reset transistor and an amplifier transistor (not shown in the figure) connected to the charge-to-voltage conversion region through contact 608. Pixel 600 may further include a row select transistor (not shown) connected to the amplifier transistor. Such components are well known in the art and therefore are not shown in fig. 6 for purposes of brevity and ease of understanding.

The photodetector 602 collects and stores charge generated by incident light. When a bias voltage is applied to the transfer gate 604, the collected charge packets are transferred from the photodetector 602 to the charge-to-voltage conversion region 606. An amplifier transistor (not shown) connected to charge-to-voltage conversion region 606 through contact 608, such as a source follower transistor, converts the charge packet into a voltage signal representative of the amount of charge on charge-to-voltage conversion region 606. Then, the voltage signal is transmitted to a column output line by the amplifier transistor.

FIG. 7 is a simplified block diagram of a top view of a two-by-one shared pixel arrangement suitable for use in image sensor 206 in an embodiment in accordance with the invention. The pixel arrangement 700 includes two photodetectors 702, 704, transfer gates 706, 708 adjacent to each photodetector 702, 704, respectively, and a common charge-to-voltage conversion region 710 shared by the two photodetectors 702, 704. The common charge-to-voltage conversion region 710 includes a contact 712. Typically, the light detector 702 is disposed in a row (or column) of pixels of a pixel array and the light detector 704 is positioned in an adjacent row (or column) of pixels of the pixel array.

Bias voltages are selectively applied to the transfer gates 706, 708 to selectively and respectively transfer the collected charge packets from the photodetectors 702, 704 to the charge-to-voltage conversion region 710. An amplifier transistor (not shown) connected to the charge-to-voltage conversion region 710 through a contact 712 converts each charge packet into a voltage signal representative of the amount of charge on the charge-to-voltage conversion region 710. Then, the voltage signal is transmitted to a column output line by an amplifier transistor.

Source/drain contact implant regions 714 are disposed under the contacts 712 in embodiments in accordance with the invention. Source/drain contact implant regions 714 are formed during dopant implantation of the source/drain regions. Source/drain contact implant regions 714 may be created by patterning a masking layer to define openings in which contacts 712 are to be formed while masking regions of charge-to-voltage conversion regions 710 not covered by contacts 712. The source/drain contact implant regions 714 do not substantially extend outside the area for the contact 712.

Referring now to FIG. 8, a simplified block diagram of a top view suitable for use in a two by two shared pixel arrangement in image sensor 206 is shown, in an embodiment according to the invention. Pixel arrangement 800 includes four photodetectors 802, 804, 806, 808, transfer gates 810, 812, 814, 816 adjacent to the respective photodetectors 802, 804, 806, 808, and a common charge-to-voltage conversion region 818 shared by the four photodetectors 802, 804, 806, 808. The common charge-to-voltage conversion region 818 includes a contact 820. Typically, the photodetectors 802, 806 are disposed in a row (or column) of pixels of a pixel array and the photodetectors 804, 808 are positioned in adjacent rows (or columns) of pixels of the pixel array.

Bias voltages are selectively applied to the transfer gates 810, 812, 814, 816 to selectively and respectively transfer the collected charge packets from the photodetectors 802, 804, 806, 808 to the charge-to-voltage conversion region 818. An amplifier transistor (not shown) connected to the charge-to-voltage conversion region 818 by a contact 820 converts each charge packet into a voltage signal representative of the amount of charge on the charge-to-voltage conversion region 818. Then, the voltage signal is transmitted to a column output line by an amplifier transistor.

Although two-by-one and two-by-two arrangements have been described, other embodiments according to the invention are not limited to such pixel arrangements. Different pixel arrangements may be used with the present invention. By way of example only, pixel arrangements such as three by two and four by two may be used in other embodiments in accordance with the invention. In addition, the pixel array is not limited to row and column arrangements. The pixel array may be arranged in any desired pattern, such as, for example, a hexagonal pattern.

Fig. 9-15 are cross-sectional views of a portion of an image sensor in an embodiment in accordance with the invention for depicting a first method for forming an implant region in only a portion of a transfer gate during implantation of source/drain regions. First, as shown in FIG. 9, the structure of the image sensor 900 has been processed to a stage where the photo detectors 902, threshold implants 904, wells 906, pad oxide 908, and transfer gates 910 have been formed in or on a substrate layer 912. The spaces 914 between the transfer gates 910 are referred to herein as transition region gaps 914.

The threshold implant 904, the well 906, and the substrate layer 912 have a first conductivity type, while the photodetector 902 has a second conductivity type opposite the first conductivity type. By way of example only, the threshold implant 904, the well 906, and the substrate layer 912 have an n conductivity type, while the photodetector 902 has a p conductivity type.

Then, as shown in fig. 10, a masking layer 1000 (e.g., a photoresist layer) is deposited over the image sensor 900 and patterned to form an opening 1001. The opening 1001 exposes a portion of each transfer gate 910 and a surface 1002 of the substrate layer 912 in the transition region gap 914.

Next, one or more dopant implants (represented by arrows 1100) are implanted through the opening 1001 and into the surface 1002 to form a Lightly Doped Drain (LDD)1102 in the well 906 (fig. 11). The combined LDD 1102 and well 906 act as a charge-to-voltage conversion region 1104. In an embodiment in accordance with the invention, the LDDs 1102 have a conductivity type opposite that of the well 906. Implanting the dopants into the well 906 to form the LDDs 1102 also forms doped regions 1106 in a portion of the upper region of each transfer gate 910.

Next, masking layer 1000 is removed and conformal dielectric layer 1200 is deposited over image sensor 900 (fig. 12). Masking conformal dielectric layer 1202 is deposited over conformal dielectric layer 1200. In an embodiment in accordance with the invention, conformal dielectric layer 1200 is implemented as a nitride layer and masking conformal dielectric layer 1202 is implemented as an oxide layer. For conformal dielectric layer 1200 and masking conformal dielectric layer 1202, different materials may be used according to other embodiments of the invention. For example, any combination of nitride/oxide, oxide/oxide, nitride/nitride, or oxide/nitride may be used.

The thickness of masking conformal dielectric layer 1202 is selected to be thick enough so that it fills the transition region gap 914 or fills the bottom of transition region gap 914 after a subsequent etch process is performed. By way of example only, the thickness of masking conformal dielectric layer 1202 is at least half of the distance between transfer gates 910 or the transition region gap 914. In other embodiments according to the invention, masking conformal dielectric layer 1202 may be deposited to different thicknesses.

The transfer region gap 914 is designed in one embodiment to be a minimum distance to ensure that the transfer region gap 914 is filled by the conformal dielectric layer 1202. Implementing the switching region gap 914 at its minimum width also reduces the capacitance of the charge-to-voltage switching region, which increases the pixel switching gain.

The masking conformal dielectric layer 1202 and conformal dielectric layer 1200 are then etched to expose the top surface of the transfer gate 910 (fig. 13). By way of example only, masking conformal dielectric layer 1202 and conformal dielectric layer 1200 are anisotropically etched in a vertical direction with a reactive ion etch or a plasma etch in embodiments in accordance with the invention.

The etch forms sidewall spacers 1300 along the outer sides or edges (sides opposite the transition region gap 914) of the transfer gates 910. A conformal dielectric layer 1200 covers the inner edges of the transfer gate 910 and the surface of the substrate 912. The etch also causes masking conformal dielectric layer 1202 to fill or completely fill the bottom of the remaining portion of the transition region gap 914 not filled by conformal dielectric layer 1200.

Next, as shown in FIG. 14, masking layer 1400 is deposited over image sensor 900 and patterned to form openings 1402, openings 1402 exposing a portion of the upper region of each transfer gate 910, conformal dielectric layer 1200 in the transfer region gap 914, and masking conformal dielectric layer 1202. One or more dopants are implanted (represented by arrows 1404) through the opening 1402 and into a portion of the transfer gate 910 during a source/drain implant process to form a source/drain implant region (not shown) in the image sensor 900 and an implant region 1406 in the transfer gate 910. In an embodiment in accordance with the invention, the implanted region 1406 is of an opposite conductivity type to the well 906. Masking conformal dielectric layer 1202 acts as a mask during implant 1404 and prevents dopants in implant 1404 from being implanted into charge-to-voltage conversion region 1104.

Next, masking layer 1400 is removed, as shown in FIG. 15. As shown in fig. 15, the image sensor 900 includes an implanted region 1406 only in the transfer gate 910. The charge-to-voltage conversion region 1104 (well 906 and LDD 1102) is substantially free of implanted regions. Image sensor 900 can now be further processed to complete the fabrication of image sensor 900. Such fabrication processes are well known in the art and therefore are not described in detail herein.

Fig. 16-19 are cross-sectional views of a portion of an image sensor in an embodiment in accordance with the invention to illustrate a second method for forming an implant region in only a portion of a transfer gate during implantation of source/drain regions. The processing techniques shown in fig. 16-19 replace the fabrication steps depicted in fig. 12-15. The process shown in fig. 16 immediately follows the process illustrated in fig. 11. A masking conformal dielectric layer 1600 is deposited over the image sensor 1602. The thickness of masking conformal dielectric layer 1600 is selected to be thick enough so that it fills the transition region gap 914 or completely fills the bottom of the transition region gap 914 after a subsequent etch process is performed. In an embodiment in accordance with the invention, masking conformal dielectric layer 1600 is implemented as a nitride layer. In other embodiments according to the invention, masking conformal dielectric layer 1600 can be made of different materials. For example, silicon dioxide, silicon nitride, hafnium oxide, or any type of dielectric film may be used.

Next, as shown in FIG. 17, the masking conformal dielectric layer 1600 is etched to expose the upper surface of the transfer gate 910. The etch causes the conformal dielectric layer 1600 to form sidewall spacers along the outside of the transfer gate 910 and fill the transfer region gap 914 or completely fill the bottom of the transfer region gap 914.

Next, a resist layer 1800 is deposited over image sensor 1602 and patterned to form an opening 1802. An example of the resist layer 1800 is a photoresist layer. Opening 1802 exposes a top surface of the blanket conformal dielectric layer 1600 in the transition region gap 914 and a portion of the top surface of each transfer gate 910 (fig. 18). One or more dopants are implanted (represented by arrows 1804) through the opening 1802 and into a portion of the transfer gate 910 during the source/drain implant process to form a source/drain implant region (not shown) in the image sensor 1602 and an implant region 1806 in the transfer gate 910. In an embodiment in accordance with the invention, the implanted region 1806 has a conductivity type opposite that of the well 906. Masking conformal dielectric layer 1600 acts as a mask during implant 1804 and prevents dopants in implant 1804 from implanting into charge-to-voltage conversion region 1104 (well 906 and LDD 1102).

Next, the masking layer 1800 is removed, as shown in fig. 19. As shown in fig. 19, the image sensor 1602 includes an implanted region 1806 only in the transfer gate 910. The charge-to-voltage conversion region 1104 is substantially free of implanted regions. Image sensor 1602 can now be further processed to complete the fabrication of image sensor 1602. Such fabrication processes are well known in the art and therefore are not described in detail herein.

Referring now to fig. 20, shown is a cross-sectional view of a portion of an image sensor fabricated with a third method for forming an implant region in only a portion of the transfer gate during implantation of source/drain regions, in an embodiment in accordance with the invention. Image sensor 2000 in fig. 20 differs from image sensor 900 in fig. 15 in that two layers of conformal dielectric layers 2002, 2004 are deposited over image sensor 2000 before masking conformal dielectric layer 2006 is deposited over image sensor 2000. Two layers of conformal dielectric layers 2002, 2004 and a masking conformal dielectric layer 2006 are shown in the sidewall spacer 2008 and fill the transition region gap 914.

In an embodiment in accordance with the invention, conformal dielectric layer 2002 is implemented as an oxide layer, conformal dielectric layer 2004 is implemented as a nitride layer, and masking conformal dielectric layer 2006 is implemented as an oxide layer. In other embodiments according to the invention, the dielectric layers 2002, 2004, and 2006 can be made of any combination of insulators (e.g., oxide/nitride/oxide or oxide/nitride or oxide/nitride or any other dielectric material).

Image sensor 2000 is formed by following the process depicted in fig. 12-15, except that in the step shown in fig. 12, conformal dielectric layer 2002 is first deposited over image sensor 2000, conformal dielectric layer 2004 is then deposited over conformal dielectric layer 2002, and masking conformal dielectric layer 2006 is deposited over conformal dielectric layer 2004. The image sensor 2000 is then processed using the fabrication steps shown in fig. 13 and 14 to produce the structure illustrated in fig. 20.

Fig. 21-23 are cross-sectional views of a portion of an image sensor in an embodiment in accordance with the invention to illustrate a fourth method for forming an implant region in only a portion of a transfer gate during implantation of source/drain regions. The processing steps of fig. 21 immediately follow fig. 11. A masking layer 2100, such as a photoresist layer, is deposited over the image sensor 2102 and patterned to form an opening 2104. The opening 2104 exposes a portion of the top surface of the transfer gate 910. Masking layer 2100 is patterned using techniques that allow finer patterning and extremely small dimensions. By way of example only, in embodiments according to the invention, masking layer 2100 is patterned using Deep Ultraviolet (DUV) lithography, Extreme Ultraviolet (EUV) lithography, immersion lithography, or x-ray lithography.

Next, as shown in fig. 22, one or more dopants are implanted (represented by arrows 2200) through the opening 2104 and into a portion of the transfer gate 910 during a source/drain implantation process to form a source/drain implant region (not shown) in the image sensor 2102 and an implant region 2202 in the transfer gate 910. In an embodiment in accordance with the invention, implanted region 2202 has an opposite conductivity type than well 906. The portion of masking layer 2100 disposed between transfer gates 910 (in the transition region gap 914) prevents implant 2200 from implanting within charge/voltage transition region 1104 (well 906 and LDD 1102).

Next, as shown in fig. 23, masking layer 2100 is removed. As shown in fig. 23, the image sensor 2102 includes an implanted region 2202 only in the transfer gate 910. The charge-to-voltage conversion region 1104 is substantially free of implanted regions. The image sensor 2102 may now be further processed to complete the fabrication of the image sensor 2102. Such fabrication processes are well known in the art and therefore are not described in detail herein.

Advantages of the invention include forming an implant region in the transfer gate without forming an implant region within the charge-to-voltage conversion region when the source/drain region is formed in an image sensor. Preventing heavily doped source/drain implants from implanting the charge-to-voltage conversion region increases charge-to-voltage conversion gain or sensitivity. The invention also eliminates the formation of lattice defects caused by the heavy source/drain implant and reduces dark current in this region.

Parts list

100 image sensor

102 substrate

104 photo detector

106 threshold implant

108 trap

110 lightly doped drain

112 source/drain implant

114 charge-to-voltage conversion region

116 transfer gate

118 sidewall spacer

120 contact

122 doped region in the transfer gate

200 image capturing device

202 light

204 imaging stage

206 image sensor

208 processor

210 memory

212 display

214 other input/output (I/O) elements

300 image sensor

302 pixel

304 imaging area

306 column decoder

308 row decoder

310 digital logic

312 multiple analog or digital output circuits

314 timing generator

400 pixels

402 light detector

404 transfer gate

406 charge-to-voltage conversion region

408 reset transistor

410 potential

412 amplifier transistor

414 row select transistor

416 source/drain terminals

418 source/drain terminals

420 source/drain terminal

422 output

424 source/drain terminals

426 source/drain terminal

428 source/drain terminal

430 grid

500 source/drain implant

502 source/drain implant

504 substrate layer

506 contact

508 contact

510 electrode

512 contact

600 pixel

602 optical detector

604 transfer gate

606 charge-to-voltage conversion region

700 pixel

702 optical detector

704 photo detector

706 transfer gate

708 transfer gate

710 charge-to-voltage conversion region

712 contact

714 source/drain contact implantation

800 pixel

802 light detector

804 optical detector

806 photodetector

808 photo detector

810 transfer gate

812 transfer gate

814 transfer gate

816 transfer gate

818 charge-to-voltage conversion region

820 contact

900 image sensor

902 optical detector

904 threshold implant

906 trap

908 pad oxide

910 transfer gate

912 substrate layer

914 transition region gap

1000 resist layer

1002 surface of the substrate layer

1100 dopant implantation

1102 lightly doped drain

1104 Charge-to-voltage conversion region

1106 doped region in transfer gate

1200 conformal dielectric layer

1202 masking a conformal dielectric layer

1300 sidewall spacer

1400 resist layer

1402 opening

1404 dopant implantation

1406 source/drain implant regions

1600 mask conformal dielectric layer

1602 image sensor

1800 resist layer

1802 opening

1804 dopant implantation

1806 Source/Drain implant

2000 image sensor

2002 conformal dielectric layer

2004 conformal dielectric layer

2006 masking conformal dielectric layer

2008 sidewall spacer

2100 resist layer

2102 image sensor

2104 opening

2200 dopant implantation

2202 source/drain implanted region

Claims (13)

1. An image sensor, comprising:

at least one photodetector formed in the substrate layer;

a well comprising a charge-to-voltage conversion region formed in the substrate layer;

a transfer gate disposed between each photodetector and the charge-to-voltage conversion region; and

a first implant region comprising a first dopant disposed over a second implant region comprising a second dopant, wherein the first and second implant regions extend from an edge of the transfer gate overlying the charge-to-voltage conversion region and are disposed only in a portion of each transfer gate, wherein the charge-to-voltage conversion region comprises the first dopant of the first implant region extending away from the transfer gate from below the edge of the transfer gate, wherein the first and second dopants have a conductivity type opposite to a conductivity type of the well.

2. The image sensor of claim 1, wherein the image sensor includes two photodetectors that share the charge-to-voltage conversion region.

3. The image sensor of claim 2, further comprising a masking conformal dielectric layer disposed over a surface of the substrate layer between the transfer gates associated with the shared charge-to-voltage conversion region and filling at least a bottom of a space between the two transfer gates.

4. The image sensor of claim 3, further comprising a conformal dielectric layer covering an inner edge of each transfer gate and disposed between the masking conformal dielectric layer and the surface of the substrate layer.

5. The image sensor of claim 1, wherein the first and second implant regions extend laterally within the transfer gate less than an entire width of an upper surface of the transfer gate.

6. The image sensor of claim 1, wherein the first dopant of the first implant region included in the charge-to-voltage conversion region is a lightly doped drain formed in the well.

7. An image sensor, comprising:

a plurality of pixels, each pixel including a photodetector and a transfer gate adjacent to the photodetector, wherein the pixels are arranged such that two adjacent pixels share a common charge-to-voltage conversion region, wherein the common charge-to-voltage conversion region is included in a well having a conductivity type; and

a first implant region comprising a first dopant disposed over a second implant region comprising a second dopant, wherein the first and second implant regions extend from an edge of the transfer gate overlying the charge-to-voltage conversion region and are disposed only in a portion of each transfer gate, wherein each common charge-to-voltage conversion region comprises the first dopant of the first implant region extending away from the transfer gate from below the edge of the transfer gate, wherein the first and second dopants have a conductivity type different from a conductivity type of the well.

8. The image sensor of claim 7, further comprising a masking conformal dielectric layer disposed over a surface of a substrate layer between the transfer gates associated with the common charge-to-voltage conversion region, and wherein the masking conformal dielectric layer fills at least a bottom of a space between the two transfer gates.

9. The image sensor of claim 8, further comprising a conformal dielectric layer covering an inner edge of each transfer gate and disposed between the masking conformal dielectric layer and the surface of the substrate layer.

10. The image sensor of claim 7, wherein the first and second implant regions extend laterally within the transfer gate less than an entire width of an upper surface of the transfer gate.

11. A method for fabricating an image sensor, wherein the image sensor comprises a plurality of pixels, each pixel including a photodetector, wherein the pixels are arranged such that two adjacent pixels share a common charge-to-voltage conversion region, the method comprising:

forming a plurality of transfer gates over a surface of a substrate layer, wherein a transfer gate is disposed between a respective shared charge-to-voltage conversion region and a respective photodetector associated with the shared charge-to-voltage conversion region and the transfer gates associated with the respective shared charge-to-voltage conversion regions are separated by a predetermined distance to form a conversion region gap;

depositing a masking conformal dielectric layer over the image sensor, wherein the masking conformal dielectric layer covers the plurality of transfer gates and fills the respective transfer region gaps;

etching the masking conformal dielectric layer to form sidewall spacers along outer edges of the respective transfer gates, wherein a portion of the masking conformal dielectric layer remains in the respective transfer region gaps and is disposed over the surface of the substrate layer in the respective transfer region gaps; and

implanting a plurality of source/drain regions in the substrate layer, wherein implant regions are formed in the plurality of transfer gates and the masking conformal dielectric layer in each transfer region gap masks the source/drain implants such that each charge/voltage transfer region is substantially free of the implant regions.

12. The method of claim 11, further comprising depositing a conformal dielectric layer over the image sensor prior to depositing the masking conformal dielectric layer.

13. The method of claim 12, wherein etching the masking conformal dielectric layer to form sidewall spacers along outer edges of respective transfer gates comprises etching the masking conformal dielectric layer and the conformal layer to form sidewall spacers along outer edges of respective transfer gates, wherein the masking conformal dielectric layer and the conformal layer fill the transfer region gaps.