HK1170845A - Method for forming photodetector isolation in imagers - Google Patents

Description

Method of forming photodetector isolation in an imager

Technical Field

The present invention relates to image sensors for use in digital cameras and other types of image capture devices, and in particular to Complementary Metal Oxide Semiconductor (CMOS) image sensors. More particularly, the present invention relates to photodiode isolation in CMOS image sensors and methods for producing such isolation.

Background

Image sensors capture images using thousands to millions of pixels, typically configured in an array. Fig. 1 depicts a top view of a pixel typically used in a CMOS image sensor according to the prior art. The pixel 100 includes a Photodetector (PD)102 that collects charge in response to incident light. Before reading out the charge of the photodetector 102, an appropriate signal is applied to the gate (RG) of the reset transistor via contact 104 to reset the charge-to-voltage conversion region (FD)106 to a known potential VDD. Charge is then transferred from the photodetector 102 to the charge-to-voltage conversion region 106 when the transfer transistor is enabled by applying an appropriate signal to the Transfer Gate (TG) using the contact 108. The charge-to-voltage conversion region 106 is used to convert the collected charges into a voltage.

The gate 110 of the amplifier transistor (SF) is connected to the charge-to-voltage conversion region 106 via a signal line 111. To transfer the voltage from the charge-to-voltage conversion region 106 to an output VOUT, an appropriate signal is applied to the gate of the row select transistor (RS) via contact 112. Activation of the row select transistor enables an amplifier transistor (SF) which in turn transfers the voltage from the charge-to-voltage converter (FD) to VOUT. A shallow trench isolation region (STI) surrounds the Photodetector (PD) and the pixel 100 to electrically isolate the pixel from neighboring pixels in the image sensor. An n-type isolation layer 114 surrounds these STI regions, as will be described in more detail in connection with fig. 2 and 3.

Fig. 2 illustrates a cross-sectional schematic view along line a-a in fig. 1, depicting a prior art pixel structure. The pixel 100 includes a Transfer Gate (TG), a charge-to-voltage conversion region 106, and a photodetector 102. Photodetector 102 is implemented as a pinned photodiode consisting of an n + pinning layer 200 and a p-type storage region 202 formed within an n-type layer 204. An n-type layer 204 is disposed over the substrate layer 206.

Shallow trench isolation regions (STI)208 are formed laterally adjacent to and surround the opposing sides of photodetector 102. STI 208 is also formed laterally adjacent to the charge-to-voltage conversion region 106, with a Transfer Gate (TG) positioned between the photodetector 102 and the charge-to-voltage conversion region 106. STI region 208 includes a trench formed in n-type layer 204 filled with dielectric material 210. An n-type isolation layer 114 surrounds the sidewalls and bottom of each trench. The isolation layer 114 is typically formed by implanting n-type dopants into the sidewalls and bottom of the trench prior to filling the trench with the dielectric material 210.

Fig. 3 depicts a cross-sectional schematic view along line B-B in fig. 1, depicting a prior art pixel structure. STI 208 is formed laterally adjacent to photodetector 102 and surrounds photodetector 102. STI 208 is also formed laterally adjacent to the charge-to-voltage conversion region 106. An n-type isolation layer 114 surrounds the sidewalls and bottom of the trench.

The shallow n + implant of the isolation layer 114 may increase the peripheral capacitance of the charge-to-voltage conversion region 106 and may result in higher dark current or point defects due to the p +/n + diode junction formed by the n-type isolation layer and the p-type charge-to-voltage conversion region 106. In addition, the n-type isolation layer 114 laterally adjacent to one or more transistors in the pixel 100, such as an amplifier transistor (SF), may reduce the effective width of the transistors. This can lead to narrow channel effects and requires the design of wider transistors which in turn reduce the fill factor of the pixel.

Disclosure of Invention

The image sensor includes a pixel array forming an imaging area. At least one pixel includes a photodetector and a charge-to-voltage conversion region disposed in a silicon semiconductor layer. The photodetector includes a storage region having a first conductivity type disposed in the silicon semiconductor layer having a second conductivity type. The charge-to-voltage conversion region has the first conductivity type and is electrically connectable to the storage region by a transfer gate positioned between the storage region and the charge-to-voltage conversion region.

Shallow trench isolation regions are formed laterally adjacent to or surrounding the photodetectors, the charge-to-voltage conversion region, and other features and components in each pixel. Each of the shallow trench isolation regions includes a trench disposed in the silicon semiconductor layer filled with a dielectric material. A shallow trench isolation region is laterally adjacent to and surrounds each photodetector. The isolation layer having the second conductivity is disposed only along a bottom portion of the trench proximate to the photodetector and only along a sidewall of the trench proximate to the photodetector. The isolation layer is not disposed along the remaining bottom portion and opposing sidewalls of the trench.

Another shallow trench isolation region is laterally adjacent to or surrounds other electrical components in each pixel. These other electrical components may include a charge-to-voltage conversion region and source/drain implant regions for one or more transistors. The isolation layers are not disposed along the bottom and sidewalls of the trenches adjacent to these other electrical components in the pixel.

Drawings

FIG. 1 depicts a top view of a pixel typically used in a CMOS image sensor according to the prior art;

FIG. 2 illustrates a cross-sectional view along line A-A in FIG. 1, depicting a prior art pixel structure;

FIG. 3 depicts a cross-sectional view along line B-B in FIG. 1 depicting a prior art pixel structure;

FIG. 4 is a simplified block diagram of an image capture device in an embodiment in accordance with the invention;

FIG. 5 is a simplified block diagram of an image sensor suitable for use as image sensor 406 in the embodiment according to the invention shown in FIG. 4;

FIG. 6 illustrates top views of two exemplary pixels that are each suitable for use as the pixel 502 in the embodiment according to the invention shown in FIG. 5;

FIG. 7 depicts a cross-sectional view along line C-C in FIG. 6;

FIG. 8 depicts a cross-sectional view along line D-D in FIG. 6;

FIG. 9 is a flow chart of a method for fabricating a portion of an imaging region in an image sensor in an embodiment in accordance with the invention;

10A-10D depict a method for producing the STI regions and isolation layers 714 shown in FIG. 7 in an embodiment in accordance with the invention;

figures 11A-11B illustrate a method for producing the STI regions and isolation layers 714 shown in figure 8 in an embodiment in accordance with the invention; and

fig. 12 is a cross-sectional view of an alternative pixel structure in an embodiment in accordance with the invention.

Detailed Description

Throughout the specification and claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meaning of "a" and "the" includes plural references, and the meaning of "in. The term "connected" means either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term "circuit" refers to a single component or a number of components (active or passive) connected together to provide a desired function. The term "signal" means at least one current, voltage, charge or data signal.

In addition, directional terminology, such as "in. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. The directional terms, when used in connection with layers of an image sensor wafer or corresponding image sensors, are intended to be broadly interpreted, and thus should not be interpreted to exclude the presence of one or more intervening layers or other intervening image sensor features or components. Thus, a given layer described herein as being formed on or over another layer may be separated from the latter layer by one or more additional layers.

Finally, the term "substrate layer" should be understood to refer to semiconductor-based materials including, but not limited to, silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers, or wells or other semiconductor structures formed on a semiconductor substrate.

Referring to the drawings, like numbers indicate like parts throughout the views.

FIG. 4 is a simplified block diagram of an image capture device in an embodiment in accordance with the invention. The image capture device 400 is implemented as a digital camera in fig. 4. Those skilled in the art will recognize that a digital camera is only one example of an image capture device that may be utilized and have the image sensor of the present invention. Other types of image capture devices, such as cell phone cameras and digital video camcorders, may be used with the present invention.

In the digital camera 400, light 402 from a subject scene is input to an imaging stage 404. Imaging stage 404 may include conventional components such as lenses, neutral density filters, apertures, and shutters. Light 402 is focused by imaging stage 404 to form an image on image sensor 406. The image sensor 406 captures one or more images by converting incident light into electrical signals. The digital camera 400 further includes a processor 408, a memory 410, a display 412, and one or more additional input/output (I/O) components 414. Although shown as separate components in the embodiment of fig. 4, the imaging stage 404 may be integrated with the image sensor 406, and possibly with one or more additional components of the digital camera 400, to form a compact camera module.

Processor 408 may be implemented, for example, as a microprocessor, Central Processing Unit (CPU), Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), or other processing device, or a combination of multiple such devices. The various components of the imaging stage 404 and the image sensor 406 may be controlled by timing signals or other signals supplied from the processor 408.

Memory 410 may be configured in any combination as any type of memory, such as Random Access Memory (RAM), Read Only Memory (ROM), flash memory, disk-based memory, removable memory, or other type of storage component. A given image captured by the image sensor 406 may be stored by the processor 408 in the memory 410 and presented on the display 412. The display 412 is typically an active matrix color Liquid Crystal Display (LCD), although other types of displays may be used. Additional I/O components 414 may include, for example, various on-screen controls, buttons or other user interfaces, network interfaces, or memory card interfaces.

It will be appreciated that the digital camera shown in fig. 4 may include additional or alternative components of the type known to those skilled in the art. Components not specifically shown or described herein may be selected from components well known in the art. As indicated previously, the present invention may be implemented in a variety of image capture devices. Still further, certain aspects of the embodiments described herein may be implemented, at least in part, in software executed by one or more processing components of an image capture device. As will be appreciated by those skilled in the art, such software may be embodied in a straightforward manner given the teachings provided herein.

Referring now to FIG. 5, there is shown a simplified block diagram of an image sensor suitable for use as the image sensor 406 in the embodiment according to the invention shown in FIG. 4. Image sensor 500 generally includes an array of pixels 502 forming an imaging region 504. Image sensor 500 further includes a column decoder 506, a row decoder 508, digital logic 510, and analog or digital output circuitry 512. In an embodiment in accordance with the invention, image sensor 500 is implemented as a back-illuminated or front-illuminated Complementary Metal Oxide Semiconductor (CMOS) image sensor. Thus, column decoder 506, row decoder 508, digital logic 510, and analog or digital output circuit 512 are implemented as standard CMOS electronic circuits electrically connected to imaging region 504.

The functionality associated with the sampling and readout of the imaging area 504 and the processing of the corresponding image data may be implemented at least in part in the form of software stored in the memory 410 and executed by the processor 408 (see fig. 4). Portions of the sampling and reading circuitry may be disposed external to the image sensor 406 or integrally formed with the imaging region 504, e.g., on a common integrated circuit with the photodetector and other components of the imaging region. Those skilled in the art will recognize that other peripheral circuit configurations or architectures may be implemented in other embodiments in accordance with the invention.

FIG. 6 illustrates top views of two exemplary adjacent pixels suitable for use as the pixel 502 in the embodiment according to the invention shown in FIG. 5. Pixels 600 each include a Photodetector (PD)102 as shown in fig. 1, a transfer transistor having a Transfer Gate (TG) and a contact 108, a charge-to-voltage conversion region (FD)106, a reset transistor having a Reset Gate (RG)104, an amplifier transistor (SF) having a gate 110, a row select transistor having a gate and a contact 112, VDD, and VOUT. The signal line 111 connecting the charge-to-voltage conversion region 106 to the gate 110 of the amplifier transistor (SF) is omitted in fig. 6 for simplicity. In an embodiment in accordance with the invention, the amplifier transistor (SF) is implemented as a source follower transistor and the charge-to-voltage conversion region is implemented as a floating diffusion region.

Transfer transistors, charge-to-voltage conversion regions 106, reset transistors, row select transistors, amplifier transistors, VDD and VOUT are examples of electrical components that may be included in pixel 600. One or more of these illustrated electrical components may be omitted according to other embodiments of the invention. Alternatively, the pixels may include fewer, additional, or different types of electrical components.

The charge collection and readout from the pixel 600 is the same as that described with reference to fig. 1. A shallow trench isolation region (STI) surrounds the photodetector 102 and other electrical components as in the prior art, but the n-type isolation layer 602 surrounds only the portion of the STI region immediately adjacent to the photodetector 102, as will be described in more detail in connection with fig. 7 and 8.

Fig. 7 depicts a cross-sectional view along line C-C in fig. 6. In an embodiment in accordance with the invention, the pixel 600 includes a storage region 700 and a pinning layer 702 that together form the photodetector 102. In the illustrated embodiment, the storage region 700 is doped with one or more dopants having a p conductivity type, while the pinning layer 702 is doped with one or more dopants having an n conductivity type.

The pixel 600 further includes a charge-to-voltage conversion region 106. A Transfer Gate (TG)704 is disposed between the photodetector 102 and the charge-to-voltage conversion region 106. When an appropriate signal is applied to the contact 108, the charge collected in the storage region 700 is transferred to the charge-to-voltage conversion region 106.

The photodetector 102 and the charge-to-voltage conversion region 106 are disposed in the silicon semiconductor layer 706. The silicon semiconductor layer 706 has an n conductivity type and may be implemented as a layer across an imaging region (e.g., imaging region 504) or as a well. The voltage supply VDD is connected to the silicon semiconductor layer 706.

A silicon semiconductor layer 706 is disposed over the substrate layer 708. In the fig. 7 embodiment, the substrate layer 708 is implemented as an epitaxial layer 710 disposed over a substrate 712. In an embodiment in accordance with the invention, both the epitaxial layer 710 and the substrate 712 have a p conductivity type. In another embodiment according to the present invention, the substrate 712 may be implemented as a bulk substrate having an n conductivity type.

Shallow trench isolation regions (STI)714 are disposed in silicon semiconductor layer 706. Each STI region includes a trench 716, 718 filled with a dielectric material 720. The isolation layer 602 having the n conductivity type only partially surrounds the STI region 714 that is immediately adjacent to the photodetector 102 and surrounds the photodetector 102. The isolation layer 602 is disposed along a portion of the bottom trench 716 and along only one side of the trench 716. In particular, the isolation layer 602 is disposed along portions and sides of the trench 716 that are immediately adjacent to the bottom of the storage region 700 and the pinning layer 702.

Forming the isolation layer 602 along only a portion of the bottom of the trench 716 and along the sidewalls of the trench 716 that are immediately adjacent to the photodetector 102 suppresses dark current adjacent to the STI sidewalls or interface of the photodetector. In addition, isolation layer 602 is not disposed along the remaining bottom portion and another sidewall of trench 716, and not along the sidewall and bottom of trench 718 immediately adjacent to the STI region of charge-to-voltage conversion region 106. Because there is no isolation layer 602 in these areas, the capacitance of the charge-to-voltage conversion region 106 and the characteristics of other transistors (e.g., reset transistor, source follower transistor, row select transistor) in the pixel 600 are not adversely affected by the isolation layer 602. Another advantage of removing n + isolation layer 602 from the sidewalls and bottom of trench 718 is an increase in the effective width of the Field Effect Transistor (FET). The FET width can be physically pulled up to be smaller, which allows the width of the photodetector 102 to be pulled up to be larger, thereby increasing the pixel fill factor.

Referring now to FIG. 8, a cross-sectional view along line D-D in FIG. 6 is shown. Shallow trench isolation regions 714 are disposed in silicon semiconductor layer 706. The STI region 714 adjacent to the photodetector 102 and surrounding the photodetector 102 includes an isolation layer 602 having an n conductivity type. The isolation layer 602 only partially surrounds the STI region 714 that is immediately adjacent to the photodetector 102. The isolation layer 602 is disposed along portions and sides of the trench 716 that are immediately adjacent to the bottom of the storage region 700 and the pinning layer 702.

The isolation layer 602 is not disposed along the portion of the trench 716 that is not immediately adjacent to the bottom of the photodetector 102 and the other sidewall. Isolation layer 602 is also not disposed along the sidewalls and bottom of trench 718.

Fig. 9 is a flow chart of a method for manufacturing a portion of an imaging region in an image sensor in an embodiment in accordance with the invention. Initially, a silicon semiconductor layer 706 is formed in a substrate layer 708 (block 900). When the substrate layer comprises an epitaxial layer disposed over the substrate, a silicon semiconductor layer 706 is formed in the epitaxial layer (e.g., epitaxial layer 710).

Next, as shown in block 902, STI regions 714 and isolation layers 602 are formed in silicon semiconductor layer 706. The process for creating STI regions 714 and isolation layer 602 will be described in more detail in conjunction with fig. 10 and 11.

The gates of the transistors in the pixel are then formed as shown in block 904. These gates may include a Transfer Gate (TG), a Reset Gate (RG), a gate of an amplifier transistor, and a gate of a row select transistor in an embodiment in accordance with the invention.

Next, as shown in block 906, an implant region is formed. In an embodiment according to the present invention, the implanted regions include the storage region 700, the charge-to-voltage conversion region 106, other source/drain regions, and the pinning layer 702.

Those skilled in the art will recognize that other features and components of the pixels or imaging regions are generated prior to, concurrently with, or subsequent to the process illustrated in fig. 9. Further, features and components outside of the imaging area (e.g., area 504 in fig. 5) may be fabricated prior to, concurrently with, or after the process illustrated in fig. 9.

Fig. 10A-10D depict a method for producing the STI regions and isolation layers 714 shown in fig. 7 in an embodiment in accordance with the invention. The processes shown in fig. 10A-10D are not intended to illustrate all of the fabrication techniques for an image sensor or pixel. One skilled in the art will recognize that other processes may be implemented between the techniques shown in fig. 10A-10D.

Figure 10A illustrates the pixel after n-type silicon semiconductor layer 706 is formed in p-type epitaxial layer 710 and after trenches 716, 718 are formed in layer 706. The n-type silicon semiconductor layer 706 is produced by implanting dopants having an n-conductivity type into the epitaxial layer 710. Trenches 716, 718 are formed by etching n-type layer 706 using techniques known in the art.

Block 1000 represents the area in the silicon semiconductor layer 706 where the photodetectors will be subsequently formed. Block 1002 represents a region in the silicon semiconductor layer 706 where a charge-to-voltage conversion region will subsequently be formed. As shown in fig. 9, the photodetector and other implanted regions (such as the charge-to-voltage conversion region and the source/drain implanted regions) are typically formed after the STI regions and gates have been formed.

A mask layer 1004 is then formed over the pixel 600 and patterned to create an opening 1006 (fig. 10B). Opening 1006 exposes trench 716 and a portion of n-type silicon semiconductor layer 706. The portion of the bottom of trench 716 exposed in opening 1102 and the sidewalls of trench 716 are the portion of trench 716 immediately adjacent to the PD to be formed (represented by block 1000). As indicated by the arrows, n-type dopants are implanted into the opening 1006. The n-type dopant generally has a high dopant concentration. The implanted dopant forms an n-type isolation layer 602 along a portion of the bottom of trench 716 and the sidewalls of trench 716 immediately adjacent to block 1000.

Masking layer 1004 is then removed and a dielectric material 1008 is formed over the surface of n-type silicon semiconductor layer 706 to fill trenches 716, 718. The dielectric material 1008 is removed from the surface of the n-type layer 706 until the dielectric material 1008 fills only the trenches 716, 718. Such processes are illustrated in fig. 10C.

A mask layer 1010 is then formed over the pixel 600 and patterned to create an opening 1012 (fig. 10D). N-type dopants are implanted into the opening 1012 as indicated by the arrows. The n-type dopant typically has a lower dopant concentration than the dopant implanted in fig. 10B. The implanted dopants passivate the interface between the sidewall surfaces and the n-type silicon semiconductor layer 706 and the n-type isolation layer 602. The process depicted in FIG. 10D is optional and is not performed in other embodiments according to the invention.

Referring now to fig. 11A-11B, a method for producing the STI region 714 and isolation layer 602 shown in fig. 8 in an embodiment in accordance with the invention is shown. Fig. 11A depicts the pixel after n-type silicon semiconductor layer 706 is formed in p-type epitaxial layer 710 and after trenches 716, 718 are formed in layer 706. A mask layer 1100 is then formed over the pixel 600 and patterned to create an opening 1102 (fig. 11B). Opening 1102 exposes trench 716 and a portion of n-type silicon semiconductor layer 706. The portion of the bottom of trench 716 exposed in opening 1102 and the sidewalls of trench 716 are the portion of trench 716 immediately adjacent to the PD to be formed (represented by block 1000). No openings are formed for trenches 718, and trenches 718 remain covered by mask layer 1100.

N-type dopants are then implanted into the silicon semiconductor layer 706 through the opening 1102 as indicated by the arrows. The n-type dopant generally has a high dopant concentration. The implanted dopant forms n-type isolation layer 602 along only a portion of the bottom of trench 716 and one sidewall of trench 716. An isolation layer 602 is formed in the silicon semiconductor layer 706 immediately adjacent to the area where the photodetector will be formed.

Dopants are not implanted into other portions of trench 716 and into the sidewalls and bottom of trench 718 because other portions of trench 716 and trench 718 are covered by mask layer 1100. Thus, n-type isolation layers are not formed along other portions of the bottom of trench 716, along sidewalls of trench 716 that are not immediately adjacent to the region where the photodetector will be formed, and along sidewalls and bottom of trench 718.

As previously described, the dopant forming the isolation layer 602 is typically implanted into the trench prior to disposing the dielectric layer in the trench. In general, the isolation layer implantation is performed only in the imaging region (e.g., imaging region 504 in fig. 5) of the image sensor. The implant in the imaging region is an unpatterned or unmasked implant, which means that all STI regions in the imaging region receive an isolation layer implant. The patterned mask layer is used to cover only the area outside the imaging area during isolation layer implantation. Thus, the present invention does not increase manufacturing costs by using a mask layer (layer 1004 in FIG. 10B; layer 1100 in FIG. 11) in the imaging region, since the mask layer can be the same mask layer used to cover regions outside the imaging region.

Fig. 12 is a cross-sectional view of an alternative pixel structure in an embodiment in accordance with the invention. The pixel structure shown in fig. 12 is the same as that depicted in fig. 8, except that a well 1200 is used instead of an STI region. In the illustrated embodiment, the well 1200 is doped with one or more dopants having an n-conductivity type. Well 1200 is disposed in silicon semiconductor layer 706 laterally adjacent to charge-to-voltage conversion region 106 (on the side opposite STI region 714). The well 1200 is used to isolate the charge-to-voltage conversion region 106 from other charge-to-voltage conversion regions and components in neighboring pixels. As with the fig. 8 embodiment, n + isolation layer 602 is not present around well 1200 and the portion of trench 716 immediately adjacent to charge-to-voltage conversion region 106.

The invention has been described in detail with particular reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. For example, the pixel 600 has been characterized with reference to a particular conductivity type. In other embodiments according to the invention, the opposite conductivity type may be used. Additionally, some of the features illustrated in the pixel 600 may be omitted or shared in other embodiments in accordance with the invention. For example, the pinning layer 702 need not be included in the pixel. In other embodiments according to the invention, the amplifier transistor (SF) or charge-to-voltage conversion region 106 may be shared by two or more pixels.

Moreover, while specific embodiments of the invention have been described herein, it should be noted that the application is not limited to such embodiments. In particular, any feature described in relation to one embodiment may also be used in other embodiments (if compatible). Also, the features of the different embodiments may be interchanged (if compatible).

Parts list

100 pixels

102 photo detector

104 contact

106 charge to voltage conversion region

108 contact

110 gate of source follower transistor

111 signal line

112 contact

114 barrier layer

200 pinning layer

202 storage area

204 layers

206 substrate layer

208 shallow trench isolation

210 dielectric material

400 image capturing apparatus

402 light

404 imaging stage

406 image sensor

408 processor

410 memory

412 display

414 other input/output (I/O)

500 image sensor

502 pixel

504 imaging region

506 column decoder

508 row decoder

510 digital logic

512 analog or digital output circuit

600 pixel

602 isolation layer

700 storage area

702 pinning layer

704 transfer gate

706 silicon semiconductor layer

708 substrate layer

710 epitaxial layer

712 base plate

714 shallow trench isolation

716 trench

718 trench

720 dielectric material

1000 area where the photodetector will be formed

1002 area to form a charge-to-voltage conversion region

1004 mask layer

1006 opening

1008 dielectric material

1010 mask layer

1012 opening

1100 mask layer

1102 opening

1200 well

RG reset gate

RS row select transistor

SF amplifier transistor

STI shallow trench isolation

TG transfer gate

VDD Voltage supply

VOUT output terminal

Claims (10)

1. A method for forming a shallow trench isolation region in close proximity to a photodetector in a layer of a first conductivity type, wherein the photodetector comprises a storage region of a second conductivity type disposed in the layer of the first conductivity type, the method comprising:

forming a trench in the layer of the first conductivity type;

implanting dopants of the first conductivity type into the layer of the first conductivity type only partially along a bottom of the trench and only along a sidewall of the trench immediately adjacent to where the storage region of the photodetector will be subsequently formed; and

the trench is filled with a dielectric material.

2. The method of claim 1, further comprising implanting dopants of the first conductivity type along the bottom and sidewalls of the trench after filling the trench with the dielectric material.

3. The method of claim 2, in which implanting dopants of the first conductivity type into the layer of the first conductivity type only partially along a bottom of the trench and only along a sidewall of the trench comprises: implanting dopants of the first conductivity type into the layer of the first conductivity type at a first dopant concentration only partially along a bottom of the trench and only along a sidewall of the trench immediately adjacent to where the storage region of the photodetector will be subsequently formed.

4. The method of claim 3, in which implanting dopants of the first conductivity type along the bottom and sidewalls of the trench after filling the trench with the dielectric material comprises: after filling the trench with the dielectric material, implanting dopants of the first conductivity type along the bottom and sidewalls of the trench with a second dopant concentration, wherein the first dopant concentration is higher than the second dopant concentration.

5. The method of claim 1, further comprising:

after forming the trench and before implanting the dopant having the first conductivity type into the layer having the first conductivity type, forming a mask layer over the layer having the first conductivity type, and patterning the mask layer to create an opening in the mask layer that exposes only a portion of the bottom of the trench and only a sidewall of the trench immediately adjacent to where the storage region of the photodetector will be formed; and

after implanting the dopant having the first conductivity type into the layer having the first conductivity type, the mask layer is removed prior to filling the trench with a dielectric material.

6. A method for forming a shallow trench isolation region in a layer of a first conductivity type immediately adjacent to where a photodetector and a charge-to-voltage conversion region are to be formed in the layer of the first conductivity type, wherein the photodetector comprises a storage region of a second conductivity type and the charge-to-voltage conversion region is of the second conductivity type, the method comprising:

forming a first trench in the layer of the first conductivity type proximate where the photodetector is to be formed;

forming a second trench in the layer of the first conductivity type immediately adjacent where the charge-to-voltage conversion region is to be formed;

implanting dopants of the first conductivity type into the layer of the first conductivity type only partially along a bottom of the first trench and only along a sidewall of the first trench immediately adjacent to where the storage region of the photodetector is to be formed, without implanting the dopants of the first conductivity type into the first layer of the first conductivity type along a bottom and sidewall of the second trench; and

filling the first trench and the second trench with a dielectric material.

7. The method of claim 6, further comprising implanting dopants of the first conductivity type along the bottom and sidewalls of the first and second trenches after filling the first and second trenches with the dielectric material.

8. The method of claim 7, in which implanting dopants of the first conductivity type into the layer of the first conductivity type only partially along a bottom of the first trench and only along a sidewall of the first trench comprises: implanting dopants of the first conductivity type into the layer of the first conductivity type at a first dopant concentration only partially along a bottom of the first trench and only along a sidewall of the first trench immediately adjacent to a region where the photodetector will be subsequently formed.

9. The method of claim 8, in which implanting dopants of the first conductivity type along the bottom and sidewalls of the first trench and the second trench after filling the first trench and the second trench with dielectric material comprises: implanting dopants of the first conductivity type at a second dopant concentration along the bottom and sidewalls of the first and second trenches after filling the first and second trenches with the dielectric material, wherein the first dopant concentration is higher than the second dopant concentration.

10. The method of claim 6, further comprising:

after forming the first and second trenches and before implanting the dopant of the first conductivity type into the layer of the first conductivity type, forming a mask layer over the layer of the first conductivity type and patterning the mask layer to create an opening in the mask layer that exposes only a portion of the bottom of the first trench and exposes only a sidewall of the first trench that is immediately adjacent to a region where the photodetector will be subsequently formed; and

after implanting the dopant having the first conductivity type into the layer having the first conductivity type, the mask layer is removed prior to filling the first trench and the second trench with the dielectric material.