HK1178695B - Low common mode driver - Google Patents

Abstract

Techniques to provide a replica bias circuit for a high speed and low voltage common mode driver. In an embodiment, a pre-driver is coupled to provide driver input voltages to the driver, which driver includes a set of circuit elements coupled to provide, based on the driver input voltages, an output signal of a differential output. In another embodiment, a regulator circuit is coupled to provide regulated power to the pre-driver and driver, where the regulator circuit includes a scale replica circuit having a replica of the first set of circuit elements.

Description

Low common mode driver

Technical Field

The present disclosure relates generally to drivers and more particularly, but not exclusively, to low voltage differential signaling devices.

Background

Various high-speed differential serial link standards have been designed to accommodate increased off-chip data rate communications. High speed Universal Serial Bus (USB), firewire (IEEE-1394), serial Advanced Technology Attachment (ATA), and Small Computer System Interface (SCSI) are several standards for serial data transfer in the PC industry. Low Voltage Differential Signaling (LVDS) has also been implemented in transmission-side serial data communications.

Additionally, vendors (e.g., cellular telephone companies) have proposed a "sublvds" standard, which is a small voltage swing variation of the LVDS standard. It has been proposed to use sublvds in the compact camera port 2(CCP2) specification for serial communication between, for example, an image sensor and an onboard system.

CCP2 is part of the Standard Mobile Imaging Architecture (SMIA) standard. Typical LVDS/sublvds levels have an output common mode level (Vcm) between the supply voltages VDD and VSS. For example, a transmitter (Tx) for CCP2 typically has an output signal swing (Vod) of 150mV, with a center voltage Vcm at 0.9V.

In addition to high-speed image data, low-speed chip control signals are also typically transmitted between the host and the client. Several new protocols have been developed for high speed ("HS") to low power ("LP") state changes using common mode levels. The concerted effort among various cellular telephone companies has defined new physical layer (PHY) standards. The PHY standard defines a Mobile Industry Processor Interface (MIPI) that combines high-speed image data transmission with low-speed control signals in a single communication signal path ("lane").

Fig. 1 is a block diagram showing a conventional LVDS interface 100. The LVDS interface 100 includes a differential current switch pair 101 with a driver (or "output") stage of a current source 102. The tail current from the differential current switch pair 101 is adjusted to control the output voltage swing. The common mode level Vcm is sensed by tapping the midpoint of the back termination resistor 103. The Vcm is tracked and adjusted in real time using a common mode feedback filter 104.

For high speed transmission, some degree of impedance matching has been used for longer transmission lines. Conventional LVDS interfaces typically include a 100 Ω -200 Ω back termination resistor 103 on the chip between the differential output pads Dp and Dn, for example, to improve the differential reflection coefficient below-10 dB at the frequencies of general interest. However, in such a design, real-time Vcm tracking is not practical due to the long shared mode settling time required during mode changes from LP to HS mode (e.g., from a logic high voltage of 1.2V in LP mode to a logic high voltage of 100mV in HS mode). Also, power penalties may be generated by the back termination resistor 103, which may result in the need for an additional 50% to 100% of the output driver current. Thus, low common mode transmission designs exhibit limited responsiveness to LVDS settling time and/or limited efficiency of silicon space or power consumption.

Disclosure of Invention

One embodiment of the invention relates to a transmitter. The transmitter includes: a pre-driver coupled to receive a data signal and to output a driver input voltage based on the data signal; a driver coupled to the pre-driver, the driver including a first set of circuit elements coupled in series with each other, wherein the first set of circuit elements are coupled to provide a differentially output first output signal based on the driver input voltage; and a first regulator circuit coupled to provide regulated power to the driver, the first regulator circuit including: a first transistor coupled between the driver and a supply voltage rail; a proportional replica circuit having a replica of the first set of circuit elements; and an error amplifier, wherein the proportional replica circuit and the first transistor are both coupled to an output of the error amplifier, wherein the proportional replica circuit is coupled to provide a feedback voltage to the error amplifier, wherein the error amplifier is coupled to amplify a difference between the feedback voltage and a reference voltage.

Another embodiment of the present invention relates to an image forming apparatus. The image forming apparatus includes: an array of pixels; readout circuitry to generate image data based on signals from the pixel array; and a transmitter coupled to the readout circuitry to transmit the image data, the transmitter comprising: a pre-driver coupled to receive a data signal and to output a driver input voltage based on the data signal; a driver coupled to the pre-driver, the driver including a first set of circuit elements coupled in series with each other, wherein the first set of circuit elements are coupled to provide a differentially output first output signal based on the driver input voltage; and a first regulator circuit coupled to provide regulated power to the driver, the first regulator circuit including: a first transistor coupled between the driver and a supply voltage rail; a proportional replica circuit having a replica of the first set of circuit elements; and an error amplifier, wherein the proportional replica circuit and the first transistor are both coupled to an output of the error amplifier, wherein the proportional replica circuit is coupled to provide a feedback voltage to the error amplifier, wherein the error amplifier is coupled to amplify a difference between the feedback voltage and a reference voltage.

Another embodiment of the invention relates to a transmitter. The transmitter includes: a pre-driver coupled to receive a data signal and to provide a driver input voltage based on the data signal; a driver coupled to the pre-driver, the driver including a first set of circuit elements coupled in series with each other, wherein the first set of circuit elements are coupled to provide a differentially output first output signal based on the driver input voltage; a first regulator circuit coupled to provide regulated power to the predriver, the first regulator circuit including: a first transistor, wherein the predriver is coupled to a supply voltage via the first transistor; a proportional replica circuit having a replica of the first set of circuit elements; an error amplifier; and a first amplifier, wherein an output of the error amplifier and an output of the first amplifier are both connected to the first transistor, wherein the proportional replica circuit is coupled to provide a feedback voltage to the error amplifier, wherein the error amplifier is used to amplify a difference between the feedback voltage and a reference voltage, and wherein the proportional replica circuit is further coupled to a feedback loop extending from the transistor back to the first amplifier.

Drawings

Various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

fig. 1 is a block diagram of a conventional LVDS driver.

FIG. 2 is a block diagram illustrating select elements of a device for communicating data, according to an embodiment.

Fig. 3 is a block diagram of a conventional MIPI transmitter.

FIG. 4 is a block diagram illustrating select elements of a high speed differential transmitter having regulated driver stages according to an embodiment.

FIG. 5 is a block diagram illustrating select elements of a high speed differential transmitter having a predriver regulator and an output stage open-circuit regulator, according to an embodiment.

FIG. 6 is a block diagram illustrating select elements of a high speed differential transmitter with predriver regulators according to an embodiment.

Detailed Description

The embodiments discussed herein variously provide replica bias circuits by which the transmitter's low common mode driver can perform high speed signaling and low power signaling. For example, one embodiment provides a transmitter including power conditioning circuitry for causing the transmitter to operate differently in at least two transmission modes, e.g., where one transmission mode is a relatively lower power and lower speed mode compared to another transmission mode being a relatively higher power and higher speed transmission mode.

In an embodiment, a transmitter includes a predriver coupled to receive one or more data signals and provide a driver input voltage based on the one or more data signals. The transmitter may further include a driver (also referred to as an output stage) coupled to the predriver, for example, where the driver is coupled to provide a differential output based on a driver input voltage generated by the predriver. For example, the driver may include a set of circuit elements coupled to provide an output signal of a differential output. The set of circuit elements may be coupled in series with one another, such as between supply voltages VDD and VSS (e.g., ground). For example, the set of circuit elements may include circuit elements of a pull-up (pu1l-up) path for pulling an output signal up to a logic high voltage level. Alternatively or additionally, the set of circuit elements may include circuit elements of a pull-down path for pulling the output signal down to a logic low voltage level.

In certain embodiments, the transmitter may include one or more regulator circuits to provide regulated power to either or both of a predriver and a driver of the transmitter. For example, the regulator circuit may include a proportional replica circuit that includes a replica of the set of circuit elements (that will provide the output signal) of the driver. The proportional replica circuit can be coupled to provide a feedback voltage for power supply regulation.

In one embodiment, the regulator circuit includes a transistor through which the regulator circuit provides regulated power to the driver. The regulator may further include an error amplifier to provide an output that, for example, directly or indirectly controls the operation of the transistor. The error amplifier may amplify the difference between the reference voltage and the voltage feedback provided by the proportional replica circuit. In one embodiment, the transistor and the proportional replica circuit share a connection to the output of the error amplifier.

In another embodiment, the regulator circuit will provide regulated power to the predriver, e.g., where the predriver is coupled to the supply voltage through a transistor of the regulator circuit. The regulator circuit may include a first amplifier and an error amplifier, e.g., where an output of the error amplifier and an output of the first amplifier are both connected to the transistor. A proportional replica circuit of the regulator circuit can be coupled to provide a feedback voltage to the error amplifier, e.g., where the error amplifier is to amplify a difference between the feedback voltage and a reference voltage. Furthermore, the proportional replica circuit may be further coupled to a feedback loop extending from the transistor back to the first amplifier.

FIG. 2 is a block diagram illustrating select elements of a device 200 for communicating data using a low common mode driver, according to an embodiment. Device 200 may include a PHY interface 218 (e.g., an interface of image sensor circuitry 210 of device 200) to operate differently in two different transmission modes to provide an output 220. One such transmission mode may be a relatively lower power and lower speed mode compared to another transmission mode being a relatively higher power and higher speed transmission mode.

For example, device 200 may comprise any of a variety of devices having image sensing capabilities. By way of illustration and not limitation, device 200 may comprise a desktop computer, laptop computer, tablet computer or other handheld computer, mobile phone, dedicated digital camera (e.g., camera and/or video camera), and so forth.

Although shown in the context of the illustrative device 200, it should be understood that the various embodiments may be implemented entirely within an interface having the characteristics of the PHY interface 218. Accordingly, it should also be appreciated that certain features of the apparatus 200 that are external to the PHY interface 218 may not be limited to certain embodiments. For example, the operation of PHY interface 218 may be extended to apply to interfaces that additionally or alternatively communicate information other than image data. Further, such an interface may (additionally or alternatively) provide an interface for circuitry that relays (rather than generates) image data.

Image sensor circuitry 210 may include a pixel array 212, readout circuitry 214, and control circuitry 216. Some or all of image sensor circuitry 210 may reside on an Integrated Circuit (IC) chip that communicates with one or more off-chip components via PHY interface 218. In an embodiment, pixel array 212 is a two-dimensional ("2D") array of backside illuminated imaging sensors or pixels (e.g., pixels P1, P2.. Pn). In one embodiment, each pixel is a complementary metal-oxide-semiconductor ("CMOS") imaging pixel. As illustrated, each pixel is arranged into rows (e.g., rows R1-Ry) and columns (e.g., columns C1-Cx) to acquire image data of a person, place, or object, which can then be used to render a 2D image of the person, place, or object.

The pixel array 212 may be exposed to an image (e.g., via the lens 205 of the device 200). After the pixels of pixel array 212 have acquired their image data or image charge, the image data is read out by readout circuitry 214 and transferred directly or indirectly to functional logic 230 (e.g., a process running on a processor coupled directly or indirectly to PHY interface 218). The readout circuitry 214 may include amplification circuitry, analog-to-digital ("ADC") conversion circuitry, parallel-to-serial conversion circuitry, and/or other circuitry. Function logic 230 may simply store the image data to memory (not shown) or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red-eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 214 may readout one column of image data at a time along readout column lines (illustrated), or may readout the image data using various other techniques (not illustrated), such as a serial readout or a full parallel readout of all pixels simultaneously.

Control circuitry 216 is coupled to pixel array 212 to control operating characteristics of pixel array 212. For example, the control circuitry 216 may generate a shutter signal for controlling image acquisition. In one embodiment, the shutter signal is a global shutter signal that is used to simultaneously enable all pixels within the pixel array 212 to simultaneously capture their respective image data during a single acquisition window. In an alternative embodiment, the shutter signal is a rolling shutter signal, whereby each row, column, or group of pixels is sequentially enabled during successive acquisition windows.

Fig. 3 is a block diagram of a conventional MIPI transmitter system 300. MIPI system 300 includes a serializer 320, a high-speed transmission ("HS-TX") transmitter 340, and a low-power transmission ("LP-TX") transmitter 350. The serializer 320 (also referred to as a multiplexer or "MUX") converts parallel data (e.g., received on multiple parallel channels 310) into a single data channel 330 having a higher transmission rate. For example, the readout circuit 214 may include circuitry to implement the functionality of the serializer 320.

As shown in fig. 3, HS and LP transmissions may share the same physical channel to reduce the number of package pins and the cost of padding. For example, the differential output 360 of the MIPI transmitter system 300 includes respective output signals provided on output pads Dp 365a and Dn365 b. Transmitter functions (e.g., "channel states") can be programmed by driving the channel at certain line levels. For example, HS-TX transmitter 340 of MIPI transmitter system 300 differentially drives the channel with a low common mode voltage level of 200mV and a differential swing of 200 mV. In contrast, LP-TX transmitter 350 of MIPI transmitter system 300 may output a signal toggled between 0V and 1.2V at other times.

The HS-TX transmitter 340 and the LP-TX transmitter 350 of the conventional MIPI system 300 are separate functional elements. However, as exemplified herein, a single bank of circuitry may exhibit the respective transmission characteristics of both the HS-TX transmitter 340 and the LP-TX transmitter 350 in various ways, according to some embodiments.

Existing common mode driver designs include the use of current mode logic ("CML") drivers and the use of large capacitive or resistive loads. However, such types of drivers occupy silicon space on a semiconductor chip and consume a large amount of power. Various embodiments provide techniques for limiting such power costs.

In an embodiment, a transmitter includes a predriver coupled to receive one or more data signals and provide a driver input voltage based on the one or more data signals. The transmitter may further include a driver coupled to provide a differential output based on the driver input voltage. The driver may include a set of circuit elements to provide an output signal of the differential output.

In certain embodiments, the transmitter includes one or more regulator circuits coupled to provide regulated power to a driver of the transmitter. For example, the regulator circuit may include a proportional replica circuit that includes a replica of the set of circuit elements of the driver. The proportional replica circuit can be coupled to provide a feedback voltage for power supply regulation.

In one embodiment, the regulator circuit includes a transistor through which the driver is powered, and an error amplifier (e.g., where the output of the error amplifier controls the operation of the transistor). For example, the error amplifier may amplify the difference between a reference voltage and a feedback voltage provided by the proportional replica circuit. In one embodiment, the proportional replica circuit and the transistor share a connection to the output of the error amplifier.

By way of illustration and not limitation, FIG. 4 shows select elements of a high speed differential transmitter 400 having regulated driver stages according to an embodiment. The high speed differential transmitter 400 may include a driver stage 410, a predriver 420, and a regulator circuit 440. The driver stage 410 may be an NMOS-on-NMOS (or "N-on-N") structure and may include a pull-up path and a pull-down path. By way of illustration and not limitation, the first pull-up path may include transistor 411 and resistor 415, and the second pull-up path may include transistor 412 and resistor 416. Similarly, the first pull-down path may include transistor 413 and resistor 417, and the second pull-down path may include transistor 414 and resistor 418. For example, the first set of circuit elements of transmitter 400 may include some or all of the elements in the circuit branch including transistors 412, 414 and resistors 416, 418. Alternatively, the first set of circuit elements may include some or all of the elements in a circuit branch that includes transistors 411, 413 and resistors 415, 417. In other words, the elements from either of the two circuit branches may be considered to be their scaled copies of the first set of circuit elements included in the replica circuit element 470. In an embodiment, the elements from the other of the two circuit branches may be considered to have their scaled copies included in the second set of circuit elements in the replica circuit elements 470.

The regulator circuit 440 may include a replica circuit 470 as part of the means for regulating power to the driver 410. Replica circuit 470 can include a replica of the first set of circuit elements (e.g., transistors 472, 473 and resistors 474, 475). As referred to herein, copies of a set of circuit elements have at least the same configuration relative to each other as that of some set of reference circuit elements. Further, one or more characteristics (e.g., resistance, capacitance, inductance, and/or the like) of the replicated circuit elements may be in some proportion to one another according to a corresponding proportion of such characteristics in the set of reference circuit elements.

The output impedance of the pull-up path may be controlled by the replica bias in the regulator circuit 440 via a voltage control signal VCTRL generated by the replica circuit 470. For example, a feedback loop, such as that of error amplifier 442 including some portion of replica circuit 470 and coupled to capacitor 445, may help control the output impedance of the pull-up path. In an embodiment, the voltage feedback VFB may be provided from a circuit node of the replica circuit 470 that corresponds to the circuit node from which the output signal is to be provided. For example, voltage feedback VFB may be provided from a node between resistors 474, 475 that corresponds to one or either of the node between resistors 415, 417 and the node between resistors 416, 418.

However, the output impedance of the pull-down resistors 413 and 414 may not be controlled by the output regulator 440, but may vary with changes in process, voltage, and/or temperature (PVT). To reduce variation of the output impedance of the pull-down path over changes in PVT, resistor 417 may be coupled between differential output signal OUTN and pull-down transistor 413, and resistor 418 is coupled between differential output signal OUTP and pull-down transistor 414. The change in PVT has less effect on the resistor than it has on the NMOS transistor. For example, the output impedance of the pull-down path may be the sum of the resistances of resistor 417 and transistor 413 or alternatively the sum of the resistances of resistor 418 and transistor 414. The respective resistances of resistors 417 or 418 may each constitute a substantial portion of the output impedance of the corresponding pull-down path, which reduces the effect of PVT on the output impedance of the pull-down path. More particularly, resistor 418 may provide a majority of the pull-down output impedance Zd for the output signal OUTP. Alternatively or additionally, resistor 417 may provide a majority of the pull-down output impedance (e.g., equal to Zd) for output signal OUTN. In one embodiment, the sizes of pull-down transistors 413 and 414 are selected such that the output impedance Zd for the pull-down path of OUTP when OUTP is at a logic low output and the output impedance Zd for the pull-down path of OUTN when OUTN is at a logic low output are each approximately 50 Ω. Similarly, the sizes of NMOS transistor 441 and pull-up transistors 411 and 412 may be selected such that the output impedance for the pull-up path of OUTP when OUTP is at a logic high output and the output impedance for the pull-up path of OUTN when OUTN is at a logic high output are each approximately 50 Ω.

A resistor 415 may be coupled between the differential output OUTN and the pull-up transistor 411 to reduce variations, such as variations over PVT, in the pull-up output impedance Zu measured at a circuit node that will provide the output signal OUTN. Similarly, a resistor 416 may be coupled between the differential output OUTP and the pull-up transistor 412 to reduce variations in the pull-up output impedance (e.g., equal to Zu) measured at the circuit node that will provide the output signal OUTP. However, resistors 415 and 416 do not make up a significant portion of the pull-up output impedance, since this output impedance will be controlled by the voltage control signal VCTRL generated by replica circuit 470. In one embodiment, resistors 415, 416, 417, and 418 are polysilicon resistors, while in other embodiments resistors 415, 416, 417, and 418 may be other types of resistors. In another embodiment, resistors 415, 416 and corresponding proportional replica resistor 474 may be omitted.

One disadvantage of the output stage 410 may be that the pull-up transistors 411 and 412 experience a body effect (body effect), where the source terminal of one of the pull-up transistors 411 and 412 is at a higher potential than the corresponding body terminal. Thus, the threshold voltage of pull-up transistors 411 and 412 may be greater than the threshold voltage of pull-down transistors 413 and 414. For example, if the same signal is applied to the gate terminals of pull-up transistors 411 and 412 and pull-down transistors 413 and 414, pull-up transistors 411 and 412 will turn on slower and turn off faster than pull-down transistors 413 and 414. Since this may result in an imbalance and asymmetric rising and falling edges of the differential outputs OUTP and OUTN, the addition of resistors 423 and 424 may correct the imbalance.

The gate terminals of pull-up transistors 411 and 412 may be coupled to a first end (or "port") of resistor 423 and a first port of resistor 424, respectively. The gate terminals of pull-down transistors 414 and 413 may be coupled to a second port of resistor 423 and a second port of resistor 424, respectively. The added resistance slows down the turn-off of pull-up transistors 411 and 412 and the turn-on of pull-down transistors 413 and 414. This will reduce the asymmetric rising and falling edges of the differential outputs OUTP and OUTN.

The predriver 420 may include pull-up PMOS transistors 421 and 422, with transistor 421 coupled between VDD and the first port of resistor 423, and transistor 422 coupled between VDD and the first port of resistor 424. The second ports of resistors 423 and 424 may be coupled to pull-down NMOS transistors 425 and 426, respectively. The gates of pull-up PMOS transistor 421 and pull-down NMOS transistor 425 may be coupled to a buffered version of data signal 450 via buffer 460, and the gates of pull-up PMOS transistor 422 and pull-down NMOS transistor 426 may be coupled to an inverted version of data signal 450 via inverter 465.

The regulator circuit 440 may provide power to the driver stage 410 and may include a replica circuit 470 and an error amplifier 442. Together with capacitor 445, error amplifier 442 and replica circuit 470 constitute a feedback loop to regulate power to driver stage 410. Replica circuit 470 can include NMOS transistors 471, 472, and 473 and resistors 474 and 475 as seen in fig. 4. The output VCTRL of the error amplifier 442 may be coupled to the gate of the NMOS transistor 441 and its scaled replica NMOS transistor 471. The non-inverting input of the error amplifier may be coupled to a current source 443 and a resistor 444. Capacitor 445 provides a compensation capacitance to keep the feedback loop stable. Current source 443 and resistor 444 together generate a voltage reference VREF. In one embodiment, VREF may be set to 0.3V, a logic high voltage for the transmitter in high speed mode.

The proportional replica 470 may be sized to generate a current that is some desired fraction of the current consumed by the driver stage 410. Illustrative cases of quarter scale factors are discussed herein. It should be appreciated, however, that certain embodiments may include any of a variety of additional or alternative scaling factors for replica circuits.

In an embodiment, the width of the transistors 472, 473 in the replica circuit 470 may be one quarter of the width of their peer transistors 412, 414 (and/or transistors 411, 413) in the driver stage 410. The pull-up transistors 411 and 412 may each be four times the size of the NMOS transistor 472, and the pull-down transistors 413 and 414 may each be four times the size of the NMOS transistor 473. Similarly, NMOS transistor 441 may be four times the size of NMOS transistor 471. The resistances of resistors 415 and 416 may each be one-fourth the resistance of resistor 474. The resistance of resistor 417 (or resistor 418) and the resistance of the resistor load on the receiver side may be one-fourth of the resistance of resistor 475.

The output impedance Zru (measured at the voltage feedback VFB) of the pull-up path of the proportional replica 470 may be four times the value of Zu. Similarly, the output impedance Zrd of the pull-down path of scaled replica 470 (measured at voltage feedback VFB) may be four times the value of the sum of Zd and off-chip termination resistors. In one embodiment, the sizes of NMOS transistors 471, 472, and 473 and resistors 474 and 475 are selected such that Zrd may be approximately 600 Ω and Zd may be approximately 50 Ω when feedback voltage VFB may be 0.3V, and Zru may be approximately 200 Ω and Zu may be approximately 50 Ω assuming 100 Ω off-chip termination transistors.

In certain embodiments, the regulator circuit is coupled to provide regulated power to the predriver, e.g., where the predriver includes a transistor coupled to and through which power from the supply voltage is provided to the predriver. The regulator circuit may include a first amplifier and an error amplifier, for example, where the output of the error amplifier drives the gate of the transistor and the first amplifier drives the body of the transistor. The regulator circuit may include a proportional replica circuit including a replica of a set of circuits of the driver, where the set of circuits are coupled to provide differentially output signals. The replica circuit of the regulator circuit can be coupled to provide a feedback voltage to an error amplifier, e.g., where the error amplifier will amplify the difference between the feedback voltage and a reference voltage. The proportional replica circuit may be further coupled to a feedback loop extending from the transistor back to the first amplifier.

FIG. 5 shows select elements of a high speed differential transmitter 500 having a predriver regulator and an output stage open-circuit regulator, according to an embodiment. By way of illustration and not limitation, the high speed differential transmitter 500 may include an output stage 510, a predriver 520, an output stage open circuit output regulator 530, and a predriver regulator 540.

Open-circuit output regulator 530 may include a current source 531, NMOS transistors 532 and 534, and a resistor 533, where NMOS transistors 532 and 534 form a current mirror. Current source 531 may be coupled between VDD and a first port of NMOS transistor 532. The resistor 533 may be coupled between the second port of the NMOS transistor 532 and ground. A first port of the NMOS transistor 534 may be coupled to VDD, with a second port of the NMOS transistor 534 outputting the regulator voltage 580. Capacitor 535 may be coupled between regulator voltage 580 and ground, for example, to provide decoupling capacitance to reduce regulator voltage noise.

Predriver 520 may include pull-up PMOS transistors 521 and 522 coupled to a first port of resistor 523 and a first port of resistor 524, respectively. The second ports of resistors 523 and 524 may be coupled to pull-down NMOS transistors 525 and 526, respectively. The gates of pull-up PMOS transistor 521 and pull-down NMOS transistor 525 may be coupled to a buffered version of data signal 563 via buffer 564, and the gates of pull-up PMOS transistor 522 and pull-down NMOS transistor 526 may be coupled to an inverted version of data signal 563 via inverter 565.

The power provided to the pull-up transistors 511 and 512 of the output stage 510 may be controlled by an open-circuit output regulator 530. Alternatively or additionally, the power provided to the pull-up transistors 521 and 522 of the predriver 520 may be controlled by the predriver regulator 540. Regulator voltage 580 may be determined by current source 531, NMOS transistors 532, 534, and resistor 533. Open-circuit regulators occupy less silicon area and consume less power than closed-circuit regulators. In one embodiment, regulator voltage 580 may be set to about 0.4V.

A disadvantage of an open-circuit regulator is its regulator voltage 580 variation with PVT changes, however, the replica circuit 570 in the predriver regulator 540 can track PVT changes. For example, replica circuit 570 may comprise a replica of a set of circuits in driver 510 that are coupled to provide differentially output signals. By way of illustration and not limitation, NMOS transistor 571 and resistors 572, 573 of replica circuit 570 may be a replica of transistor 511 and resistors 515, 517, and/or a replica of transistor 512 and resistors 516, 518. A first port of NMOS transistor 571 may be coupled to regulator voltage 580 and a second port of NMOS transistor 571 may be coupled to a first port of resistor 572. Resistor 573 may be coupled between the second port of resistor 572 and ground. A second port of resistor 572 may be coupled to an inverting input of error amplifier 542. In the illustrated embodiment, replica circuit 570 is a replica of not all of the circuit elements in any branch of driver 510. However, in one embodiment, an additional NMOS transistor may be coupled between resistor 573 and ground, for example, with the gate of such additional NMOS transistor coupled to regulator voltage 590.

The resistor pair 515, 516 (or resistor pair 517, 518) corresponding to the replica resistor pair 572, 573 can reduce variation in the output impedance of the output stage 510 versus changes in PVT. In one embodiment, resistors 515, 516 and their corresponding proportional replica resistors 572 may be omitted. As discussed with respect to resistors 423 and 424, resistors 523 and 524 may correct the asymmetric rising and falling edges of differential outputs OUTP and OUTN caused by output stage 510.

The predriver regulator 540 provides a regulator voltage 590 to the predriver 520. Regulator voltage 590 may be controlled by a feedback loop including error amplifier 542, transistor 541, and the elements of replica circuit 570. The replica circuit 570 and the output stage 510 have the same power supply, i.e., regulated voltage 580. The feedback loop will generate a feedback voltage VFB from replica circuit 570 for amplifier 542 to subtract from reference voltage VREF. In one embodiment, VREF may be equal to the logic high voltage of the high speed mode (e.g., 0.3V), and the width of the transistors in replica circuit 570 may be some fraction (e.g., one quarter) of their counterparts in output stage 510.

Error amplifier 542 may require a high gain to achieve good accuracy in replica circuit 570. However, the output impedance of error amplifier 542 may also be high, and thus, this may cause the feedback loop response of VFB to be slow. As loading conditions change, the regulator voltage 590 may drift away from the target value and cause regulator voltage noise before the slow feedback loop pulls the regulator voltage 590 back. Regulator voltage noise may appear as common mode noise at the differential outputs OUTP and OUTN. To reduce the occurrence of common mode noise, a second feedback loop may be added. This second feedback loop may include an amplifier 561, a resistor 549, and a capacitor 546. The gain of amplifier 561 may be low to result in a faster feedback loop. Resistor 549 and capacitor 546 may form a low pass filter to filter out regulator voltage drift and may be coupled to the non-inverting input of amplifier 561. The inverting input of amplifier 561 may be coupled to regulator voltage 590. As the regulator voltage 590 drifts away from the target value, the amplifier 561 drives the back gate or body of transistor 541 to correct for the drift before the slow feedback loop responds.

In an embodiment, resistor 562 can be coupled between regulator voltage 590 and ground to limit regulator voltage 590 from floating when data signal 563 is not toggled. The capacitor 560 may be coupled to the regulator voltage 590 as a decoupling capacitor to reduce high frequency noise in the regulator voltage 590.

As shown above, in certain embodiments, a transmitter may include another regulator circuit to provide regulated power to a driver of the transmitter, e.g., where the other regulator circuit is coupled to the regulator circuit, from which power to the pre-driver is to be regulated. In an alternative embodiment, a single regulator circuit may provide regulated power to both the predriver and the driver of the transmitter.

FIG. 6 shows select elements of a high speed differential transmitter 600 with predriver regulators according to an embodiment. The high speed differential transmitter 600 may be similar to that in fig. 5, but with the open output regulator 530 omitted, the output stage 510 and the replica circuit 570 connected directly to VDD. By omitting the open output regulator, the area occupied by the high speed differential transmitter circuit can be reduced without having a large impact on the performance of the transmitter.

By way of illustration and not limitation, high speed differential transmitter 600 may include an output stage 610, a predriver 620, and a regulator circuit 640. Predriver 620 may include pull-up PMOS transistors 621 and 622 coupled to a first port of resistor 623 and a first port of resistor 624, respectively. The second ports of resistors 623 and 624 may be coupled to pull-down NMOS transistors 625 and 626, respectively. The gates of pull-up PMOS transistor 621 and pull-down NMOS transistor 625 may be coupled to a buffered version of data signal 663 via buffer 664, and the gates of pull-up PMOS transistor 622 and pull-down NMOS transistor 626 may be coupled to an inverted version of data signal 663 via inverter 665.

Pull-up transistors 611 and 612 of output stage 610 may be directly coupled to VDD. The power provided to pull-up transistors 621 and 622 of predriver 620 may be controlled by regulator 640, which includes replica circuit 670. For example, replica circuit 670 may comprise a replica of a set of circuits in driver 610 that are coupled to provide differentially output signals. By way of illustration and not limitation, NMOS transistor 671 and resistors 672, 673 of replica circuit 670 may be a replica of transistor 611 and resistors 615, 617, and/or a replica of transistor 612 and resistors 616, 618. A first port of NMOS transistor 671 may be directly coupled to VDD, and a second port of NMOS transistor 671 may be coupled to a first port of resistor 672. Resistor 673 may be coupled between the second port of resistor 672 and ground. A second port of resistor 672 may be coupled to an inverting input of error amplifier 642. In the illustrated embodiment, the replica circuit 670 is a replica of not all of the circuit elements in any branch of the driver 610. However, in one embodiment, an additional NMOS transistor may be coupled between resistor 673 and ground, for example, with the gate of such additional NMOS transistor coupled to regulator voltage 690.

The resistor pair 615, 616 (or resistor pair 617, 618) corresponding to the replica resistor pair 672, 673 may reduce variations in the output impedance of the output stage 610 over changes in PVT. In one embodiment, the resistors 615, 616 and their corresponding proportional replica resistors 672 may be omitted. As discussed with respect to resistors 423 and 424, resistors 623 and 624 may correct the asymmetric rising and falling edges of differential outputs OUTP and OUTN caused by output stage 610.

The pre-driver 640 provides the regulator voltage 690 to the pre-driver 620. Regulator voltage 690 may be controlled by a feedback loop including error amplifier 642, transistor 641, and elements of replica circuit 670. The replica circuit 670 and the output stage 610 have the same power supply VDD. The feedback loop will generate a feedback voltage VFB from replica circuit 670 for amplifier 642 to subtract from reference voltage VREF. In one embodiment, VREF may be equal to the logic high voltage of the high speed mode (e.g., 0.3V) and the width of the transistors in replica circuit 670 may be some fraction (e.g., one quarter) of their counterparts in output stage 610.

Error amplifier 642 may require a high gain to achieve good accuracy in replica circuit 670. However, the output impedance of error amplifier 642 may also be high, which may therefore cause the feedback loop response of VFB to be slow. As loading conditions change, regulator voltage 690 may drift away from a target value and cause regulator voltage noise before slow feedback loop pulls regulator voltage 690 back. Regulator voltage noise may appear as common mode noise at the differential outputs OUTP and OUTN. To reduce the occurrence of common mode noise, a second feedback loop may be added. This second feedback loop may include an amplifier 661, a resistor 649, and a capacitor 646. The gain of amplifier 661 can be low to result in a faster feedback loop. Resistor 649 and capacitor 646 may form a low pass filter to filter out regulator voltage drift and may be coupled to the non-inverting input of amplifier 661. The inverting input of amplifier 661 may be coupled to regulator voltage 690. As the regulator voltage 690 drifts away from the target value, the amplifier 661 drives the back gate or body of the transistor 641 to correct for the drift before the slow feedback loop responds.

In an embodiment, resistor 662 may be coupled between regulator voltage 690 and ground to limit regulator voltage 690 from floating when data signal 663 is not toggled. Capacitor 660 may be coupled to regulator voltage 690 as a decoupling capacitor to reduce high frequency noise in regulator voltage 690.

Techniques and architectures for providing high speed transmissions and low power transmissions have been described herein. In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the various embodiments.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

Some portions of the detailed descriptions herein are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the discussion herein, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Certain embodiments also relate to an apparatus for performing the operations herein. Such an apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs) such as dynamic RAM (dram), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description herein. In addition, some embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein.

In addition to those described herein, various modifications may be made to the disclosed embodiments and implementations thereof without departing from their scope. The illustrations and examples herein should, therefore, be construed in an illustrative rather than a restrictive sense. The scope of the invention should be measured solely by reference to the claims that follow.

Claims (18)

1. A transmitter, comprising:

a pre-driver coupled to receive a data signal and to output a driver input voltage based on the data signal;

a driver coupled to the pre-driver, the driver including a first set of circuit elements coupled in series with each other, wherein the first set of circuit elements are coupled to provide a differentially output first output signal based on the driver input voltage; and

a first regulator circuit coupled to provide regulated power to the driver, the first regulator circuit including:

a first transistor coupled between the driver and a supply voltage rail;

a proportional replica circuit having a replica of the first set of circuit elements; and

an error amplifier, wherein the proportional replica circuit and the first transistor are both coupled to an output of the error amplifier, wherein the proportional replica circuit is coupled to provide a feedback voltage to the error amplifier, wherein the error amplifier is coupled to amplify a difference between the feedback voltage and a reference voltage.

2. The transmitter of claim 1, the first set of circuit elements having:

a second transistor coupled to the first output signal;

a first resistor coupled between the second transistor and the first output signal; and

a third transistor coupled to the first output signal.

3. The transmitter of claim 2, wherein a second resistor is coupled between the third transistor and the first output signal.

4. The transmitter of claim 1, wherein the driver includes a second set of circuit elements coupled in series with each other, the second set of circuit elements coupled to provide a second output signal of the differential output, wherein the second set of circuit elements is coupled in parallel with the first set of circuit elements.

5. The transmitter of claim 1, wherein the proportional replica circuit is a quarter-proportional replica of the first set of circuit elements.

6. The transmitter of claim 1, wherein a gate of the first transistor and a gate of a transistor of the proportional replica circuit are coupled to the output of the error amplifier.

7. An imaging device, comprising:

an array of pixels;

readout circuitry to generate image data based on signals from the pixel array; and

a transmitter coupled to the readout circuitry to transmit the image data, the transmitter comprising:

a pre-driver coupled to receive a data signal and to output a driver input voltage based on the data signal;

a driver coupled to the pre-driver, the driver including a first set of circuit elements coupled in series with each other, wherein the first set of circuit elements are coupled to provide a differentially output first output signal based on the driver input voltage; and

a first regulator circuit coupled to provide regulated power to the driver, the first regulator circuit including:

a first transistor coupled between the driver and a supply voltage rail;

a proportional replica circuit having a replica of the first set of circuit elements; and

an error amplifier, wherein the proportional replica circuit and the first transistor are both coupled to an output of the error amplifier, wherein the proportional replica circuit is coupled to provide a feedback voltage to the error amplifier, wherein the error amplifier is coupled to amplify a difference between the feedback voltage and a reference voltage.

8. The imaging device of claim 7, the first set of circuit elements having:

a second transistor;

a first resistor coupled between the second transistor and the first output signal; and

a third transistor coupled to the first output signal.

9. The imaging device of claim 8, wherein a second resistor is coupled between the first output signal and the third transistor.

10. The imaging device of claim 8, wherein the driver includes a second set of circuit elements coupled in series with each other, the second set of circuit elements coupled to provide a second output signal of the differential output, wherein the second set of circuit elements is coupled in parallel with the first set of circuit elements.

11. The imaging device of claim 7, wherein a gate of the first transistor and a gate of a transistor of the proportional replica circuit are coupled to the output of the error amplifier.

12. A transmitter, comprising:

a pre-driver coupled to receive a data signal and to provide a driver input voltage based on the data signal;

a driver coupled to the pre-driver, the driver including a first set of circuit elements coupled in series with each other, wherein the first set of circuit elements are coupled to provide a differentially output first output signal based on the driver input voltage;

a first regulator circuit coupled to provide regulated power to the predriver, the first regulator circuit including:

a first transistor, wherein the predriver is coupled to a supply voltage via the first transistor;

a proportional replica circuit having a replica of the first set of circuit elements;

an error amplifier; and

a first amplifier, wherein an output of the error amplifier and an output of the first amplifier are both connected to the first transistor, wherein the proportional replica circuit is coupled to provide a feedback voltage to the error amplifier, wherein the error amplifier is used to amplify a difference between the feedback voltage and a reference voltage, and wherein the proportional replica circuit is further coupled to a feedback loop extending from the transistor back to the first amplifier.

13. The transmitter of claim 12, wherein the first set of circuit elements includes:

a second transistor;

a first resistor coupled between the second transistor and the first output signal; and

a third transistor coupled to the first output signal.

14. The transmitter of claim 13, wherein the replica of the first set of circuit elements includes a fourth transistor corresponding to the third transistor, and wherein the replica circuit is coupled to the feedback loop via the fourth transistor.

15. The transmitter of claim 14, further comprising a second regulator circuit coupled to the first regulator circuit via the fourth transistor, the second regulator circuit coupled to provide regulated power to the driver.

16. The transmitter of claim 14, wherein the fourth transistor is further coupled to conduct current directly from the supply voltage according to a voltage of the feedback loop.

17. The transmitter of claim 13, wherein a second resistor is coupled between the third transistor and the first output signal.

18. The transmitter of claim 12, wherein the first amplifier is coupled to provide an output representative of a difference between a reference voltage and the feedback voltage.