HK1170079B - Analogue/digital delay locked loop - Google Patents

Abstract

A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Description

Analog/digital delay locked loop

Description of divisional applications

This application is a divisional application entitled "analog/digital delay locked loop" filed on 29/12/2003, under the international application number 200380107873.2 (PCT/CA 2003/002040).

Technical Field

The invention relates to an analog/digital delay locked loop.

Background

Many devices, such as Synchronous Dynamic Random Access Memories (SDRAMs) and microprocessors, receive an external clock signal generated by an external clock source, such as a crystal oscillator. An external clock signal received through an input on a device is routed through a tree of buffer circuits to various circuits within the device. The buffer tree introduces a common delay between the external clock and each buffered clock.

Typically, a Delay Locked Loop (DLL) with an adjustable delay line is used to synchronize the buffered clock signal with the external clock signal by delaying the external clock signal applied to the buffer tree. The DLL includes a phase detector for detecting a phase difference between an external clock signal and a buffered clock signal. Based on the detected phase difference, the DLL synchronizes the buffered clock signal with the external clock signal by adding an appropriate delay to the external clock signal until the buffered clock signal (internal clock) is in phase with the external clock signal. The DLL may be implemented as an analog delay locked loop or a digital delay locked loop. In an analog delay locked loop, a voltage controlled delay line is used to delay an external clock signal.

Fig. 1 is a block diagram of a prior art analog Delay Locked Loop (DLL) 100. The analog DLL100 synchronizes an internal clock signal KI with an external clock signal CKE. The external clock signal CKE is coupled to the voltage controlled delay line 102 and the voltage controlled delay line 102 is coupled to a clock tree buffer 108. The delayed external clock signal CKE is fed to a clock tree buffer 108 where it is propagated to the output of the tree and applied to the various circuits. The delay through the clock tree buffer 108 causes a phase difference between the external clock signal CKE and the internal clock signal CKI. The voltage controlled delay line 102 adjusts the delay of the external clock signal CKE by either increasing or decreasing the delay to synchronize the external and internal clock signals.

To determine the appropriate delay in the delay line, one of the outputs of the clock tree buffer 108 is connected to the phase detector 104, where it is compared to the external clock signal CKE. The phase detector 104 detects a phase difference between the internal clock signal CKI and the external clock signal CKE. The output of the phase detector 104 is integrated by a charge pump 106 and a loop filter capacitor 112 to provide a variable bias voltage VCTRL 110 for the Voltage Controlled Delay Line (VCDL) 102. The bias voltage VCTRL selects the amount of delay to be added to the external clock signal by the VCDL 102 to synchronize the internal clock signal CKI with the external clock signal CKE.

The phase detector 104 is a D-type flip-flop having a D-input coupled to the external clock signal CKE and a clock input coupled to the internal clock signal CKI. On each rising edge of the internal clock signal CKI, the output of the phase detector 104 indicates whether the rising edge of the internal clock signal precedes or follows the rising edge of the external clock signal.

The analog DLL100 produces a voltage controlled delay with high accuracy. However, the performance of the analog DLL varies over the frequency range because the delay produced using the voltage controlled delay line varies non-linearly with changes in the bias control voltage VCTRL.

Fig. 2 is a graph illustrating the non-linear control voltage characteristic of the voltage controlled delay line shown in fig. 1. Typically, devices support a wide range of external clock frequencies, within which operating frequencies are selected for a particular device. In the example shown in fig. 2, the device may operate at any frequency between point a and point C. The selected operating frequency is at point B.

As shown, the control voltage characteristic is non-linear: is sharp at one end of the control voltage range (point C) and almost flat at the opposite end (point a). This control voltage characteristic causes DLL instability at point C and a longer lock time at point a. A wide range of frequencies (delays) is controlled by the bias voltage VCTRL.

Referring again to fig. 1, the bias voltage VCTRL is the output of the charge pump 106 and remains in a high-impedance state most of the time. Any noise on the bias voltage signal VCTRL interferes with the output of the analog DLL 100. For example, if the analog DLL is operating at point B, a small voltage change (Δ V) due to noise results in a large change in delay. Thus, in the illustrated broad frequency range from point C to point a, the analog DLL is very sensitive to noise when operating at point B. Therefore, the analog DLL is not stable over a wide frequency range.

Digital DLLs do not have the stability problems of analog DLLs. However, the accuracy of a digital DLL is as high as that of an analog DLL, since the delay is provided by combining fixed share (stride) delays. The smaller the delay step, the higher the accuracy. However, since more delay elements are required to cover a wider frequency range, the reduction in step size causes a corresponding increase in silicon area.

Disclosure of Invention

A delay locked loop having high accuracy, good stability and fast lock time over a wide frequency range is presented. The delay locked loop is a delay locked loop that operates over a wide frequency range, combining shorter lock time, higher accuracy and stability with lower energy consumption and smaller silicon area.

The delay locked loop includes a digital delay circuit and an analog delay circuit. The digital delay circuit enables the delay element to provide coarse phase adjustment in the delay locked loop. The analog delay circuit provides fine phase adjustment in a delay locked loop while holding the digital delay circuit at a fixed delay. A lock detector in the digital delay circuit detects completion of the coarse phase adjustment, freezes (freeze) the fixed delay upon completion and enables the fine phase adjustment.

A digital delay circuit including a plurality of fixed delay elements operates over a wide delay range. The analog delay circuit operates over a smaller delay range within the wide delay range and remains at a second fixed delay until the digital delay circuit completes the coarse phase adjustment.

Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIG. 1 is a prior art analog Delay Locked Loop (DLL);

FIG. 2 is a graph illustrating the non-linear control voltage characteristic of the voltage controlled delay line shown in FIG. 1;

FIG. 3 is a block diagram of a wide frequency range delay locked loop according to the principles of the present invention;

4A-4B illustrate delay elements in DCDL and VCDL;

FIG. 5 is a schematic diagram of one embodiment of any of the delay elements shown in FIGS. 4A-4B;

fig. 6 is a graph illustrating a narrow frequency range of a non-linear control voltage characteristic of the VCDL in the DLL shown in fig. 3;

FIG. 7 is a schematic diagram of an embodiment of the lock detector and analog switch shown in FIG. 3;

8A-C are timing diagrams showing the relationship between the phase detector output and the phase difference between the clocks;

fig. 9 is a timing diagram showing signals in the schematic shown in fig. 7.

Detailed Description

Preferred embodiments of the present invention will be described below.

Fig. 3 is a block diagram of a wide range Delay Locked Loop (DLL)300 in accordance with the principles of the present invention. The wide frequency range DLL 300 has two domains of operation: the digital domain including digital delay circuit 302 and the analog domain including analog delay circuit 304.

In a DLL, high accuracy, small silicon area usage and lower energy are typically achieved using analog techniques, while better stability and shorter lock times are typically achieved using digital techniques. The wide frequency range DLL 300 combines these two techniques to provide high accuracy over a wide frequency range, better stability, and faster lock time. The digital delay circuit 302 is responsible for coarse phase adjustment during initialization, while the analog delay circuit 304 is responsible for fine phase adjustment during normal operation after the coarse phase adjustment is completed by the digital delay circuit 302. Digital delay circuit 302 operates over a wide delay range and brings delay locked loop 300 to a stable operating point during power-up initialization. In normal operation, the analog delay circuit 304 operates in a smaller delay range of a stable operating point within a wider delay range and holds the delay locked loop at the stable operating point while holding the digital delay circuit 302 at a fixed delay.

The total delay provided by the DLL includes: a Digitally Controlled Delay Line (DCDL)306 having a set of delay elements each having a fixed delay, and a Voltage Controlled Delay Line (VCDL) 312. The combination of the DCDL delay provided by the DCDL 306 and the VCDL delay provided by the VCDL 312 provides an accurate delay. Only one of these domains can change the DLL delay at any time. At power-up initialization, the digital delay circuit 302 changes the DCDL 306 (coarse delay). After the coarse phase adjustment is completed (lock is reached), the DCDL delay is held at a fixed number of DCDL delay elements (frozen) and the analog delay circuit 304 changes the DLL delay to provide a fine phase adjustment by changing the VCDL delay.

The digital delay circuit 302 operates over a wide delay range to bring the DLL 300 quickly to the operating point (lock) in order to provide a short lock time. A lock detector 310 in the digital delay circuit 302 detects when the digital delay circuit 302 has reached a stable operating point for the DLL delay and is able to switch control of the DLL delay to the analog delay circuit 304.

The phase detector 320 detects a phase difference between the external clock signal CKE and the internal clock signal CKI. Phase detector 320 may be any phase detector known to those skilled in the art. In the illustrated embodiment, phase detector 320 (FIG. 3) includes a D-type flip-flop with CKI coupled to the clock input and CKE coupled to the D input. The rising edge of CKI latches the state of CKE at the output of the D-type flip-flop (Ph _ det).

The analog delay circuit 304 includes a multiplexer 314, a VCDL 312, and a charge pump 316. The VCDL 312 is a chain of differential input-differential output stages (delay elements) each controlled by two bias voltages VBP, VBN that can be provided by two different sources under the control of the multiplexer 314, as will be described in further detail later. In FIG. 3, a single signal is used to represent the two bias voltages from each source, namely VBP2, VBN2 and VBP1, VBN 1.

The multiplexer 314 selects the source of the VCDL bias voltage 322 to the VCDL 312. The VCDL bias voltage 322 may be a bias voltage pair VBP1, VBN1 provided by the bias voltage generator 318, or a variable bias voltage pair VBP2, VBN2 provided by the charge pump 316. During initialization, the pair of differential bias voltages VBP1, VBN1 is provided to the VCDL bias voltage 322 by the multiplexer 314 before the DCDL 306 achieves lock. Thus, the VCDL bias voltage 322 provides a constant VCDL delay while the digital delay circuit 302 selects the DCDL delay. The delay may be in the middle of the entire VCDL delay range to achieve fine tuning in both the positive and negative directions, as discussed below.

At initialization, the code stored in counter 308 is initialized to zero, corresponding to a minimum delay; i.e., the minimum number of delay elements in the DCDL 306 that are enabled. The lock detector 310 allows the DCDL 306 to increase the DCDL delay by adding a delay element as the counter 318 increments until the most recent rising edge of the internal clock signal cki aligns with the rising edge of the external clock signal CKE. The counter 308 is incremented by the external clock signal CKE until lock is reached (the clock edges are aligned). In one embodiment, counter 308 is an up counter that increments on each rising edge of external clock signal CKE while being enabled by the SW signal from lock detector 310. The delay elements in the DCDL 306 are added to the DCDL delay line according to the count value of c bits output by the counter 308 to achieve the minimum number of DCDL delay elements required according to the bias voltage pair VBP1, VBN 1.

After the clock edges are aligned, the SW signal output by the lock detector 310 disables any further incrementing of the counter 308. The VCDL bias voltage 322 is provided by the bias voltage pair VBP2, VBN2, the output of the charge pump 316 through the multiplexer 314. The charge pump 316 may be any charge pump known to those skilled in the art.

By enabling only a minimum number of delay elements in the DCDL 306, the overall delay line has a minimum length to minimize noise. The enabled delay elements provide coarse phase adjustment in the delay locked loop. Once lock is achieved, the digital delay circuit 302 is held at a fixed delay by disabling further incrementing of the counter 308. Only the VCDL portion of the DLL delay line can be changed by the analog delay circuit 304 to provide fine phase adjustment in the delay locked loop. The analog delay circuit 304 fine-tunes the DLL delay to compensate for all drift and condition variations during normal operation of the DLL to keep the external and internal clock signal edges aligned by changing the VCDL delay added to the fixed delay provided by the DCDL. The analog controlled delay line 310 changes the bias voltage to the VCDL delay element 402 by detecting the phase difference between the clocks, changing the VCDL delay up or down.

Fig. 4A-4B illustrate the delay elements in the DCDL and VCDL in more detail. The Digitally Controlled Delay Line (DCDL) includes a chain structure of DCDL delay elements 400, while the Voltage Controlled Delay Line (VCDL) includes a chain structure of VCDL delay elements 402. The delay of each DCDL cell 400 is fixed by permanently connecting the bias voltage of each DCDL cell 400 to the fixed bias voltage pair VBP1, VBN 1. The fixed bias voltage pairs VBP1, VBN1 are provided by a bias voltage generator 318 (fig. 3), which bias voltage generator 318 may be any type of voltage initialization device, such as a band-gap reference without necessarily corresponding to the VCDL bias voltage 322 initially applied to the VCDL, as discussed in further detail below.

Figure 5 is a schematic diagram of one embodiment of any of the delay elements shown in figures 4A-4B. Delay element 400 includes a source connected pair of NMOS devices T1, T2 having symmetric loads 500, 502.

The differential input clock signals CKEI-, CKEI + are connected to respective gates of NMOS devices T1, T2, where CKEI + is connected to the gate of NMOS device T1 and CKEI-is connected to the gate of NMOS device T2. The differential output clock signals CKEO-, CKEO + are coupled to respective drains of the NMOS devices T1, T2. The sources of the NMOS devices T1 and T2 are connected and also connected to the drain of an NMOS current source T3. The NMOS current source T3 compensates for drain and substrate voltage variations.

Symmetric load 500 includes diode-connected PMOS device T4 in parallel with biased PMOS device T5. Symmetric load 502 includes a diode-connected PMOS device T7 in parallel with a biased PMOS device T6. The effective resistance of the symmetric loads 500, 502 changes with changes in the bias voltage VBP1, causing corresponding delay changes from the differential clock input to the differential clock output through the delay stages.

Returning to fig. 4, at initialization, the delay element 400 in the DCDL 306 is not enabled, which is for the c-bit count value output from the counter to be zero and only the multiplexer 408 is enabled. The DLL delay includes only the fixed delay provided by the demultiplexer 404, the multiplexer 408, and the VCDL delay element 402 in the VCDL coupled to the fixed bias voltage pair VBP1, VBN 1. The VCDL delay provided by the VCDL depends on the fixed bias voltage pair VBP1, VBN 1. In the embodiment shown in fig. 4A-4B, the DCDL delay element 400 and the VCDL delay element 402 are the same delay element with voltage controlled delay. However, in alternative embodiments, the DCDL delay element 400 may be different from the VCDL delay element 402, as described and illustrated in fig. 5.

The DCDL delay is changed by increasing the number of DCDL delay elements 400, where each DCDL delay element 400 has the same delay set by the fixed bias voltage pair VBP1, VBN 1. In the illustrated embodiment, during initialization, the same fixed bias voltage pair VBP1, VBN1 is connected to the DCDL delay element 400 and the VCDL element 402. However, in alternative embodiments, the fixed bias voltages connected to the VCDL delay element 402 and the DCDL delay element 400 may be different. For example, the first bias voltage VBP1 may be set to 0.3VDD connected to DCDL, while the second bias voltage VBP2 may be set to 0.5VDD connected to VCDL. The VCDL delay is initially fixed, with each of the three VCDL delay elements 402 numbered 1-3 connected to a fixed bias voltage pair VBP1, VBN1, but during normal operation, the VCDL delay changes as the VCDL bias voltage pair 322VBP2, VBN2 changes.

The number of delay elements enabled in the DCDL 306 depends on the c-bit count 406 output by the counter 308. The c-bit count 406 is coupled to mux selection logic 430 that provides m-bit mux selection signals, one of each of which is coupled to each of the multiplexers in the DCDL 306, and d-bit demux selection signals 432 coupled to the demux 404. The d-bit demux select signal 406 is coupled to the demux 404 to select the output through which the external clock is output to the DCDL 306. In one embodiment, mux logic 430 is a decoder that decodes the c-bit count to provide an m-bit mux signal. In the illustrated embodiment, m and d are both 7, and c is 3. However, in alternative embodiments, m and d may be different. There are six delay elements 400, labeled 4-9. The mux select logic 430 decodes the three bit count 406 to select one of seven multiplexers through which to provide the external clock to the various delay elements shown in table 1 below. The Most Significant Bit (MSB) of the seven-bit multiplexed selection signal corresponds to the selection signal of multiplexer 420 and the Least Significant Bit (LSB) of the seven-bit multiplexed signal corresponds to the selection signal of multiplexer 408. Thus, as the count increases, the number of enabled delay elements also increases. In an alternative embodiment, the mux selection logic may be implemented as a shift register that is clocked by an external clock and enabled by the SW signal.

Counter output count [2:0] mux select demux select

TABLE 1

After lock has been reached, the external clock signal CKE is delayed by DCDL delay elements enabled according to the c-bit count output by the counter 308. Control of the DLL delay is switched to the VCDL 312 by switching the bias voltage supplied to the VCDL from the bias voltage pair VBP1, VBN1 to the bias voltage pair VBP2, VBN2 via the multiplexer 314 (fig. 3).

Thus, the DLL delay includes: the minimum delay provided by the enabled DCDL delay element 400 in the DCDL 306 and the additional delay provided by the VCDL 312 in order to provide an accurate DLL delay. The stability of the DLL is increased by using the digital domain to cover a wide delay range to obtain a minimum delay, and then freezing the digital domain to allow the analog domain to operate over a smaller delay range by controlling the DLL delay to provide fine phase adjustment in the delay locked loop. The bias voltage connected to the VCDL bias voltage 322 is set so that the VCDL does not control the overall DLL delay until after a lock condition is detected by the digital domain. Before the lock condition, the VCDL only provides a constant delay independent of the phase difference between the clocks.

In one embodiment, counter 308 is implemented as a ripple counter. Initially, the counter 308 is reset to 0. The demultiplexer 404 manipulates the external clock CKE to the delay elements based on the d-bit demux select signal 432 output by the mux select logic 430. When the output of the counter 308 is set to "0" and the demux select signal 432 is set to "1111110," CKE is manipulated through the output 422 of the demux 404 connected to the multiplexer 408 and the DCDL element 400 is not enabled.

After the output of counter 308 is incremented from 000 to 001 as shown in table 1 by CKE, clock signal CKE is operated by the counter output set to "1" through output 424 of demultiplexer 404 to enable the DCDL delay stage labeled 4. Multiplexer 410 is enabled to allow CKE to be steered through DCDL delay stage 400 when the m-bit multiplexer select signal output by multiplexer select logic 430 operates to delay CKE to the VCDL through multiplexer 408. Those skilled in the art will understand that: embodiments of the demultiplexer 404 may be implemented using a plurality of PMOS transistors each enabled by an active logic low signal (with all other signals held at logic high, as shown in table 1). Alternatively, the demultiplexer 404 may be implemented using NMOS transistors or full CMOS pass gates.

When the counter output is set to six and CKE is directed through the demux output 426 via the multiplexers 420, 418, 416, 414, 412, 410, 408 and the delay elements labeled 9-4, all six DCDL delay stages are enabled. The DCDL line is frozen when the counter 308 is disabled by the SW signal being set to a logic low.

Fig. 6 is a graph illustrating the non-linear control voltage characteristic of the narrow delay range of the VCDL 312 in the DLL 300 shown in fig. 3. In the illustrated embodiment, the digital domain provides the minimum delay for the operating range of DLL 300 to reach point B. After the lock condition has been obtained, the analog domain operates within a narrow delay range 600 from point B-high to point B-low. This delay range is much smaller than the wide delay range supported by the DLL, but can be controlled by the same larger voltage range as the pure analog case shown in fig. 2. The small delay range, controlled by the large voltage range, ensures stability of the analog domain during normal operation of the DLL.

As shown, the analog delay circuit 304 operates over a voltage range of 200mV to 800mV, within a delay range of 85ns to 80ns to provide fine phase adjustment to the delay locked loop. In contrast to the wide delay range over the same voltage range shown in fig. 2, a small change in the control voltage (Δ V) does not have a substantial effect on the delay.

Fig. 7 is a schematic diagram of an embodiment of lock detector 310 and multiplexer 314 shown in fig. 3. The lock detector 310 includes two SR flip-flops 700, 702, an and gate 706, and an inverter 704. The SR flip-flop 700 detects when the internal clock signal CKI is within the phase detection window. The SR flip-flop 702 detects when the internal clock signal CKI is in phase with the external clock signal CKE. Once the internal clock signal CKI is in phase with the external clock signal CKE, the SW signal is set to logic "0" to disable further changes to the DCDL delay.

The lock detector output SW is held at logic "0" until lock is reached, and is set to logic "1" after lock is reached. Before lock is achieved, a logic "0" on the SW signal connects the fixed bias voltage through the multiplexer 314 to provide the VCDL bias voltage pair 322. After the lock has been reached, a logic "1" on SW is connected through the multiplexer 314 to the variable bias voltage pair VBP2, VBN2 to provide the VCDL bias voltage pair 322 to allow the VCDL 312 to fine tune the overall delay.

During power-up of the device, the reset signal connected to the R inputs of the SR flip-flop 700 and the SR flip-flop 702 is set to a logic "1". The flip-flops 700, 702 are reset simultaneously with the respective Q outputs (LC1, SW) set to logic "0". The SR flip-flops 700, 702 remain in a reset state at a logic "0" on the respective Q outputs until the phase detector 320 detects that the phase difference between the clock signals CKE, CKI is within the phase detection window. The phase difference is within the phase detection window while a rising edge of the internal clock signal CKI occurs after a falling edge of the external clock signal CKE. The output of the phase detector (Ph _ det) changes to logic "0". A logic "0" on Ph _ det changes the S input of the SR flip-flop 700 to a logic "1" through the inverter 704, setting the SR flip-flop 700 (i.e., the Q output changes to a logic "1"). The delay provided by the DCDL 306 continues to increase, further delaying the rising edge of the internal clock signal until the internal wall clock signal and the external clock signal are in phase. The SR flip-flop 702 is set on the next rising edge of Ph _ det that occurs when the rising edge of CKE is detected after the rising edge of CKI. The Q output of the SR flip-flop 702 is set to a logic "1," indicating a coarse phase adjustment provided by the digital delay circuit. The logic "1" on the output of the SR flip-flop 702, the SW signal, through the multiplexer 314, disconnects the VCDL bias signal 322 from the bias voltage pair VBP1, VBN1, and connects the bias voltage pair VBP2, VBN2 from the charge pump 316 (fig. 3) to the bias voltage pair 322 of the VCDL to the VCDL 312.

The lock detector 310 remains in a locked state with SW set to logic "1" until the system is reset. While in the locked state, but the digital domain is no longer controlling the delay, since the code stored in the counter 308 is frozen to freeze the DCDL delay while SW is set to logic "1".

Fig. 8A-C are timing diagrams showing the relationship between the phase detector output (Ph-det) and the phase difference between the clocks. Referring to fig. 8A, at initialization, phase detector 320 (fig. 3) detects that an internal clock rising edge occurs after an external clock rising edge. The rising edge of C KI will latch a "1" on the Ph _ det output of the D flip-flop. CKE rising edge continues to increment the code to add additional delay to the DCDL.

Referring to fig. 8B, the phase detector detects that the CKI rising edge is now after the falling edge of CKE, i.e., the external clock rising edge is within the phase detection window. The rising edge of CKI latches a "0" on the Ph _ det output of the D-type flip-flop. CKE rising edge increments the code to add another delay element 400 to the DCDL.

Referring to fig. 8C, the phase detector detects a lock condition when the CKI rising edge moves after the CKE rising edge. The rising edge of CKI latches a "1" on the Ph _ det output of the D-type flip-flop.

Fig. 9 is a timing diagram showing signals in the schematic diagram shown in fig. 7. The timing diagram shows the signal states in the schematic when the system is reset when it is detected that the phase detection window has been reached and a lock condition is detected (when the clock edges of CKE and CKI are aligned). Fig. 9 will be described in conjunction with fig. 3 and 7.

At time 900, the system is reset and the reset signal is switched to a logic "1". The reset signal is coupled to the R inputs of flip-flops 700, 702 to reset the flip-flops. The Ph _ det signal is reset to a logic "1". The Q outputs (LC1, SW) of both flip-flops are reset to "0". The internal clock signal CKI has the same frequency as the external clock signal CKE, but there is an initial phase difference due to the delay through the clock tree buffer 328.

At time 902, after the system is reset, the reset signal is changed to a logic "0". Initially, delay is added to CKE through DCDL and not through VCDL. The rising edge of cki occurs later than the rising edge of CKE due to the delay through the clock tree buffer 328 (fig. 3) and the delay through the DCDL. The SW signal set to logic "0" allows CKE to increment the code stored in counter 308 (fig. 3). When the code stored in counter 308 (fig. 3) is incremented by CKE (rising or falling edge), more delay elements 400 (fig. 4A-4B) are added to DCDL 306 (fig. 3) to further delay CKE. The delay between CKE and CKI increases until the phase detection window is reached.

At time 904, phase detector 320 (fig. 3) detects that the phase detection window has been entered. The Ph _ det signal output from the phase detector changes state from a logic "1" to a logic "0" indicating that the phase detector 320 has detected a rising edge of the CKI signal after a falling edge of CKE. The SR flip-flop 600 is set and LC1 at the Q output is set to "1". The phase difference between CKE and CKI decreases with increasing DCDL delay in successive clock cycles.

At time 906, phase detector 320 (fig. 3) detects that sufficient delay has been added by the DCDL such that a rising edge of CKI occurs after a rising edge of CKE. The Ph-det output of phase detector 320 changes to return to a logic "1". LC2 at the output of and gate 706 changes to a logic "1", SR flip-flop 702 is set, and the Q output (SW) changes to a logic "1". Further changes in the Ph-det signal do not affect the state of LC1 and SW. The SW signal set to "1" further inhibits the incrementing of counter 308.

During normal DLL operation, the delay adjustment of the clock path to compensate for offsets and condition changes covers a narrower range of the wide delay range. Thus, after lock has been achieved, the DCDL enables the delay elements to provide coarse phase adjustment in the delay locked loop. The DLL delay is varied by the VCDL over a smaller delay range to provide fine phase adjustment in the delay locked loop. Monitoring for a smaller delay range during normal operation provides greater stability and reduces the sensitivity of the control voltage node. In the event that the DLL loses a lock condition that exceeds the compensation capability of the VCDL, the system resets to the initial condition and the DCDL is reactivated to bring the external and internal clocks within the phase detection window.

The invention has been described for embodiments with a single fixed bias voltage level. In alternative embodiments, more than one fixed bias voltage level or more than one fixed bias voltage pair level may be used to provide a more compact DLL that is less sensitive to noise. This allows for modification of the wide delay range to reduce the number of DCDL delay elements by selecting a fixed bias voltage level according to the frequency of the external clock. Reducing the number of DCDL delay elements reduces the sensitivity to noise. For example, in one embodiment, for a fixed bias voltage with 0.6VDD, 15 DCDL delay elements are needed to provide the DCDL delay. When the fixed bias voltage is 0.7VDD, only 8 DCDL delay elements are needed to provide the DCDL delay. However, changing the delay range may result in a delay range that covers an unstable region, such as at point C in the graph shown in fig. 2.

The invention may be used in integrated circuits requiring high accuracy input/output data synchronization, e.g. in memories, microprocessors and Application Specific Integrated Circuits (ASICs).

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that: various changes in form and details may be made therein without departing from the scope as defined by the appended claims. For example, while the delay of the DCDL remains fixed over a short time, it may be allowed to be temporarily offset, e.g., to bring the VCDL close to its delay limit.

Claims (20)

1. A delay locked loop, comprising:

a digital delay circuit enabling the digital delay element to provide coarse phase adjustment during initialization in the delay locked loop; and

a counter included in the digital delay circuit configured to control a number of enabled digital delay elements, the counter further configured to have an initial value corresponding to a minimum delay of the digital delay circuit; and

an analog delay circuit that provides fine phase adjustment in the delay locked loop after coarse phase adjustment is completed,

wherein the analog delay circuit employs a variable voltage control signal during fine phase adjustment, and

wherein the analog delay circuit remains at a second fixed delay and receives a fixed voltage control signal while the digital delay circuit provides coarse phase adjustment; the digital delay circuit remains at a first fixed delay while the analog delay circuit provides fine phase adjustment.

2. The delay locked loop of claim 1, wherein the counter is an up counter.

3. The delay locked loop of claim 1 wherein the counter is controlled by an input clock signal.

4. The delay locked loop of claim 3, wherein the counter increments in response to a rising edge of the input clock signal.

5. The delay locked loop of claim 1, wherein the counter is implemented as a ripple counter.

6. The delay locked loop of claim 1, wherein the counter is reset to "0" when reset.

7. The delay locked loop of any one of claims 1 to 6 wherein a voltage controlled delay line in the analog delay circuit is in series with a digitally controlled delay line in the digital delay circuit.

8. The delay locked loop of any one of claims 1 to 6 wherein the digital delay circuit operates over a wide delay range.

9. The delay locked loop of claim 8 wherein the analog delay circuit operates over a small delay range within a wide delay range.

10. The delay locked loop of any one of claims 1 to 6, further comprising: a lock detector in the digital delay circuit detects completion of the coarse phase adjustment, freezes the fixed delay upon completion, and enables the fine phase adjustment.

11. The delay locked loop of any one of claims 1 to 6, wherein the counter is configured to: the counter is disabled upon detection of clock signal edge alignment.

12. The delay locked loop of claim 11 wherein one of the clock signals is an internal clock signal.

13. The delay locked loop of any one of claims 1 to 6, wherein the digital delay circuit is held at a fixed delay while performing fine phase adjustment in the delay locked loop after coarse phase adjustment is completed.

14. A method of performing phase adjustment in a delay locked loop, comprising the steps of:

initializing a counter to a value corresponding to a minimum delay of a digital delay circuit in a delay locked loop;

enabling digital delay elements in a digital delay circuit to provide coarse phase adjustment during initialization in a delay locked loop, wherein a number of enabled digital delay elements depends on an output of the counter; and

after the coarse phase adjustment is completed, a fine phase adjustment is provided using an analog delay circuit,

wherein the analog delay circuit employs a variable voltage control signal during fine phase adjustment, and

wherein the analog delay circuit remains at a second fixed delay and receives a fixed voltage control signal while the digital delay circuit provides coarse phase adjustment; the digital delay circuit remains at a first fixed delay while the analog delay circuit provides fine phase adjustment.

15. The method of claim 14, further comprising the steps of: incrementing the counter with an input clock signal received by the counter.

16. The method of claim 15, wherein the counter is incremented in response to a rising edge of an input clock signal.

17. The method of claim 14, wherein the counter is implemented as a ripple counter.

18. The method according to any one of claims 14 to 17, further comprising the step of: resetting the counter to "0," the resetting occurring prior to the step of enabling the digital delay element.

19. The method according to any one of claims 14 to 17, further comprising the step of:

detecting completion of coarse phase adjustment;

freezing the coarse phase adjustment upon completion; and

fine phase adjustment is enabled when frozen.

20. The method of any of claims 14 to 17, further comprising: after the coarse phase adjustment is completed, the digital delay circuit is held at a fixed delay during the provision of the fine phase adjustment.