HK1169521A - Initialization circuit for delay locked loop - Google Patents

Abstract

An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation, after reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line, after at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.

Description

Initialization circuit for delay locked loop

This application is a divisional application of original application 200480017535.4 (international application number PCT/CA2004/000936, international application date 2004, 6/23, entering chinese national phase date 2005, 12/23), and thus claims priority as follows:

US 60/482,260 submitted on 6/25/2003, and

US 10/647,664 filed on 8/25/2003.

Background

A Delay Locked Loop (DLL) with an adjustable delay line is used to synchronize a first clock signal with a second clock signal by delaying the first clock signal. The DLL includes a phase detector that detects a phase difference between the first clock signal and the second clock signal. Based on the detected phase difference, the DLL synchronizes the first clock signal to the external clock signal by adding an appropriate delay to the first clock signal until the second clock signal is in phase with the first clock signal.

Fig. 1 is a block diagram of a prior art DLL 100. The reference clock (CLK _ REF) is provided by buffering an externally provided Clock (CLK) by a clock buffer 101, which is coupled to the voltage controlled delay line 102 and the phase detector 104. The voltage controlled delay line 102 generates an output clock (CLK _ OUT) that is a delayed version of CLK-REF and is sent to various circuits within the device and also to the replica delay circuit 103. The replica delay circuit 103 provides a delay similar to the delay of the transmission delay through the buffer 101 and the line. The replication delay is well known to those skilled in the art. See commonly owned U.S. Pat. No. 5,796,673 by Foss et al for further explanation of replication delay. The feedback clock signal CLK _ FB output from the replica delay circuit 103 is coupled to the phase detector 104. Other prior art DLLs utilize digital delay lines or tapped (tapped) delay lines. These DLLs are described in commonly owned U.S. patent nos. 5,796,673 and 6,087,868.

The phase detector 104 generates phase control signals (UP, DOWN) that depend on the phase difference between CLK _ REF and CLK _ FB. The DOWN signal is set to a logic '1' on each CLK _ REF rising edge and the UP signal is set to a logic '1' on each CLK _ FB rising edge. When the second rising edge of these two signals is received, both the UP and DOWN signals are reset to logic '0'. Thus, when a rising edge of CLK _ REF is detected before a rising edge of CLK _ FB, the DOWN signal transitions to logic '0' to reduce the delay in the Voltage Controlled Delay Line (VCDL)102 until the next rising edge of CLK _ FB is detected. Alternatively, if a CLK _ FB rising edge is detected before a CLK _ REF rising edge, the UP signal is asserted (logic '1') to increase the delay until the next rising edge of CLK _ REF is detected.

The phase control signals (UP/DOWN) of the phase detector 104 are combined by the charge pump 105 and loop filter 106 to provide a variable bias voltage V for the VCDL 110_CTRL110. Bias voltage V_CTRLThe delay is selected to add to CLK _ REF through VCDL 102 to synchronize CLK _ FB and CLK _ REF.

The phase detector 100 may be level sensitive or edge triggered. Typically, edge triggered phase detectors are used because level sensitive phase detectors are susceptible to false locks. However, the clocks are free running and it is not known which clock edge will occur first after reset. Thus, on the initial phase relationship between the input signals to the phase detector (i.e., on whether the rising edge of CLK _ REF or CLK _ FB occurs first after system reset or power up). When the delay should be decreased (increased), the UP (/ DOWN) signal may be triggered first, so that the DLL with edge triggered phase detector never reaches lock.

Fig. 2 is a schematic diagram of a prior art edge triggered phase detector 104. The phase detector 104 detects the phase difference between CLK _ REF and CLK _ FB and sets the UP, DOWN signals to logic '1' based on the phase difference to increase or decrease the delay. The phase detector 104 includes two rising edge triggered D-type flip-flops (DFFs) 201, 203 and a reset circuit 210. The input of each DFF201, 203 is coupled to V_DDAnd the respective asynchronous reset input of each DFF201, 203 is coupled to the output (RSTb) of the reset circuit 210. When the RESETb signal is a logic '0' or when both the UP and DOWN signals are logic '1', the reset circuit 210 generates a logic '0' on the RSTb signal to reset the DFFs 201, 203.

The clock input of each DFF is coupled to a respective one of the input signals (CLK _ REF, CLK _ FB), where the clock input of DEF 201 is coupled to CLK _ REF and the clock input of DEF 203 is coupled to CLK _ FB. The output of each DFF201, 203 is coupled to a respective UP/DOWN input of the charge pump 105 (fig. 1) to increase or decrease the delay of the VCDL 102 based on the detected phase difference between the clocks.

If the rising edge of CLK _ REF (transitioning from logic '0' to logic '1') is detected before the rising edge of CLK _ FB, the delay is decreased. For example, if the rising edge of CLK _ REF occurs before the rising edge of CLK _ FB, the DOWN signal is asserted (i.e., the output of DFF201 changes to logic '1') to reduce the delay. The charge pump and loop filter reduce the delay in the VCDL 102 when the DOWN signal is a logic '1'. The DOWN signal remains at logic '1' until the subsequent rising edge of CLK _ FB clocks DFF 203 and the UP signal on the output of DFF 203 transitions from logic '0' to logic '1'. When both the UP and DOWN signals are logic '1', the reset circuit 210 generates a logic '0' pulse on the RSTb signal. A logic '0' pulse on the RSTb signal coupled to the asynchronous reset inputs of DFFs 201, 203 resets DFFs 201, 203 and the UP and DOWN signals are reset to a logic '0'.

If the rising edge of CLK _ FB is detected before the rising edge of CLK _ REF, the delay increases and the UP signal transitions from a logic '0' to a logic '1'. When the UP signal is a logic '1', the charge pump and loop filter increase the delay through the delay line. The UP signal is held at logic '1' until the rising edge of CLK REF clocks DFF 203 and the DOWN signal transitions to logic '1'. When both the UP and DOWN signals are asserted (at a logic '1'), the reset circuit 210 generates a logic '0' on the RSTb signal and resets the DFFs 201, 203. After the DFFs 201, 203 are reset, the UP and DOWN signals on the DFF outputs are reset to logic '0'.

After power-up or system reset, the voltage controlled delay line is typically set to a minimum delay. If the rising edge of the CLK _ FER signal occurs before the rising edge of the CLK _ FB signal after reset or power up, the phase detector 104 sets the DOWN signal to a logic '1' to reduce the delay. However, the delay is already at the minimum allowed. Thus, all subsequent phase detector cycles will continuously try to reduce the DLL delay and the DLL will never reach lock.

FIG. 3 is a timing diagram illustrating the problem of the clock edge adjustment sequence after reset. The problem of achieving lock occurs when the rising edge of CLK _ REF occurs before the rising edge of CLK _ FB. In the example shown, the rising edge of CLK _ REF and the falling edge of CLK _ FB occur simultaneously. However, the phase difference is variable, and the two rising edges may occur exactly at the same time. Fig. 3 is described in conjunction with the circuit shown in fig. 2. During reset, the RESETb signal remains at logic '0' and the delay in the voltage controlled delay line is set to the minimum delay (one unit of delay cell). Also, since DFFs 201, 203 are held reset by a logic '0' on the RESETb signal, both signals UP and DOWN are held at a logic '0'.

At time 200, the RESETb signal transitions from a logic '0' to a logic '1'. As shown, after reset, a rising edge of CLK _ REF occurs, followed by a rising edge of CLK _ FB.

At time 202, the first rising edge on the CLK _ REF signal (from logic '0' to logic '1') sets DFF201, and the DOWN signal (output of DFF 201) is set to logic '1'. When the DOWN signal is a logic '1', the delay in the delay line is reduced. However, the DLL delay has been set at a minimum value when RESETb is logic '0'. Therefore, a logic '1' on the DOWN signal has no effect on the delay of the VCDL.

At time 204, the detected rising edge on the CLK _ FB signal sets DFF 203, resulting in the UP signal (output of DFF 203) being set to logic '1'. When both the UP signal and the DOWN signal are logic '1', the reset circuit 210 generates a logic '0' pulse on the RSTb signal to reset the DFFs 201, 203 and reset the UP and DOWN signals to logic '0' at time 206.

At time 208, this sequence repeats starting with the next rising edge of CLK _ REF and continues on each subsequent rising edge of CLK _ REF and CLK _ FB. The delay remains at a minimum delay and, therefore, the DLL never reaches lock.

Disclosure of Invention

An initialization circuit in a delay locked loop is proposed that ensures proper sequencing of the clock signals to the phase detector after reset. The delay locked loop includes a delay circuit that provides a delay to a reference clock to generate a feedback clock. The delay circuit has a delay range. A phase detector in the delay locked loop compares the phases of the reference clock and the feedback clock to change the delay of the delay circuit. The initialization circuit ensures that the phase detector initially changes delay in a direction away from the first end of the delay range after receiving one of the reference clock and the feedback clock after reset, and that the phase detector is capable of changing delay in the opposite direction toward the first end only after receiving one of the reference clock and the feedback clock and subsequently the other of the reference clock and the feedback clock.

The first end of the delay range is the smallest delay and the delay increases in a direction away from the first end and decreases in an opposite direction toward the first end. The initialization circuit increases the delay after receiving the reference clock and can decrease the delay only after receiving the reference clock followed by the feedback clock. The initialization circuit may include a first latch and a second latch, wherein an input of the second latch is coupled to an output of the first latch. The first latch is responsive to the reference clock and detects a first edge of the reference clock to begin changing the delay in a direction away from the first end. The second latch is responsive to the feedback clock and detects an edge of the feedback clock to begin changing the delay in the opposite direction after the first edge of the reference clock has been detected by the first latch.

In an alternative embodiment, more delay may be added to allow the clock to stabilize by adding two latches to the initialization circuit. An input of the third latch is coupled to an output of the first latch and an input of the fourth latch is coupled to an output of the third latch. The third latch detects a next edge of the reference clock to delay enabling of the phase detection circuit in the first direction by at least one reference clock cycle. The fourth latch detects the next edge of the feedback clock and thereby delays the enabling of the adjustment of the phase detector in the other direction by at least one feedback clock cycle.

The first edge of the reference clock may be a rising edge and the edge of the feedback clock is a rising edge.

In an alternative embodiment, the initialization circuit includes a first latch and a second latch. The first latch is responsive to the feedback clock and detects a first edge of the feedback clock to begin changing the delay in a direction away from the first end. The second latch is responsive to the reference clock, and detects an edge of the reference clock after the first edge of the feedback clock has been detected by the first latch, thereby initiating a change in delay in the opposite direction. The input of the second latch is coupled to the output of the first latch.

The phase detector may include a latch responsive to a reference clock to generate the first phase control signal and another latch responsive to a feedback clock to generate the second phase control signal.

Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIG. 1 is a block diagram of a typical prior art Delay Locked Loop (DLL);

fig. 2 is a schematic diagram of a typical prior art phase detector;

FIG. 3 is a timing diagram illustrating the clock edge ordering problem after reset;

fig. 4 is a schematic diagram of an edge triggered phase detection circuit including a phase detector initialization circuit in accordance with the principles of the present invention;

FIG. 5 is a circuit diagram of an embodiment of the reset circuit shown in FIG. 4;

FIG. 6 is a timing diagram illustrating the operation of the circuit shown in FIGS. 4 and 5;

FIG. 7 is a timing diagram illustrating the operation of the circuit shown in FIG. 4 when the rising edge of the feedback clock precedes the rising edge of the reference clock after reset;

fig. 8 is a schematic diagram of an alternative embodiment of the phase detector circuit shown in fig. 4 for use in a DLL in which the delay is reset to a maximum value at the time of reset;

fig. 9 is a schematic diagram of an alternative embodiment of a phase detector initialization circuit;

fig. 10 is yet another embodiment of a phase detector initialization circuit; and

fig. 11 is a timing diagram illustrating the operation of the circuit of fig. 9 when the rising edge of the reference clock precedes the rising edge of the feedback clock.

Detailed Description

The following is a description of preferred embodiments of the invention.

Fig. 4 is a schematic diagram of an edge triggered phase detection circuit 400 including a phase detector initialization circuit 410 in accordance with the principles of the present invention. The phase detection circuit 400 replaces the phase detector 104 of fig. 1 to provide a new DLL. The phase detection circuit 400 includes a phase detector 412 that detects a phase difference between a reference clock (CLK _ REF) signal and a feedback clock (CLK _ FB) signal. The outputs (UP, DOWN) of the phase detector 412 are coupled to respective UP/DOWN inputs of a charge pump described in connection with the phase detector 104 shown in fig. 1 to increase or decrease the delay of the reference clock based on the detected phase difference between the clocks.

The delay may range from a minimum value to a maximum value. In voltage controlled delay lines, the control voltage has a range of allowed values. One end of the range corresponds to a minimum delay value of the VCDL, and the other end of the range corresponds to a maximum delay value of the VCDL. The operation of the VCDL is readily understood by those skilled in the art and thus will not be discussed further. Other DLLs that use digital delay lines have a minimum delay value that is generally equal to one unit delay in the digital delay line and a maximum delay value that is generally equal to multiple unit delays in the digital delay line. In the illustrated embodiment, the delay of the DLL is reset to a minimum value at reset. The phase detector initialization circuit 410, which is coupled to the phase detector 412 on nodes a and B, ensures the correct order of detection of the clock edges after reset.

To ensure proper sequencing, the phase detector initialization circuit 410 disables the operation of the phase detector 412 until after the first rising edge of clkref has been detected after reset. After the phase detector initialization circuit 410 detects the first rising edge of clkref, the state of the phase detector 412 is set to allow for an increase in DLL delay. The phase detector initialization circuit 410 further delays the delay reduction enabled by the phase detector 412 until the next CLK _ FB rising edge to ensure that the delay is always increased after a system or power-on reset even when there is no initial phase difference between the clocks. After the initial increase in delay, the phase detector 412 operates as the prior art phase detector described in fig. 2 and 3. By first detecting the rising edge of CLK _ REF after reset and delaying the detection of the first rising edge of CLK _ FB before initiating phase detection, the delay always increases after reset. By always automatically increasing the delay after reset, the unlocked condition of the prior art phase detector described in connection with fig. 2 and 3 will not be encountered.

The phase detector initialization circuit 410 includes two DFFs 404, 403. DFF 404 detects the first rising edge of CLK REF after reset and increases the delay by setting node a to logic '1'. DFF 403 delays the process of reducing the delay by holding a logic '0' at node B until the next rising edge of CLK _ FB occurs.

The phase detection circuit 402 includes two DFFs 401, 402 and a reset circuit 416. The output of DFF 404 (node a) is coupled to the D input of DFF 402 and the output of DFF 403 (node B) is coupled to the D input of DFF 401. The respective asynchronous reset input of each DFF401, 402 is coupled to the output (RSTb) of the reset circuit 416. The RSTb signal is set to logic '0' during reset (the RESETb signal remains at logic '0', or both the UP and DOWN signals are at logic '1') to reset the DFFs 401, 402.

The clock input of each DFF401, 402 is coupled to a respective one of the input clock signals (CLK _ REF, CLK _ FB), with the clock input of DFF401 coupled to CLK _ REF and the clock input of DFF 402 coupled to CLK _ FB. The output of each DFF401, 402 is coupled to a respective UP/DOWN input of the charge pump to increase or decrease the delay based on the detected phase difference between the clocks.

Fig. 5 is a circuit diagram of an embodiment of the reset circuit 416 shown in fig. 4. The reset circuit 416 includes a plurality of INVERTERs 215, 213, 212, 217, a NAND gate 216, AND an AND-OR-INVERTER 211. Table 1 below shows a truth table describing the operation of the reset circuit.

TABLE 1

During reset, the RESETb signal is set to logic '0' and the RSTb signal is set to logic '0' at the input of inverter 217. A logic '1' on the output of INVERTER 217 coupled to one input of AND-OR-INVERTER211 results in a logic '0' on the RSTb signal.

When both the UP and DOWN outputs of the phase detector circuit 412 transition to a logic '1', the RSTb signal is set to a logic '0' for a length of time equal to the propagation delay through the inverters 212, 213, 214. Prior to the DOWN and UP signals being converted to a logic '1' at the inputs of NAND gate 216, the output of inverter 212 is a logic '1'. When the inputs of NAND gate 216 are all logic '1', the output of NAND gate 216 transitions to logic '0'. A logic '0' at the input of INVERTER 215 results in a logic '1' at the output of INVERTER 215 coupled to the input of AND-OR-INVERTER 211. The RSTb signal transitions to a logic '0' when the inputs of AND-OR-INVERTER211 are all logic '1'. A logic "1" at the input of INVERTER 214 propagates through INVERTERs 213, 212 resulting in the RSTb signal transitioning back to a logic '1' after a logic '0' at the input of AND-OR-INVERTER211 coupled to the output of INVERTER 212. This results in a logic '0' pulse on the RSTb signal.

The operation of the circuits shown in fig. 4 and 5 is described in conjunction with the timing diagrams shown in fig. 6 and 7. Fig. 6 illustrates the case when the rising edge of the reference clock precedes the rising edge of the feedback clock after reset, and fig. 7 illustrates the case when the rising edge of the feedback clock precedes the rising edge of the reference clock after reset.

Fig. 6 is a timing diagram illustrating the operation of the circuit shown in fig. 4 and 5.

The outputs of DFFs 403, 404 are coupled to respective D-inputs of DFFs 401, 402 at nodes B and a. Prior to time 500 in fig. 6, during reset, the RESETb signal remains at logic '0' and the delay in the voltage controlled delay line is set to a minimum delay. In a wide frequency range DLL, the minimum delay of the delay line may be larger than the CLK _ REF period. When the RESETb and RSTb signals are logic '0' and logic '0' on the respective D-inputs of DFFs 401, 402, 403, the rising edge on the CLK _ FB or CLK _ REF signal has no effect on the output signals (UP, DOWN).

The RSTb is coupled to respective asynchronous reset inputs of DFFs 401, 402 and the RESETb is coupled to respective asynchronous reset inputs of DFFs 403, 404. Nodes a and B remain at logic '0' signals because DFFs 403, 404 are held in reset by the RESETb signal. Also, the UP and DOWN signals on the outputs of DFFs 401, 402 remain at logic '0' because the RSTb signal output by reset circuit 410 remains at logic '0' while RESETb remains at logic '0', as depicted in fig. 5.

At the end of the reset period, at time 500, the RESETb signal transitions to a logic '1', which allows the DFFs 404, 403 to transition states. After reset, the first rising edge of CLK _ REF (transition from logic '0' to logic '1') occurs before the first rising edge of the CLK _ FB signal.

At time 502, the first rising edge of the CLK _ REF signal sets DFF 404, and the signal on node A (the output of DFF 404) transitions from logic '0' to logic '1'. A logic '1' on node a allows DFF 402 to set the UP signal to increase the delay after detecting the next rising edge of CLK _ FB.

At time 504, the first rising edge of CLK _ FB sets DFF 402 and the UP signal (output of DFF 402) transitions from logic '0' to logic '1'. The first rising edge of CLK _ FB also sets DFF 403 and the signal on node B (output of DFF 403) transitions from logic '0' to logic '1', which allows the delay to be reduced on the next rising edge of CLK _ REF. When the UP signal is logic '1', the delay is increased.

The DFF 403 in the phase detector initialization circuit 410 ensures that the delay always increases after reset even if there is no initial phase difference between the signals (CLK _ REF and CLK _ FB). The time that the UP signal remains at logic '1' before the DOWN signal is set to logic '1' by DFF401 depends on the initial phase difference between CLK _ FB and CLK _ REF.

At time 505, when the logic on the D-input of DFF401 is a '1', the rising edge of CLK _ REF causes the output of DFF401 to be a logic '1'. When the outputs (DOWN, UP) of DFFs 401, 402 are both logic '1', the reset circuit 416 generates a logic '0' pulse on the RSTb signal to reset the DFFs 401, 402. At time 506, DFFs 401, 402 are both reset and the outputs (DOWN, UP) are both reset to logic '0'. DFFs 403, 404 are not reset. In effect, they remain in the set state (logic '1' on the respective outputs at node A, B) until the next reset is detected.

Thus, after an initial increase in delay, the phase detector 412 controls the generation of the phase control signals (UP/DOWN) to further increase or decrease the delay until lock is achieved. The phase detector 412 continues to increase the delay by generating additional UP signal transitions as shown at times 508 and 510 until the DLL is in a locked state at time 512. The phase detector 412 continuously monitors the phase difference between the CLK _ REF signal and the CLK _ FB signal and adjusts the delay by setting the UP/DOWN signals appropriately to achieve lock.

Fig. 7 is a timing diagram illustrating the operation of the circuit shown in fig. 4 when the first rising edge of the feedback clock occurs before the first rising edge of the reference clock after reset.

At time 700, the RESETb signal transitions from a logic '0' to a logic '1'. At time 701, the rising edge of CLK _ FB is ignored by DFFs 403, 402 because DFF 404 has not detected the first rising edge of CLK _ REF.

At time 702, the first rising edge on CLK _ REF sets DFF 404 and node A transitions from logic '0' to logic '1'.

At time 703, the next rising edge of the CLK _ FB signal sets DFF 402 and the UP signal (output of DFF 402) transitions from logic '0' to logic '1'. This rising edge of the CLK _ FB signal also sets DFF 403 and node B transitions from logic '0' to logic '1'.

At time 704, when node B (the D-input of DFF 401) has a logic '1', the rising edge of CLK _ REF makes a logic '1' on the output of DFF 401. When the outputs (DOWN, UP) of the DFFs 401, 402 are both logic '1', the reset circuit 416 generates a logic '0' pulse on the RSTb signal to reset the DFFs 401, 402, and the outputs (DOWN, UP) are set to logic '0'.

After the UP signal first transitions to a logic '1' to initially increase the delay, the phase detector 412 controls the generation of the output signal (UP/DOWN) to further increase or decrease the delay until lock is achieved. The phase detection circuit continues to increase the delay by setting the UP signal to a logic '1' as shown at time 705.

Fig. 8 is a schematic diagram of an alternative embodiment of the phase detection circuit 800 of fig. 4 for use in a DLL in which the delay is reset to a maximum value at reset. A phase detector initialization circuit 806 coupled to the phase detector 412 at nodes a and B ensures the correct order of clock edge detection after reset.

To ensure the correct sequence, the phase detector initialization circuit 806 disables the operation of the phase detector 412 until after the first rising edge of the CLK FB has been detected after reset. After the phase detector initialization circuit 806 detects the first rising edge of the CLK FB, the state of the phase detector 412 is set to allow the DLL delay to be reduced. The phase detector initialization circuit 806 further delays the increase in delay enabled by the phase detector 412 until the next CLK REF rising edge to ensure that the delay is always reduced after a system or power-on reset, even if there is no initial phase difference between the clocks. After the initial reduction in delay, the phase detector 412 operates as described for the prior art phase detector in fig. 2 and 3. By first detecting the rising edge of CLK _ FB after reset and delaying the detection of the first rising edge of CLK _ REF before enabling phase detection, the delay is always reduced after reset. By always automatically reducing the delay after reset, the unlocked condition of the prior art phase detector described in connection with fig. 2 and 3 will not be encountered.

The phase detector initialization circuit 806 includes two DFFs 802, 804. DFF 802 detects the first rising edge of CLK _ FB after reset and reduces the delay by setting node a to logic '1'. DFF 804 increases the delay by keeping node B at logic '0' until after the next rising edge of clkref occurs.

The phase detection circuit 402 includes two DFFs 401, 402 and a reset circuit 416. The output of DFF 802 (node a) is coupled to the D input of DFF401 and the output of DFF 804 (node B) is coupled to the D input of DFF 402. The respective asynchronous reset input of each DFF401, 402 is coupled to the output (RSTb) of the reset circuit 416. The RSTb signal is set to logic '0' during reset (the RESETb signal remains at logic '0', or both the UP and DOWN signals are at logic '1') to reset the DFFs 401, 402.

The clock input of each DFF401, 402 is coupled to a respective one of the input clock signals (CLK _ REF, CLK _ FB), wherein the clock input of DFF401 is coupled to CLK _ REF and the clock input of DFF 402 is coupled to CLK _ FB. The output of each DFF401, 402 is coupled to a respective UP/DOWN input of the charge pump to increase or decrease the delay based on the detected phase difference between the clocks.

Fig. 9 is a schematic diagram of an alternative embodiment of a phase detector initialization circuit. In this embodiment, the signals coupled to the data input and asynchronous reset input of DFF 604 differ from the embodiment shown in fig. 4, where DFF 604 detects the first rising edge of CLK REF after reset. The data input of DFF 604 is coupled to the RESETb signal instead of Vdd and the asynchronous reset input is coupled to Vdd instead of RESETb. When RESETb is a logic '0', DFF 604 is reset after the first rising edge of CLK _ REF. After RESETb transitions from logic '0' to logic '1', DFF 604 is set (with logic '1' on node a) after the first rising edge of CLK _ REF. After DFF 604 detects the first rising edge of CLK REF, the operation of the circuit is the same as described for the embodiment shown in fig. 4.

Fig. 10 is yet another embodiment of a phase detector initialization circuit. To allow the clock to stabilize after reset or power up, additional DFFs can be added to the phase detector initialization circuit described in fig. 4 such that more than one rising edge is detected on CLK REF before the phase detector circuit is enabled. Additional DFFs 706 are coupled to DFF 704. CLK _ REF is also coupled to a clock input of DFF 706. Thus, the transition of node A from logic '0' to logic '1' occurs after the second rising edge of CLK _ REF detected by DFF 704. The additional delay (one CLK REF period) allows the clocks (CLK REF and CLK FB) to stabilize after the circuit has been reset. Those skilled in the art will recognize that any desired number of stages may be added to further increase the number of CLK REF rising edges detected before enabling the phase detection circuit.

A further DFF 705 is also coupled between DFF 705 and DFF 701. The clock input of DFF 705 is coupled to the CLK _ FB signal and the asynchronous reset input is coupled to the RESETb signal. The output of DFF 705 is coupled to the input of DFF 703. The additional DFF 705 delays the transition of the DOWN signal from logic '0' to logic '1', thereby increasing the time that the UP signal was initially set to logic '1' to increase the delay. Those skilled in the art will appreciate that any desired number of stages may be added to further increase the time that the UP signal remains at logic '1'.

Fig. 11 is a timing diagram illustrating the operation of the circuit of fig. 10. The outputs of DFFs 703, 704 are coupled to respective inputs of DFFs 401, 402 at nodes a and B. Prior to time 900, during reset, the RESETb signal remains at logic '0' and the delay is set at a minimum delay. When the RESETb signal and the RSTb signal are logic '0' at the respective D-inputs of DFFs 401, 402, 403, 704, 705, 706, the rising edge on the CLK _ FB signal or the CLK _ REF signal has no effect on the output signals (UP, DOWN).

At time 900, the RESETb signal transitions to a logic '1', allowing the DFF to transition states.

At time 901, the first rising edge of CLK _ REF sets DFF 706, and the output of DFF 706 transitions from logic '0' to logic '1'.

At time 902, the second rising edge of CLK _ REF sets DFF704 and node A (the output of DFF 404) transitions from logic '0' to logic '1'. A logic '1' on node a causes the delay through DFF 402 in phase detection circuit 412 to increase.

At time 903, the subsequent rising edge of the CLK _ FB signal sets DFF 402 and the UP signal (the output of DFF 402) transitions from a logic '0' to a logic '1'. The subsequent rising edge of the CLK _ FB signal also sets DFF 705.

At time 904, the next rising edge of the CLK _ FB signal sets DFF 703 and the signal at node B (the output of DFF 403) transitions from logic '0' to logic '1'. While the UP signal remains at logic '1', the delay increases.

At time 905, when the input of DFF401 is a logic '1', the next rising edge of CLK _ REF makes a logic '1' on the output of DFF 401. When the outputs (DOWN, UP) of the DFFs 401, 402 are both logic '1', the reset circuit 416 generates a logic '0' pulse on the RSTb signal to reset the DFFs 401, 402, and the outputs (DOWN, UP) are both set to logic '0'.

In an alternative embodiment, the delay line can be set to the maximum delay (total delay of all unit cells in the voltage controlled delay line) at reset and the phase detector can be configured to automatically reduce the delay. In addition, the invention has been described with rising edge triggered flip-flops, however falling edge triggered DFFs may also be utilized. Furthermore, the invention has been described using voltage controlled delay lines, however digital or tapped delay lines may also be used.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims (31)

1. A delay locked loop, comprising:

a delay circuit to provide a delay to a reference clock to generate a feedback clock, the delay circuit having a delay range;

the phase discriminator compares the phases of the reference clock and the feedback clock to change the delay of the delay circuit; and

an initialization circuit that, once the delay locked loop is reset,:

i) enabling the phase detector to initially vary the delay in a direction away from the first end of the delay range; and

ii) after a certain number of clock cycles, enabling a change of the delay in the opposite direction towards the first end.

2. The delay locked loop of claim 1, wherein the initialization circuit enables the delay to be changed in the opposite direction toward the first end after a predetermined number of clock cycles once the delay locked loop is reset.

3. The delay locked loop of claim 1 or 2, wherein the number of clock cycles is an integer number of clock cycles greater than zero.

4. The delay locked loop of claim 1 or 2, wherein the delay circuit comprises a voltage controlled delay line.

5. The delay locked loop of claim 1 or 2, wherein the delay circuit comprises a tapped delay line.

6. The delay locked loop of claim 1 or 2, wherein the delay circuit comprises a digital delay line.

7. The delay locked loop of claim 1 or 2, wherein the first end of the delay range is a minimum delay, increasing the delay away from the first end and decreasing the delay in an opposite direction towards the first end.

8. A delay locked loop as claimed in claim 1 or 2, wherein the phase detector only increases the delay when the phase detector initially changes the delay.

9. The delay locked loop of claim 1 or 2, wherein the initialization circuit comprises a first latch responsive to the reference clock and a second latch responsive to the feedback clock.

10. The delay locked loop of claim 9, wherein the first latch is configured to detect a first edge of the reference clock, and the second latch is configured to detect the feedback clock edge after the first latch detects the first edge of the reference clock.

11. The delay locked loop of claim 10, wherein an input of the second latch is coupled to an output of the first latch.

12. The delay locked loop of claim 10 wherein the first edge of the reference clock is a rising edge and the feedback clock edge is a rising edge.

13. The delay locked loop of claim 10 wherein the initialization circuit further comprises a third latch responsive to the reference clock and a fourth latch responsive to the feedback clock.

14. The delay locked loop of claim 13, wherein the third latch is configured to detect a next edge of the reference clock and the fourth latch is configured to detect a next edge of the feedback clock to delay initiation of the change in delay in the opposite direction by at least one feedback clock cycle.

15. The delay locked loop of claim 14, wherein an input of the third latch is coupled to an output of the first latch and an input of the fourth latch is coupled to an output of the third latch.

16. The delay locked loop of claim 1 or 2, wherein the phase detector comprises: a latch responsive to a reference clock for generating a first phase control signal; and another latch responsive to the feedback clock for generating a second phase control signal.

17. The delay locked loop of claim 1 or 2, further comprising a reset circuit that controls resetting of the delay locked loop in response to a reset signal, the initialization circuit being reset in response to the reset signal.

18. The delay locked loop of claim 1 or 2, further comprising a reset circuit that controls the resetting of the delay locked loop in response to a reset signal, the phase detector being reset in response to the reset signal.

19. The delay locked loop of claim 1 or 2, wherein the initialization circuit further comprises an input to receive a reset signal, and wherein the phase detector further comprises an input to receive the reset signal.

20. The delay locked loop of claim 1 or 2, wherein the reset signal is an active low signal.

21. An apparatus, comprising:

a first latch and a second latch; and

a circuit configured to enable first and second latches in response to a reset signal, the circuit comprising:

a plurality of first stages, each having a storage element clocked by a first clock signal, an output of the first stage being electrically connected to a first latch; and

a plurality of second stages, each second stage having a storage element clocked with a second clock signal, the second stages receiving an output of the first stage, the output of the second stages being electrically connected to a second latch.

22. The apparatus of claim 21, wherein the first stage enables the first latches after a delay corresponding to a number of the first stages in response to the reset signal.

23. The apparatus of claim 22, wherein the delay is at least the following duration: the first clock signal has a number of clock cycles corresponding to one less than the number of first stages.

24. The apparatus of claim 21, wherein the second stage enables the second latch after a delay corresponding to a number of the first stage and the second stage in response to the reset signal.

25. The apparatus of claim 24, wherein the delay is at least the following duration: 1) a number of clock cycles of the first clock signal corresponding to one less than the number of first stages, and 2) a number of clock cycles of the second clock signal corresponding to one less than the number of second stages.

26. The apparatus of claim 21, wherein the frequencies of the first and second clock signals are substantially equal.

27. The device of claim 21, wherein each storage element comprises a latch.

28. The apparatus of claim 27, wherein the latches in successive stages are electrically connected via respective outputs and respective inputs.

29. The apparatus of claim 21, wherein the first latch is clocked with the second clock signal and the second latch is clocked with the first clock signal.

30. The apparatus of claim 21, wherein the first latch generates the control signal in response to the second clock signal and the second latch generates the control signal in response to the first clock signal.

31. An apparatus, comprising:

a first latch and a second latch; and

a circuit configured to enable first and second latches in response to a reset signal, the circuit comprising:

a plurality of first stages, each first stage having a latch clocked by a reference clock signal, an output of the first stage being electrically connected to the first latch; and

a plurality of second stages, each second stage having a latch clocked by a feedback clock signal, the second stages receiving an output of the first stage, the output of the second stages being electrically connected to the second latch.