HK1166560A - Front-end module with compensating diplexer - Google Patents

Description

Front end module with compensating duplexer

Cross-reference to related patents:

this patent application claims priority from provisional patent application entitled "CONFIGURABLE AND SCALABLE RF FRONT-END Module" having provisional application date of 2010, 6/3/2010, provisional Serial number 61/351,284, in accordance with 35 USC § 119 (e), which is incorporated herein by reference.

Statement regarding federally sponsored research or development-not applicable

Reference to material submitted on optical disc is incorporated-not applicable.

Technical Field

The present invention relates to wireless communications, and more particularly, to wireless transceivers.

Background

Communication systems are known to support wireless and wired communication between wireless and/or wired communication devices. Such communication systems range from national and/or international cellular systems to the internet to point-to-point home wireless networks. Each type of communication system is constructed in accordance with one or more communication standards and operates accordingly. For example, a wireless communication system may operate in accordance with one or more standards including, but not limited to, IEEE802.11, bluetooth, Advanced Mobile Phone System (AMPS), digital AMPS, global system for mobile communications (GSM), Code Division Multiple Access (CDMA), Local Multipoint Distribution System (LMDS), Multichannel Multipoint Distribution System (MMDS), Radio Frequency Identification (RFID), enhanced data rates for GSM evolution (EDGE), General Packet Radio Service (GPRS), WCDMA, LTE (long term evolution), WiMAX (worldwide interoperability for microwave access), and/or variants thereof.

Depending on the type of wireless communication system, a wireless communication device (e.g., a cell phone, two-way radio, Personal Digital Assistant (PDA), Personal Computer (PC), laptop, home entertainment device, RFID reader, RFID tag, etc.) communicates directly or indirectly with other wireless communication devices. For direct communication (also referred to as point-to-point communication), the participating wireless communication devices tune their receivers and transmitters to the same frequency channel(s) (e.g., one of a plurality of Radio Frequency (RF) carriers of the wireless communication system or a particular RF frequency of some systems) and communicate on that frequency channel(s). For indirect wireless communication, each wireless communication device communicates directly with an associated base station (e.g., for cellular service) and/or an associated access point (e.g., for home or indoor wireless networks) over a designated frequency channel. To complete a communication connection between wireless communication devices, the associated base stations and/or associated access points communicate directly with each other through the system controller, through the public switched telephone network, through the internet, and/or through some other wide area network.

Each wireless communication device participating in wireless communication includes an embedded wireless transceiver (i.e., a receiver and a transmitter) or is connected to an associated wireless transceiver (e.g., a station for an indoor and/or in-building wireless communication network, an RF modem, etc.). As is well known, the receiver is connected to an antenna and comprises a low noise amplifier, one or more intermediate frequency stages, a filtering stage and a data recovery stage. The low noise amplifier receives the inbound RF signal through the antenna and then amplifies it. The one or more intermediate frequency stages mix the amplified RF signals with one or more local oscillations to convert the amplified RF signals to baseband signals or Intermediate Frequency (IF) signals. The filtering stage filters the baseband signal or IF signal to attenuate unwanted out-of-band signals, thereby producing a filtered signal. The data recovery stage recovers data from the filtered signal in accordance with a particular wireless communication standard.

As is well known, a transmitter includes a data modulation stage, one or more intermediate frequency stages, and a power amplifier. The data modulation stage converts the data to baseband signals according to a particular wireless communication standard. One or more intermediate frequency stages mix the baseband signal with one or more local oscillations to produce an RF signal. The power amplifier amplifies the RF signal and then transmits through the antenna.

To implement a wireless transceiver, a wireless communication device includes a plurality of Integrated Circuits (ICs) and a plurality of discrete components. Fig. 1 illustrates one embodiment of a wireless communication device supporting 2G and 3G handset protocols. As shown, the wireless communication device includes a baseband processing IC, a power management IC, a wireless transceiver IC, a transmit/receive (T/R) switch, an antenna, and a number of discrete components. Discrete components include Surface Acoustic Wave (SAW) filters, power amplifiers, duplexers, inductors, and capacitors. Such discrete components add to the cost of raw materials for wireless communication devices, but are required to meet the stringent performance requirements of 2G and 3G protocols.

As integrated circuit manufacturing processes evolve, wireless communication device manufacturers require wireless transceiver IC manufacturers to upgrade their ICs in accordance with the advances made in IC manufacturing. For example, as manufacturing processes change (e.g., smaller transistor sizes are used), wireless transceiver ICs are also redesigned for newer manufacturing processes. Redesigning the digital portion of an IC is a relatively simple process, as most digital circuits "shrink" with the IC manufacturing process. However, redesigning the analog portion is not a simple task, as most analog circuits (e.g., inductors, capacitors, etc.) are not "scaled down" with the IC process. As such, wireless transceiver IC manufacturers will strive to produce ICs for newer IC manufacturing processes.

Disclosure of Invention

The present invention is directed to the apparatus and method of operation further described in the following brief description of the drawings, detailed description of the invention, and claims.

According to an aspect of the invention, a front end module comprises:

a duplexer, the duplexer comprising:

a first winding;

a second winding;

a third winding;

first to fifth nodes, wherein:

the first node is for operatively connecting an antenna to the first winding;

the second node is operable to receive an outbound wireless signal and operatively connect the first winding to the second winding;

the third node operatively connects the second winding to a balancing network;

a fourth node is operably connected to output a first signal component corresponding to an inbound wireless signal from the third winding; and

a fifth node is operably connected to output a second signal component corresponding to an inbound wireless signal from the third winding,

wherein the first and second signal components are electrically isolated from the outbound wireless signal; and

a compensation module operatively connected to at least one of the first, second, and third windings and operable to compensate for electrical isolation between the first and second signals and the outbound wireless signal; and

a balancing network operable to establish an impedance that substantially matches the antenna impedance.

According to another aspect, a radio frequency front end comprises:

a power amplifier operably connected to amplify the upconverted signal to generate an outbound wireless signal;

a duplexer operatively connected to an antenna, wherein the duplexer operatively provides electrical isolation between the outbound wireless signals and the inbound wireless signals;

a balancing network operatively connected to the duplexer and operative to establish an impedance substantially matching the antenna impedance;

a low noise amplifier operably connected to amplify the inbound wireless signal, wherein the low noise amplifier includes a common mode isolation compensation circuit that compensates for attenuation of common mode isolation by parasitic capacitances of the duplexer.

According to another aspect, a radio frequency front end comprises:

a power amplifier operably connected to amplify the upconverted signal to generate an outbound wireless signal;

a duplexer operatively connected to an antenna, wherein the duplexer operatively provides electrical isolation between the outbound wireless signals and inbound wireless signals;

a balancing network operatively connected to the duplexer and operative to establish an impedance substantially matching the antenna impedance; and

a compensation module operable to compensate for attenuation of electrical isolation between the first and second signals and the outbound wireless signal caused by parasitic capacitance of the duplexer.

Preferably, the compensation module comprises:

a first compensation capacitor connected in parallel with a first parasitic capacitance of the duplexer; and

a second compensation capacitor connected in parallel with a second parasitic capacitance of the duplexer, wherein a sum of capacitances of the first compensation capacitor and the first parasitic capacitance is substantially equal to a sum of capacitances of the second compensation capacitor and the second parasitic capacitance.

Preferably, the front-end module further comprises:

a detection module operatively connected for detecting an imbalance between the first and second parasitic capacitances;

a processing module operatively connected to:

determining the capacitance of the first and second compensation capacitors based on the imbalance between the first and second parasitic capacitances;

generating a first capacitance setting value based on the determined capacitance of the first compensation capacitor; and

generating a second capacitance setting value based on the determined capacitance of the second compensation capacitor;

the first compensation capacitor comprises a first capacitor network that is set based on the first capacitance setpoint; and

the second compensation capacitor includes a second capacitor network that is set based on the second capacitance setpoint.

Other features and advantages of the present invention will become apparent from the following description and the accompanying drawings.

Drawings

Fig. 1 is a schematic block diagram of a prior art wireless communication device;

FIG. 2 is a schematic block diagram of one embodiment of a portable computing communication device in accordance with the present invention;

FIG. 3 is a schematic block diagram of another embodiment of a portable computing communication device in accordance with the present invention;

FIG. 4 is a schematic block diagram of another embodiment of a portable computing communication device in accordance with the present invention;

FIG. 5 is a schematic block diagram of another embodiment of a portable computing communication device in accordance with the present invention;

FIG. 6 is a schematic block diagram of an embodiment of portions of each of a Front End Module (FEM) and an SOC module, in accordance with the present invention;

FIG. 7 is a schematic block diagram of an embodiment of portions of each of a Front End Module (FEM) and a SOC module, in accordance with the present invention;

FIG. 8 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an LNA in accordance with the present invention;

FIG. 9 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and a SOC module in accordance with the present invention;

FIG. 10 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and a SOC module in accordance with the present invention;

FIG. 11 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and a SOC module in accordance with the present invention;

FIG. 12 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an SOC module, in accordance with the present invention;

FIG. 13 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and a SOC module in accordance with the present invention;

FIG. 14 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and a SOC module, in accordance with the present invention;

FIG. 15 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an SOC module, in accordance with the present invention;

FIG. 16 is a schematic block diagram of an embodiment of portions of each of a Front End Module (FEM) and an SOC module in a 2G TX mode in accordance with the present invention;

FIG. 17 is a schematic block diagram of an embodiment of portions of each of a Front End Module (FEM) and an SOC module in a 2G RX mode in accordance with the present invention;

FIG. 18 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and a SOC module, in accordance with the present invention;

FIG. 19 is a schematic block diagram of an embodiment of a small signal balancing network in accordance with the present invention;

FIG. 20 is a schematic block diagram of an embodiment of a large signal balancing network in accordance with the present invention;

FIG. 21 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an LNA in accordance with the present invention;

FIG. 22 is a schematic block diagram of an embodiment of an impedance according to the present invention;

FIG. 23 is a schematic block diagram of another embodiment of an impedance in accordance with the present invention;

FIG. 24 is a schematic block diagram of an embodiment of a balancing network in accordance with the present invention;

FIG. 25 is a schematic block diagram of another embodiment of a balancing network in accordance with the present invention;

FIG. 26 is a schematic block diagram of an embodiment of a clock generator for a timing balance network in accordance with the present invention;

FIG. 27 is a diagram of an embodiment of the operation of the balancing network of FIG. 25, in accordance with the present invention;

FIG. 28 is a schematic block diagram of another embodiment of a balancing network in accordance with the present invention;

FIG. 29 is a schematic block diagram of another embodiment of portions of each Front End Module (FEM) in accordance with the present invention;

FIG. 30 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an SOC module, in accordance with the present invention;

FIG. 31 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an SOC module, in accordance with the present invention;

FIG. 32 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an LNA in accordance with the present invention;

FIG. 33 is a schematic block diagram of an embodiment of an equivalent circuit of portions of each of a Front End Module (FEM) and an LNA in accordance with the present invention;

FIG. 34 is a schematic block diagram of an embodiment of a transformer balun (balun) in accordance with the present invention;

FIG. 35 is a diagram of an embodiment of an implementation of a transformer balun according to the present invention;

FIG. 36 is a diagram of another embodiment of an implementation of a transformer balun in accordance with the present invention;

FIG. 37 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an SOC module, in accordance with the present invention;

FIG. 38 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) and an SOC module in accordance with the present invention.

Detailed Description

Fig. 2 is a schematic block diagram of an embodiment of a portable computing communication device 10, the portable computing communication device 10 including a system on a chip (SOC) 12 and a Front End Module (FEM) 14. The portable computing communication device 10 may be any device that can be carried by a person, can be at least partially battery powered, includes a wireless transceiver (e.g., Radio Frequency (RF) and/or millimeter wave (MMW)) and executes one or more software applications. For example, the portable computing communication device 10 may be a cell phone, laptop, personal digital assistant, video game console, video game player, personal entertainment unit, tablet computer, or the like.

SOC 12 includes SAW-less receiver portion 18, SAW-less transmitter portion 20, baseband processing unit 22, processing module 24, and power management unit 26. The SAW-less receiver 18 includes a Receiver (RX) Radio Frequency (RF) to Intermediate Frequency (IF) section 28 and a Receiver (RX) IF to baseband (BB) section 30. The RX RF to IF section 28 also includes one or more frequency translated (translated) band pass filters (FTBPF) 32.

The processing module 24 and the baseband processing unit 22 may be a single processing device, separate processing devices, or multiple processing devices. Such a processing device may be a microprocessor, microcontroller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on hard coding of the circuitry and/or operational instructions. The processing module 24 and/or the baseband processing unit 22 may have associated memory and/or storage elements that may be a single memory device, multiple memory devices, and/or embedded circuitry of the processing module 24. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache, and/or any device that stores digital information. Note that if the processing module 24 and/or the baseband processing unit 22 includes more than one processing device, the processing devices may be centrally located (e.g., directly connected together via a wired and/or wireless bus structure) or may be distributed (e.g., via indirectly connected cloud computing via a local area network and/or a wide area network). It is further noted that when the processing module 24 and/or the baseband processing unit 22 implement one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory and/or memory elements storing the corresponding operational specifications may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. It is also noted that the memory elements store, and the processing module 24 and/or baseband processing unit 22 execute, hard coded and/or operational instructions corresponding to at least some of the steps and/or functions illustrated in one or more of the figures.

The Front End Module (FEM) 14 includes one or more of a plurality of Power Amplifiers (PAs) 34-36, a plurality of receiver-transmitter (RX-TX) isolation modules 38-40, a plurality of Antenna Tuning Units (ATUs) 42-44, and a band (FB) switch. Note that FEM 14 may include more than two paths of PAs 34-36, RX TX isolation modules 38-40, and ATUs 42-44 connected to FB switch 46. For example, FEM 14 may include one path for 2G (second generation) handset services, another path for 3G (third generation) handset services, and a third path for Wireless Local Area Network (WLAN) services. Of course, there are many other combined embodiments of paths within FEM 14 that support one or more wireless communication standards (e.g., IEEE802.11, bluetooth, global system for mobile communications (GSM), Code Division Multiple Access (CDMA), Radio Frequency Identification (RFID), enhanced data rates for GSM evolution (EDGE), General Packet Radio Service (GPRS), WCDMA, High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), LTE (long term evolution), WiMAX (worldwide interoperability for microwave access), and/or variations thereof).

In one embodiment of operation, the processing module 24 performs one or more functions requiring wireless transmission of data. In this example, the processing module 24 provides outbound data (e.g., voice, text, audio, video, images, etc.) to the baseband processing module 22, and the baseband processing module 22 converts the outbound data into one or more outbound symbol streams consistent with one or more wireless communication standards (e.g., GSM, CDMA, WCDMA, HSUPA, HSDPA, WiMAX, EDGE, GPRS, IEEE802.11, bluetooth, ZigBee, Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), IEEE 802.16, optimized data evolution (EV-DO), etc.). Such transformations include one or more of the following: scrambling, puncturing (puncturing), encoding, interleaving, constellation mapping, modulation, spreading, frequency hopping, beamforming, space-time block encoding, space-frequency block encoding, frequency-to-time domain conversion, and/or digital baseband to intermediate frequency conversion. Note that the processing module 24 converts outbound data into single outbound symbol streams for single-in single-out (SISO) communications and/or for multiple-in single-out (MISO) communications, and converts outbound data into multiple outbound symbol streams for single-in multiple-out (SIMO) communications and/or for multiple-in single-out (MIMO) communications.

The baseband processing unit 22 provides one or more outbound symbol streams to the SAW-less transmitter portion 20, and the SAW-less transmitter portion 20 converts the outbound symbol stream(s) into one or more outbound RF or MMW signals. SAW-less transceiver section 20 may include a direct conversion topology (e.g., direct conversion of a baseband or near baseband symbol stream to an RF signal) or a super-heterodyne topology (e.g., converting a baseband or near baseband symbol stream to an IF signal and then converting the IF signal to an RF signal).

For direct conversion, the SAW-less transmitter portion 20 may be based on a Cartesian-based topology, a polar-based topology, or a hybrid polar-Cartesian-based topology. In a Cartesian based topology, the SAW-less transmitter portion 20 wouldIn-phase and quadrature components (e.g., A, respectively) of one or more outbound symbol streams_I(t) cos (ω_BB(t) +φ_I(t)) and A_Q(t) cos (ω_BB(t) +φ_Q(t))) and the in-phase and quadrature components (e.g., cos (ω) respectively) of one or more transmit local oscillations (TX LO)_RF(t)) and sin (ω)_RF(t))) to produce a mixed signal. The mixed signals are combined and filtered to produce one or more outbound up-converted signals (e.g., A (t) cos (ω)_BB(t) +φ(t) + ω_RF(t))). A Power Amplification Driver (PAD) module amplifies the outbound up-converted signal(s) to produce pre-PA (power amplified) outbound RF signal(s).

In a phase pole based topology, the SAW-less transmitter portion 20 includes generating oscillations (e.g., cos (ω)_RF(t)) based on phase information (e.g., +/-delta phi phase shift) of the outbound symbol stream(s)]And/or phi t) [ phase modulation]But adjusted) oscillator. The resulting modulated oscillation (e.g., cos (ω)_RF(t) +/- Δ φ) or cos (ω)_RF(t) + t)) may be determined by amplitude information (e.g., a (t)) of the outbound symbol stream(s) (e.g., a (t)) [ amplitude modulation ]]) Is further conditioned to produce one or more upconverted signals (e.g., A (t) cos (ω)_RF(t) + φ (t)) or A (t) cos (. omega.) of_RF(t) +/- Δ φ). A Power Amplification Driver (PAD) module amplifies the outbound up-converted signal(s) to produce pre-PA (power amplified) outbound RF signal(s).

In a frequency pole based topology, SAW-less transmitter portion 20 includes generating oscillations (e.g., cos (ω)_RF(t)) based on frequency information (e.g., +/- Δ f [ frequency shift ]) of the outbound symbol stream(s)]And/or f (t) frequency modulation]But adjusted) oscillator. The resulting modulated oscillation (e.g., cos (ω)_RF(t) +/- Δ f) or cos (. omega.) of_RF(t) + f (t)) may be determined by the magnitude information of the outbound symbol stream(s) (e.g.,a (t) [ amplitude modulation ]]) Is further conditioned to produce one or more upconverted signals (e.g., A (t) cos (ω)_RF(t) + f (t)) or A (t) cos (. omega.) (t)_RF(t) +/- Δ f). A Power Amplification Driver (PAD) module amplifies the outbound up-converted signal(s) to produce pre-PA (power amplified) outbound RF signal(s).

In a hybrid polar-cartesian based topology, the SAW-less transmitter section 20 will send out phase information (e.g., cos (ω) for the outbound symbol stream(s)_BB(t) +/- Δ φ or cos (. omega.) of_BB(t) + φ t)) is separated from the magnitude information (e.g., A (t)). The SAW-less transmitter portion 20 combines the in-phase and quadrature components (e.g., cos (ω), respectively) of one or more outbound symbol streams_BB(t) +φ_I(t)) and cos (. omega.) of_BB(t) +φ_Q(t))) and the in-phase and quadrature components (e.g., cos (ω) respectively) of one or more transmit local oscillations (TX LO)_RF(t)) and sin (ω)_RF(t))) to produce a mixed signal. The mixed signals are combined and filtered to produce one or more normalized outbound converted signals (e.g., cos (ω)_BB(t) + φ(t) +ω_RF(t))). A Power Amplification Driver (PAD) module amplifies the normalized outbound upconverted signal(s) and adds magnitude information (e.g., a (t)) to the normalized outbound upconverted signal(s) to generate pre-PA (power amplified) outbound RF signal(s) (e.g., a (t) cos (ω) RF signal(s) (e.g., a (t)) RF signal(s)_RF(t)+ φ(t))）。

For the super-heterodyne topology, the SAW-less transmitter section 20 includes a baseband (BB) to Intermediate Frequency (IF) section and an IF to Radio Frequency (RF) section. The BB to IF section may be a polar-based topology, a cartesian-based topology, a polar-cartesian-based hybrid topology, or a hybrid stage for up-converting the outbound symbol stream(s). In the three cases above, the BB to IF stages generate the IF signal(s) (e.g., a (t) cos (ω)_RF(t) + phi (t))) and the IF to RF section includes a mixing stage, a filtering stage, and workA Power Amplifier Driver (PAD) to generate pre-PA outbound RF signal(s).

When the BB to IF section includes a mixing stage, the IF to RF section may have a polarity-based topology, a cartesian-based topology, or a polarity-cartesian-based mixed topology. In this example, the BB to IF segments will outbound symbol stream(s) (e.g., a (t) cos ((ω) co)_BB(t) + phi (t))) into an intermediate frequency symbol stream(s) (e.g., a (t) (omega (t))) (e.g., a (t)))_IF(t) + φ (t)). The IF-to-RF section converts the IF symbol stream(s) into pre-PA outbound RF signal(s).

The SAW-less transmitter portion 20 outputs pre-PA outbound RF signal(s) to power amplifier modules (PAs) 34-36 of the Front End Module (FEM) 14. The PAs 34-36 include one or more power amplifiers connected in series and/or parallel to the amplified pre-PA outbound RF signal(s) to generate the outbound RF signal(s). It should be noted that parameters of the PAs 34-36 (e.g., gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, settling time, overshoot, stability factor, etc.) may be adjusted based on received control signals from the baseband processing unit 22 and/or the processing module 24. For example, as transmit conditions change (e.g., channel response changes, distance between the TX and RX units changes, antenna properties change, etc.), the processing resources of SOC 12 (e.g., BB processing unit 22 and/or processing module 24) monitor the transmit conditions changes and adjust the properties of PAs 34-36 to optimize performance. Such determinations are typically not performed singularly; which may be done with reference to other parameters of the front end modules that may be adjusted (e.g., ATUs 42-44, RX-TX isolation modules 38-40) to optimize the transmission and reception of RF signals.

The RX-TX isolation modules 38-40 (which may include balanced networks and duplexers, circulators, transformer baluns, or other devices that provide isolation between the TX and RX signals using a common antenna) attenuate the outbound RF signal(s). The RX-TX isolation modules 38-40 may adjust the attenuation of the outbound RF signal(s) (i.e., the TX signal) based on control signals received from the baseband processing unit and/or processing module 24 of the SOC 12. For example, when transmit power is relatively low, RX-TX isolation modules 38-40 may be adjusted to reduce attenuation of the TX signal.

Antenna Tuning Units (ATUs) 42-44, if included, are tuned to provide a desired impedance that substantially matches the impedance of antenna 16. With tuning in, the ATUs 42-44 provide attenuated TX signals from the RX-TX isolation modules 38-40 to the antenna 16 for transmission. Note that ATUs 42-44 may be continuously or periodically adjusted to track changes in the impedance of antenna 16. For example, baseband processing unit 22 and/or processing module 24 may detect a change in the impedance of antenna 16 and provide a control signal to ATUs 42-44 based on the detected change such that it changes its impedance accordingly.

In this embodiment, the SAW-less transmitter 20 portion has two outputs: one for the first frequency band and the other for the second frequency band. The foregoing discussion has focused on the process of converting outbound data into outbound RF signals for a single frequency band (e.g., 850 MHz, 900 MHz, etc.). The process for converting outbound data to RF signals for other frequency bands (e.g., 1800 MHz, 1900 MHz, 2100 MHz, 2.4 GHz, 5 GHz, etc.) is similar. Note that with antenna 16, SAW-less transmitter 20 generates an outbound RF signal in one other frequency band. A band (FB) switch 46 of the FEM 14 connects the antenna 16 to the appropriate output of the SAW-less transmitter output path. FB switch 46 receives control information from baseband processing unit 22 and/or processing module 24 to select which path to connect to antenna 16.

The antenna 16 also receives one or more inbound RF signals, which are provided to one of the ATUs 42-44 via a Frequency Band (FB) switch 46. The ATUs 42-44 provide the inbound RF signal(s) to the RX-TX isolation modules 38-40, which route the signal(s) to the Receiver (RX) RF-to-IF section 28 of the SOC 12. The RX RF-to-IF section 28 converts the inbound RF signal(s) (e.g., A (t) cos (ω)_RF(t)+φ(t)) Convert to an inbound IF signal (e.g., A)_I(t) cos (ω_IF(t)+φ_I(t)) and A_Q(t) cos (ω_IF(t)+φ_Q(t))). Various embodiments of the RX RF to IF section 28 will be described in a number of subsequent figures.

The RX IF to BB stage 30 converts the inbound IF signal into one or more inbound symbol streams (e.g., A (t) cos ((ω) co_BB(t) + φ (t))). In this example, the RX IF to BB section 30 includes a mixing section and a combining section&And a filtering section. The mixing section mixes the inbound IF signal(s) with a second local oscillation (e.g., LO2= IF-BB, where BB may range from 0 Hz to several MHz) to produce I and Q mixed signals. Merging&The filtering segment combines (e.g., adds the mixed signal together-this includes the sum component and the difference component) and then filters the combined signal to substantially attenuate the sum component and pass the substantially un-attenuated difference component as the inbound symbol stream(s).

The baseband processing unit 22 converts the inbound symbol stream(s) into inbound data (e.g., voice, text, audio, video, images, etc.) according to one or more wireless communication standards (e.g., GSM, CDMA, WCDMA, HSUPA, HSDPA, WiMAX, EDGE, GPRS, IEEE802.11, bluetooth, ZigBee, Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), IEEE 802.16, optimized data evolution (EV-DO), etc.). Such conversion may include one or more of the following: digital intermediate frequency to baseband conversion, time-to-frequency domain conversion, space-time block decoding, space-frequency block decoding, demodulation, spread spectrum decoding, frequency hopping decoding, beamforming decoding, constellation demapping, deinterleaving, decoding, de-puncturing (deputying), and/or descrambling. Note that the processing module 24 converts a single inbound symbol stream into single inbound data for single-in single-out (SISO) communications and/or for multiple-in single-out (MISO) communications, and converts multiple inbound symbol streams into inbound data for single-in multiple-out (SIMO) communications and multiple-in single-out (MIMO) communications.

The power management unit 26 is integrated into the SOC 12 to perform a variety of functions. Such functions include monitoring power connections and battery loads, charging the battery when needed, controlling power to other components of the SOC 12, generating supply voltages, shutting down unneeded SOC modules, controlling sleep modes of the SOC modules, and/or providing real time clocks. To facilitate the power supply to generate the supply voltage, the power management unit 26 may include one or more switch mode voltage supplies and/or one or more linear regulators.

Such an apparatus with a portable computing communication device 10 reduces cost and discrete off-chip components (e.g., SAW filters, duplexers, inductors, and/or capacitors) and their functionality is integrated into a front-end module (FEM) 14, which front-end module 14 may be implemented on a single chip. In addition, SAW-less receiver architectures and SAW-less transmitter architectures facilitate the reduction of discrete off-chip components.

Fig. 3 is a schematic block diagram of another embodiment of a portable computing communication device 10, the portable computing communication device 10 including a system on a chip (SOC) 52, and a Front End Module (FEM) 50 of another embodiment. SOC 52 includes power management unit 26, SAW-less receiver portion 18, SAW-less transmitter portion 20, baseband processing unit 22, and may further include processing modules. The FEM 50 includes a plurality of power amplifier modules (PAs) 34-36, a plurality of RX-TX isolation modules 38-40, and at least one Antenna Tuning Unit (ATU) 54.

In this embodiment, the SOC 52 is operable to support two or more wireless communications (e.g., a cell phone call and WLAN communications and/or Bluetooth communications) simultaneously. In this example, the SAW-less transmitter 20 generates two (or more) different frequency band outbound RF signals in the manner discussed with reference to fig. 2 and/or with reference to one or more subsequent figures. A first one of the different frequency outbound RF signals is provided to one of the PAs 34-36 of the FEM 50 and the other outbound RF signals are provided to the other PAs 34-36. The functionality of each TX-RX isolation module 38-40 may refer to the description of fig. 2, and may refer to the description of one or more subsequent figures. The ATU 54, which is tuned based on the control signal from the SOC 52, provides both outbound RF signals to the antenna 16 for transmission.

The antenna 16 also receives two or more different frequency band inbound RF signals and provides them to the ATU 54. The ATU 54 may include a shunt for shunting two inbound RF signals and splitting an impedance matching circuit (e.g., one or more LC circuits) for each of the shunted signals; a transformer balun for splitting the signal and splitting the impedance matching circuit; or impedance matching circuits for both signals, which are provided to RX-TX isolation modules 38-40.

The RX-TX isolation modules 38-40 are associated with each frequency band such that each will pass inbound and outbound RF signals only within their respective frequency bands (e.g., 850-. As such, the first TX-RX isolation module 38-40 provides a first input of the SWA-less RX segment 18 to which the first band inbound RF signals are directed, and the second TX-RX isolation module 38-40 provides a second input of the SWA-less RX segment 18 to which the second band inbound RF signals are directed. The SAW-less RX segment 18 processes the inbound RF signal to generate the first inbound data and the second inbound data in the manner discussed with reference to fig. 2 and/or discussed with reference to one or more subsequent figures.

Fig. 4 is a schematic block diagram of another embodiment of a portable computing communication device including a system on a chip (SOC) 180 connected to a Front End Module (FEM) 182. SOC 180 includes a plurality of SAW-less receiver portions (only LNA and frequency conversion bandpass filter (FTBPF) of the receiver portion are shown), a plurality of SAW-less transmitter portions (only Power Amplification Driver (PAD) is shown), a processing module, a baseband processing module (not shown or included in the processing module), and a power management unit (not shown).

The FEM 182 includes a Low Band (LB) path, a High Band (HB) path, and a band switch (FB SW). The LB path includes a power amplifier module (PA), a low-band impedance stage (LB Z), a low-band low pass filter (LB LPF), a Switch (SW), a transmit-receive isolation module (TX-RX ISO) (e.g., a duplexer), a second Switch (SW), and an Antenna Tuning Unit (ATU). The HB path includes a power amplifier module (PA), a high-band impedance stage (HB Z), a high-band low pass filter (HB LPF), a Switch (SW), a transmit-receive isolation module (TX-RX ISO) (e.g., duplexer), a second Switch (SW), and an Antenna Tuning Unit (ATU). Note that the low-band paths can be used to support low-band GSM, EDGE, and/or WCDMA wireless communications, and the high-band paths can be used to support high-band GSM, EDGE, and/or WCDMA wireless communications.

The SOC 180 is used to output pre-PA outbound RF signals, and input inbound RF signals, as previously discussed and/or discussed with reference to one or more of the following figures. The FEM 182 receives the pre-PA outbound RF signals via the LB path or the HB path and amplifies them via the respective PA modules. The impedance stage (LB Z or HB Z) provides the desired load on the PA module output and is connected to a low pass filter (LB LPF or HP LPF). The LPF filters the outbound RF signals, which are provided to the TX-RX IS0 module or to the ATU depending on the configuration of the Switch (SW). If the switch connects the LPF to the TX-RX IS0 module, the TX-KX module attenuates the outbound RF signal before providing it to the ATU. The function of the ATU is as described previously and/or as will be discussed with reference to one or more of the following figures.

Note that there are no discrete elements between SOC 180 and FEM 182. In particular, portable computing communication devices do not require discrete SAW filters as are required in current handset devices. The programmability of one or more SAW-less receiver architectures, SAW-less transmitter architectures, and/or various components of the FEM 182 all contribute to the elimination of SAW filters and/or other conventional external discrete components.

Fig. 5 is a schematic block diagram of another embodiment of a portable computing communication device including a System On Chip (SOC) 190 connected to a Front End Module (FEM) 192. SOC 190 includes a plurality of SAW-less receiver sections (only LNA and frequency conversion bandpass filter (FTBPF) are shown), a plurality of SAW-less transmitter sections (only power amplification driver (PDA) is shown), a processing module, a baseband processing module (not shown or included in the processing module), and a power management unit (not shown).

The FEM 192 includes a Low Band (LB) path, a High Band (HB) path, and a band switch (FB SW). The LB path includes a power amplifier module (PA), a low-band impedance stage (LB Z), a Switch (SW), a low-band low pass filter (LB LPF), a transmit-receive isolation module (TX-RX ISO) (e.g., duplexer), a second Switch (SW), and an Antenna Tuning Unit (ATU). The HB path includes a power amplifier module (PA), a high-band impedance stage (HB Z), a Switch (SW), a high-band low pass filter (HB LPF), a transmit-receive isolation module (TX-RX ISO) (e.g., duplexer), a second Switch (SW), and an Antenna Tuning Unit (ATU). Note that the low-band paths can be used to support low-band GSM, EDGE, and/or WCDMA wireless communications, and the high-band paths can be used to support high-band GSM, EDGE, and/or WCDMA wireless communications.

In various embodiments of SOC 190, a band pass filter for frequency translation in the receiver portion of SOC 190 may adequately filter far-out blocks (far-out blocks) and filter image signals that have negligible impact on the desired signal. This reduces the dynamic range requirements of the analog-to-digital converter (ADC) of the receiver part (at the output of the baseband processing module or at the input of the RX BB to IF section). The super-heterodyne architecture of the receiver section is optimal for reducing power consumption and chip area compared to a comparable direction conversion receiver section.

Fig. 6 is a schematic block diagram of a front-end module 810 and a system-on-chip module 812. The front end module 810 includes a duplexer 816 and a tunable balancing network 818. The system-on-chip module 812 includes a detector module 820 and a processing module 822. Note that processing module 822, like any of the other processing modules discussed in this application, may be constructed as described with reference to processing module 24 of fig. 2.

In an embodiment of operation, the duplexer is connected to an antenna 826 that transceives inbound and outbound wireless signals 835 and 837. For example, the inbound and outbound wireless signals 835 and 837 may correspond to Radio Frequency (RF) signals generated according to one or more wireless communication protocols, examples of which have been provided above. As a particular embodiment, the outbound wireless signals 835 have a carrier frequency corresponding to a transmit frequency of the wireless communication protocol, and the inbound wireless signals 835 have a carrier frequency corresponding to a receive frequency band of the wireless indication protocol.

The duplexer 816 provides electrical isolation between the inbound wireless signal 837 and the outbound wireless signal 835. The duplexer 816 can be a frequency selective duplexer or an electrically balanced duplexer to provide isolation of 30 dB or greater between the inbound and outbound wireless signals 835 and 837.

The tunable balancing network 818 may be used to establish an impedance that substantially matches the impedance of the antenna based on the tuning signal 823. Generally, the energy (e.g., current and/or voltage) of the outbound wireless signal 835 is split into two paths. The first is to the antenna 826 and the second is to the tunable balancing network 818. If the two paths are substantially equal, the energy will be substantially equal, which effectively cancels the outbound wireless signal 835 that is connected as the inbound wireless signal 837 portion of the duplexer 816.

To maintain impedance balance between the tunable balancing network 818 and the antenna 826 with varying impedance, the detector module 820 monitors the electrical performance characteristics of the duplexer 816. For example, the detector module 820 monitors the common mode of the duplexer 816 to detect a common mode bias caused by an impedance imbalance between the antenna and the tunable balancing network 818. If a bias is detected, the detector module 820 generates an error signal. Note that other electrical performance characteristics include, but are not limited to, impedance mismatches within the duplexer, non-linearities of one or more components of the duplexer, and/or frequency-dependent element responses.

The processing module 822 for tuning the engine generates a tuning signal 823 based on the error signal. For example, the error signal may indicate that the impedance of the tunable balancing network 818 is less than the impedance of the antenna 826. In this example, the processing module generates a tuning signal 823 to increase the impedance of the tunable balancing network 818 to more closely match the impedance of the antenna. Note that this is a dynamic process since the impedance of the antenna changes based on environmental conditions (e.g., proximity to metallic objects, multipath fading, etc.).

Fig. 7 is a schematic block diagram of an embodiment of portions of each of a Front End Module (FEM) 810 and an SOC 812. The FEM 810 includes, in part, a power amplifier module (PA) 814, a duplexer 816, a balancing network 818, and a sensing circuit 817. The duplexer includes a transformer (or other structure, such as a frequency selective duplexer and/or an electrically balanced duplexer), and the balancing network 818 includes at least one of a tunable resistor-capacitor network, a tunable inductor-capacitor network, and a tunable resistor-inductor-capacitor network. Sensing circuitry 817 for sensing electrical performance characteristics of the duplexer includes a pair of resistors connected across the secondary winding of the transformer. Portions of SOC 812 include a peak detector 820, a tuning engine 822, and a low noise amplifier module (LNA). Alternatively, the peak detector 820 and/or the tuning engine 822 may be within the FEM 810.

In an embodiment of operation, PA 814 supplies the outbound RF signal to the center tap (tap) of the dual winding primary of transformer duplexer 816. The current of the outbound RF signal is divided proportionally between the two windings by the impedance difference between the antenna and the balancing network 816. If the impedance of the balancing network 818 substantially matches the impedance of the antenna, the current is divided equally between the two windings.

With the winding configuration as shown, their magnetic fields essentially cancel each other in the secondary winding if the currents of the primary windings are substantially matched. Thus, the secondary winding has a substantially attenuated representation of the outbound RF signal. For an inbound RF signal, two windings of the main winding generate a magnetic field associated with the inbound RF signal. In this example, the magnetic fields are superimposed, thereby producing twice the current in the secondary winding (assuming each winding has the same number of turns) as the primary winding. In this manner, the transformer amplifies the inbound RF signal.

If there is an imbalance between the impedance of the antenna and the impedance of the balancing network 818, an outbound RF signal current component will appear in the secondary winding (e.g., TX leakage). For example, assume that the current through the winding to the inductor is i_P1And the current through the winding to the balancing network 818 is i_P2. TX leakage can be expressed as i_P1 - i_P2. The resistor of the common mode sensing circuit senses TX leakage as an electrical performance characteristic of the duplexer. For example, the voltage at the resistor center node is equal to VS- (R)₁*2i_R + R₁*i_P2 – R₂*i_P1) Where VS is the voltage of the secondary winding, and 2i_RIs the current of the received inbound RF signal. Let R be₁=R₂And i_P1=i_P2The voltage at the center node is equal to 1/2 of VS. However, if i_P1Is not equal to i_P2The voltage at the center node of the resistor will deviate proportionally from 1/2 VS according to the difference. Note that the detector 820 outputs a voltage insensitive to blocking signals received by the antenna because the inputs of the detector are connected to the differential inputs of the LNA.

Detector 820 detects the difference in voltage at the resistor center node from 1/2 VS and provides an indication of the difference to processing block 822. The processing module 822 for tuning the engine analyzes the differences and generates control signals to adjust the impedance of the balancing network. For example, if i_P1Greater than i_P2Then the common mode voltage of the sensing circuit (e.g., the center node of the resistor) will be greater than 1/2 VS, which indicates that the impedance of the balancing network 818 is too high. As such, the processing module 822 generates a tuning signal 823 that reduces the impedance of the balancing network 818. As another example, if i_P1Is less than i_P2Then the common mode voltage of the sensing circuit will be less than 1/2 VS, which indicates that the impedance of the balancing network 818 is too low. As such, the processing module 822 generates a tuning signal 823 that increases the impedance of the balancing network 818.

The processing module 822 may analyze the common mode voltage deviation, determine a desired impedance of the balancing network 818, and generate a tuning signal accordingly. Alternatively, the processing module 822 may iteratively generate tuning signals that adjust the impedance of the balancing network 818 in steps until the desired impedance is reached. In either approach, the processing module 822 operates to keep the impedance of the balancing network 818 substantially matched to the impedance of the antenna (which varies over time, usage, and/or environmental conditions) to minimize TX leakage.

FIG. 8 is a schematic block diagram of another embodiment of portions of each of the front end module (FEM 960) and SOC 962. Portions of FEM 960 include a power amplifier module (PA) 814, a duplexer 816, a balancing network 818, and a sensing circuit 817. The duplexer 816 includes a transformer (or other structure, such as a frequency selective duplexer and/or an electrically balanced duplexer). Sensing circuit 817 includes a pair of resistors connected in the secondary winding of the transformer. The portion of SOC 962 includes a peak detector 974, a processing module 976 (which is used to tune the engine), and a single-ended low noise amplifier module (LNA 972). Alternatively, the peak detector 974 and/or the tuning engine may be within the FEM 960.

As discussed with reference to fig. 7, the circuit compensates for TX leakage. To further reduce common mode issues with respect to processing inbound wireless signals, the low noise amplifier 824 may be a single-ended LNA. In this example, one end of the secondary winding of the duplexer 816 is connected to the common loop and the second input of the low noise amplifier is connected to a reference voltage.

FIG. 9 is a schematic block diagram of an embodiment of portions of each of a Front End Module (FEM) 810 and an SOC 812. The front end module 810 includes a plurality of duplexers 816-1 through 816-2 and a plurality of tunable balancing networks 818-1 through 818-2. Each of duplexers 816 is connected to an antenna 826-1 through 826-2. The system-on-chip module 812 includes a processing module 822 and a plurality of detector modules 820-1 through 820-2.

The duplexer 816-1 isolates the first outbound wireless signal 835-1 from the first inbound wireless signal 837-1. The first tunable balancing network 818-1 is tuned via the processing module 822 and the first detector module 820-1 as discussed previously. Similarly, the duplexer 816-2 isolates the second outbound wireless signal 835-2 from the second inbound wireless signal 837-2. The processing module 822 and the second detector module 820-2 tune the second tunable balancing network 818-2 via the second tuning signal 823-2.

In this embodiment, the first inbound and outbound wireless signals may transceive in a first frequency band, and the second inbound and outbound wireless signals may transceive in a second frequency band. For example, each of the first and second frequency bands may be a different one of a 900 MHz frequency band, an 1800 MHz frequency band, a 1900 MHz frequency band, a 2 GHz frequency band, a 2.4 GHz frequency band, a 5 GHz frequency band, a 60 GHz frequency band, and so forth.

Fig. 10 is a schematic block diagram of an embodiment of portions of each of a Front End Module (FEM) 810 and an SOC 812. Front-end module 830 includes a duplexer 838, a balanced network 842, and an Antenna Tuning Unit (ATU)) 840. The system-on-chip module 832 includes a low noise amplifier 852 and a processing module 846. The antenna tuning unit 840 may include a series resistor-capacitor-inductor circuit as shown. The duplexer 838 and balancing network 842 may include similar elements and function similarly to the duplexers and balancing networks discussed throughout this detailed discussion.

In an embodiment of operation, the antenna 834 receives an inbound wireless signal 837 from another communication device and transmits an outbound wireless signal 835. The inbound wireless signal 837 may be received from another wireless communication device according to one or more wireless communication protocols. The outbound wireless signal 835 may be generated by baseband processing, up-conversion, and power amplification in the chunk module 830 and/or in the system-on-chip module 832.

To provide optimal antenna performance, the antenna tuning unit 840 tunes the operational characteristics (e.g., impedance, bandwidth, gain, quality factor, radiation pattern, polarization, efficiency, etc.) of the antenna based on the antenna tuning signal. For example, the antenna tuning unit 840 adjusts a variable resistance and/or a variable capacitance of a series resistor-capacitor-inductor network according to the antenna tuning signal.

To generate the antenna tuning signal 841, the processing module 846 generates a balanced network tuning signal that adjusts the balanced network to substantially achieve a balanced impedance between the antenna and the balanced network. With the impedance between the antenna and the balancing network substantially matched, the processing module 846 estimates the impedance and/or other characteristics of the antenna based on the inbound wireless signal 837, the test signal(s), and/or the component of the outbound wireless signal 835 received by the low noise amplifier 852. For example, the antenna impedance may be estimated based on known properties of the inbound and/or outbound wireless signals and properties of the received inbound and/or outbound wireless signals. As a specific example, if the impedance is lower than expected (e.g., 50 ohms), the gain of the antenna is affected. By determining the gain effect, the impedance can be estimated.

FIG. 11 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 830 and an SOC 832. Portions of the FEM 830 include a power amplifier module (PA) 836, a duplexer 838, a balancing network 842, an Antenna Tuning Unit (ATU) 840, and a common mode sensing circuit. The duplexer 838 includes a transformer (or other structure, such as a frequency selective duplexer 838 and/or an electrically balanced duplexer 838), and the balancing network includes at least a variable resistor and at least one variable capacitor. The common mode sensing circuit includes a pair of resistors connected across the secondary winding of the transformer. Portions of SOC 832 include a peak detector 848, a tuning engine 850 (which may be implemented by processing module 846), a look-up table (LUT) 844, a processing module 846, and a low noise amplifier module (LNA) 852. Alternatively, the peak detector 848 and/or the tuning engine 850 may be within the FEM 830.

In addition to that provided by the sensing circuitry (i.e., resistors), the detector 848, the tuning engine 850, and the balancing network 842, functions to balance the impedance of the balancing network 842 with the impedance of the antenna; the FEM 830 includes an ATU 840. ATU 840 includes one or more fixed passive components and/or one or more variable passive components. For example, ATU 840 may include a variable capacitor-inductor circuit, a variable capacitor, a variable inductor, and/or the like. As another example, ATU 840 may include a tunable resistor-capacitor-inductor network and a tunable capacitor-inductor network. Another embodiment of ATU 840 is provided in fig. 10.

In an embodiment of operation, the PA 836 provides the amplified outbound RF signal to the duplexer 838, which duplexer 838 may include a transformer for isolating the outbound RF signal from the inbound RF signal. The duplexer 838 outputs the amplified outbound RF signal to the ATU 840, which is tuned via settings stored in the LUT 844 to provide the desired antenna matching circuit (e.g., impedance, bandwidth, gain, quality factor, radiation pattern, frequency response, polarization, efficiency, etc.). LUT 884 receives antenna tuning signal 841 from processing module 846 for purposes of determining settings to provide to ATU 840. The LUT 884 then reads the antenna setting 847 based on the antenna tuning signal and provides it to the ATU. ATU 840 outputs the outbound RF signals to an antenna for transmission.

For inbound RF signals, the antenna receives the signal and provides it to ATU 840, which ATU 840 in turn provides it to duplexer 838. The duplexer 838 outputs the inbound RF signal to the LNA 852 and to the common mode sensing circuitry. The functions of the common mode sensing circuit, the detector 848, the tuning engine 850, and the balancing network 842 are to balance the impedance of the balancing network 842 with the impedance of the antenna as previously described.

Processing module 846 is operable to monitor various parameters of FEM 830. For example, processing module 846 may monitor antenna impedance, transmit power, performance of PA 836 (e.g., gain, linearity, bandwidth, efficiency, noise, output dynamic range, slew rate, rise rate, setup time, overshoot, stability factor, etc.), received signal strength, SNR, SIR, adjustments made by tuning engine 850, and so forth. Processing module 846 analyzes the parameters to determine whether the performance of FEM 830 can be further optimized. For example, processing module 846 may determine that adjustments to ATU 840 will improve the performance of PA 836. In this case, processing module 846 accesses LUT 844 to provide desired settings to ATU 840. If this change in ATU 840 affects the impedance balance between ATU 840 and balancing network 842, tuning engine 850 makes the appropriate adjustments.

In an alternative embodiment, processing module 846 provides the functionality and balance adjustments of tuning engine 850 to ATU 840 and balance network 842 to achieve the desired performance of FEM 830. In yet another alternative embodiment, balancing network 842 is fixed and ATU 840 provides the desired adjustments in FEM 830 to achieve impedance balancing and achieve the desired performance of FEM 830.

FIG. 12 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 860 and an SOC 862. The front end module 860 includes a duplexer 870 and a gate balancing network 868. The system-on-chip module 862 includes a low noise amplifier 876 and an LNA bypass circuit 875.

In an embodiment of operation, the duplexer 870 provides electrical isolation between the outbound wireless signals 835 and the inbound wireless signals 837, which outbound wireless signals 835 and 837 transceive via the antenna 864. The gated balancing network 868 establishes an impedance substantially matching the impedance of the antenna when the radio frequency front end is in the third mode and establishes a low impedance relative to the impedance of the antenna when the radio frequency front end is in one of the first and second modes. For example, when the inbound wireless signal is consistent with a Time Division Duplex (TDD) protocol, the first mode corresponds to a receive mode of the radio frequency front end; the second mode corresponds to a transmit mode of the radio frequency front end when the outbound wireless signal is consistent with the TDD protocol; and the third mode corresponds to the radio frequency front end transceiving inbound and outbound wireless signals according to a Frequency Division Duplex (FDD) protocol.

The LNA bypass circuit 875 passes the inbound wireless signal to the LNA when the radio frequency front end is in the first mode and bypasses the LNA when the radio frequency front end is in the second mode. A Low Noise Amplifier (LNA) 876 amplifies the inbound wireless signal to produce an amplified inbound wireless signal.

FIG. 13 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 860 and an SOC 862 for 2G and 3G handset operation. Portions of the FEM 860 include a power amplifier module (PA) 866, a duplexer 870, a gated balancing network 868, and common mode sensing circuitry (R1 and R2). The duplexer 870 includes a transformer (or other structure, such as a frequency selective duplexer and/or an electrically balanced duplexer) and the gated balancing network 868 includes a shorting switch, at least one variable resistor, and at least one variable capacitor. The portion of SOC 862 includes a peak detector 872, a processing module 874, switches (e.g., LNA bypass circuit 875), and a low noise amplifier module (LNA 876). Alternatively, the peak detector 872 and/or tuning engine 874 may be within the FEM 860.

In this embodiment, the duplexer is optimized for Frequency Division Duplexing (FDD), which is used in 3G handset applications. In this mode, the switches of the gated balancing network 868 and the switches of the LNA bypass circuit are open such that the gated balancing network provides an impedance substantially equal to the antenna impedance based on the tuning signal.

In Time Division Duplex (TDD) used in 2G handset applications, the gated balancing network 860 is shorted via a switch. This essentially removes the 3-dB theoretical insertion loss limit and leaves only the implementation loss. Note that for 2G transmission, the LNA bypass circuit switch is off. For 2G reception, the LNA bypass circuit switch is open.

FIG. 14 is a schematic block diagram of an embodiment of portions of each of Front End Module (FEM) 860 and SOC 862 of FIG. 12 in 2G TX mode. In this mode, the LNA bypass circuit switch shorts the LNA 876 and the balancing network switch shorts the balancing network. The primary winding is substantially shorted due to the short circuit on the secondary winding. Thus, the PA 866 is effectively directly connected to the antenna.

Fig. 15 is a schematic block diagram of an embodiment of portions of each of Front End Module (FEM) 860 and SOC 862 of fig. 12 in 2G RX mode. In this mode, the LNA switch is on and the balance network switch is off, thereby shorting the balance network. In this configuration, the transformer function is identical to the function of the transformer balun receiver section.

FIG. 16 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 890 and an SOC 892. Portions of FEM 890 include power amplifier module (PA) 896, duplexer 898, balancing network 900, and common mode sensing circuitry (e.g., R1& R2). The diplexer 898 includes a transformer (or other structure, such as a frequency selective diplexer and/or an electrically balanced diplexer), and the balancing network 900 includes at least one variable resistance and at least one variable capacitor, and may also include an inductor. Portions of the SOC include a peak detector 902, a tuning engine 904 (which may be implemented via a processing module), a detection 906 module, and a low noise amplifier module (LNA) 908. Alternatively, the peak detector 902, the leak detection 906 module, and/or the tuning engine 904 may be within the FEM 890.

In an embodiment of operation, the detection module detects a non-linear function of the power amplifier to produce a detected non-linearity. For example, detection module 906 detects a change in the on-resistance of transistors within PA 896 and/or within balancing network 900. As a more specific example, as the PA 896 output current increases, the on-resistance of transistors within PA 896 and/or within balancing network 900 increases. This increase affects the overall impedance of the balancing network 900. The detection module 906 provides the detected non-linearity to the processing module 904. Alternatively, or in addition, the detection module 906 generates an envelope signal that tracks the variation of the power amplifier based on the non-linearity of the on-resistance and provides the envelope signal to the processing module 904.

The detection module 906 further detects the transmit leakage of the duplexer to produce a detected transmit leakage. For example, the detection module 906 receives common mode signals from the sensing circuits R1 and R1 and it generates monitored transmit leakage from the common mode signals. As mentioned before, the imbalance in the diplexer will produce compensation for the common mode voltage, which is sensed by the sensing circuit.

The processing module generates a coarse tuning signal based on the detected non-linearity and a fine tuning signal based on the detected transmission leakage. The processing module provides the coarse and fine tuning signals to the tunable balancing network 900, which establishes an impedance based on the coarse and fine tuning signals. As such, the coarse and fine feedback loops adjust for imbalance within the duplexer and performance variations (e.g., on-resistance) of the power amplifier and/or the balancing network 900.

Fig. 17 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 910 and an SOC module 912. Portions of the FEM 910 include a power amplifier module (PA) 916, a duplexer 918, a balancing network 920, and sensing circuitry (e.g., R1& R2). The diplexer 918 includes a transformer (or other structure, such as a frequency selective diplexer 918 and/or an electrically balanced diplexer 918), and the balancing network includes at least one variable resistance and at least one variable capacitor. Portions of SOC 912 include a peak detector 922, a processing module 926 (which includes the functionality of a tuning engine), and a low noise amplifier module (LNA) 924. Alternatively, the peak detector 922 and/or the tuning engine may be within the FEM 910.

In an embodiment of operation, the processing module 926 generates and provides a tuning signal to the balancing network 920 based on the imbalance in the duplexer, as previously described. Further, the processing module 926 determines the transmit power level of the outbound wireless signal, which may be accomplished in various ways. For example, the processing module may provide the transmit power level to the power amplifier 916, which the power amplifier 916 uses to establish the transmit power level. As another example, the front end module 910 may include a transmit signal strength indicator that provides a transmit power level 928 to the processing module 926.

The processing module 926 compares the transmit power level 928 to the isolation requirement. For example, when the transmit power level is relatively low (e.g., is a small blocker of the inbound RF signal, and/or the signal strength of the inbound RF signal is relatively high), the transmit leakage with the duplexer will be proportionally lower. In this case, the amount of attenuation of the transmit signal during the duplex period can be reduced and still provide sufficient compensation for transmit leakage. As such, the processing module 926 generates the isolation adjustment signal 921 when the transmit power level is favorable (e.g., relatively low) compared to the isolation requirements.

The processing module 926 sends an isolation adjustment signal 921 to at least one of the duplexer and the tunable balancing network. When receiving the isolation adjustment signal, the duplexer 918 adjusts electrical isolation between the outbound wireless signal and the inbound wireless signal based on the isolation adjustment signal. For example, if the duplexer 918 is a frequency selective duplexer, it adjusts the electrical isolation between the outbound wireless signals and the inbound wireless signals by adjusting one of the one or more filters. As another example, if the duplexer 918 is a balanced diplexer, the balancing network adjusts its impedance based on the isolation adjustment signal as a trade-off between the electrical isolation of the duplexer 918 and the inbound and outbound wireless signals.

Fig. 18 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 810 and an SOC module 812. The front end module 810 includes a power amplifier, a duplexer 816, and a tunable balancing network 818. The system-on-chip module 812 includes a detector module 820 and a processing module 822. Tunable balancing network 818 includes a plurality of resistive elements 841-843, a plurality of capacitive elements 845-847, and a plurality of low voltage switching elements 849-855. Tunable balancing network 818 may further include one or more inductive elements 857 connected to resistive and/or capacitive elements.

In an embodiment of operation, the power amplifier amplifies the upconverted signal to an outbound wireless signal 835. The duplexer 816 is operatively connected to the antenna and provides electrical isolation between the outbound wireless signals and the inbound wireless signals, as described above. The tunable balancing network establishes an impedance that substantially matches the antenna impedance based on the tuning signal 823. For example, the tuning signal may activate (e.g., small-scale or large-scale) one or more low-voltage switching elements of a tunable balancing network, which in turn connects one or more capacitive elements and one or more resistive elements to the duplexer as an impedance balancing load. Accordingly, by activating one or more low voltage switching elements, the impedance of the balancing network 818 is tuned within a given frequency range to substantially match the impedance of the antenna. Note that the balancing network is easily implemented on an integrated circuit by using low voltage switching elements, where the low voltage is lower than the voltage swing (swing) on the balancing network.

In a balanced network, the resistive elements may be resistors, transistor-inductors based on active resistors, and/or switched capacitors. The capacitive element may be a capacitor and/or a varactor. Examples of various resistive elements are shown in fig. 22 and 23.

Fig. 19 is a schematic block diagram of an embodiment of a small signal balancing network 880 comprising a plurality of transistors, a plurality of resistors, and a plurality of capacitors. The selection of resistors included in the balancing network may be controlled by a first set of tuning signal bits (e.g., 10 bits), and the selection of capacitors included in the balancing network may be controlled by a second set of tuning signal bits (e.g., 5 bits).

In an exemplary embodiment of the tunable balancing network, a first resistive element of the plurality of resistive elements is connected in series with a first switching element of the low voltage switching elements; a second resistive element of the plurality of resistive elements is connected in series with a second switching element of the low voltage switching elements. A common node of the second resistive element and the second switching element is connected to a control node of the first switching element. Such a connection is also used for the remaining plurality of resistive elements and the plurality of low voltage switching elements.

Continuing with the exemplary embodiment, a first capacitive element of the plurality of capacitive elements is connected in series with a third switching element of the plurality of low voltage switching elements and a second capacitive element of the plurality of capacitive elements is connected in series with a fourth switching element of the plurality of low voltage switching elements. A common node of the second capacitive element and the fourth switching element is connected to a control node of the third switching element. Such a connection is also used for the remaining plurality of capacitive elements and the plurality of low-voltage switching elements.

In this embodiment, the impedance of the tunable balancing network is tuned according to the small signal of the tuning signal. For example, as the voltage of the tuning signal 823 is adjusted (within a small signal range, such that the transistor is in a linear region), the on-resistance of the transistor is varied such that the series and parallel combination of the on-resistance, the resistors (r 1-Rn), and the capacitors (C1-Cn) provide the desired impedance for the balanced network.

Fig. 20 is a schematic block diagram of an embodiment of a large signal balance network 882 including an RLC (resistor-inductor-capacitor) network and a plurality of transistors. The turning on and off of the transistors provides different combinations of resistors, inductors and/or capacitors of the RLC network to provide the desired impedance of the balancing network. In this example, the transistor has relatively small voltage fluctuation, and thus a lower voltage transistor can be used.

For example, if the balancing network includes four resistor-transistor circuits, four capacitor-transistor circuits, and one or more inductors, the turning on and off of the transistors establishes the impedance of the balancing network. For example, each gate is connected to receive one bit of the 4-bit control signal, with the outermost resistor-transistor circuit on the left receiving the most significant bit, the gate of the next leftmost resistor-transistor circuit receiving the next most significant bit, and so on. Again, the resistor of the leftmost resistor-transistor circuit is R4, the resistor of the next leftmost resistor-transistor circuit is R3, and so on. Thus, for this embodiment, when the 4-bit control signal is 0001, only the rightmost resistor transistor circuit is on, and its resistor R1 provides the resulting resistance. When the 4-bit control signal is 0011, the two rightmost resistor transistor circuits are turned on and the resulting resistance is R1// R2. When the 4-bit control signal is 0111, the three right-most resistor transistor circuits are turned on, and the resulting resistance is R1// R2// R3. When the 4-bit control signal is 1111, all four resistor transistor circuits are turned on, and the resulting resistance is R1// R2// R3// R4. The function of the capacitor side of the balancing network is similar.

As an alternative embodiment, each resistor-transistor circuit and each capacitor-transistor circuit may be independently controlled by a corresponding control signal of one bit. For a four resistor-transistor circuit configuration as described in the preceding paragraph as modified herein, control signal 1000 will result in a resistance of R4; control signal 0100 will result in resistance of R3; the control signal 1010 will result in a resistance of R4// R2; and so on.

As yet another embodiment, a first resistive element of the plurality of resistive elements is connected in series with a first switching element of the plurality of low voltage switching elements; a second resistive element of the plurality of resistive elements is connected in series with a second switching element of the plurality of low voltage switching elements; a first capacitive element of the plurality of capacitive elements is connected in series with a third switching element of the low voltage switching element; and a second capacitive element of the plurality of capacitive elements is connected in series with a fourth switching element of the low voltage switching elements.

In this embodiment, the impedance of the tunable balancing network is tuned according to the tuning signal of the large signal. For example, as the voltage of the tuning signal 823 is adjusted (in a large signal range, such that the transistor is either "on" or "off"), the parallel and/or series combination of the resistor (r 1-Rn), capacitor (C1-Cn), and inductor (if any) provides the desired impedance for the balancing network.

Fig. 21 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 1010 and an SOC module 1012. Portions of FEM 1010 include a power amplifier module (PA) 1014, a duplexer 1016, a balancing network 1018, and an Antenna Tuning Unit (ATU) 840. Duplexer 1016 includes a transformer (or other structure, such as frequency selective duplexer 1016 and/or electrically balanced duplexer 1016). Portions of SOC 1012 include a peak detector 1002 (not shown), a processing module 1020 (which performs the functions of a tuning engine), and a low noise amplifier module (LNA) 1022. Alternatively, the peak detector 1002 and/or the tuning engine may be within the FEM 1010.

The balancing network 1018 includes an RLC network having a plurality of variable resistors, a plurality of variable capacitors, and at least one inductor as shown. In this embodiment, the balancing network 1018 may be tuned to provide a wide range of impedances to enable better matching of the impedance of the antenna. Furthermore, the balancing network has a wide tuning range for a desired Voltage Standing Wave Ratio (VSWR) (e.g., 3: 1), particularly when tuned in conjunction with a tuning ATU.

FIG. 22 is a schematic block diagram of an embodiment of impedances of resistor-transistor (R-T) circuits of a balancing network. The capacitor corresponds to a parasitic capacitance of the transistor. Since the R-T circuit includes a true passive resistor, it contributes to a theoretical limit of 3 dB on insertion loss.

FIG. 23 is a schematic block diagram of another embodiment of the impedance of the resistor-transistor (R-T) circuit of the balancing network. In this embodiment, the R-T circuit includes an inductively-decaying common-source transistor. As such, it is an active electron and does not contribute to the 3 dB theoretical limit on insertion loss. Thus, the only loss caused by the balanced network is implementation loss.

In particular, the R-T circuit provides an active gyrator within a balanced network by using active devices rather than passive resistors. With an active gyrator, the TX insertion loss does not change since it depends on the value of the resistance, but the RX noise factor (shaping) is enhanced since the noise associated with the resistance is reduced in an active implementation. For example, in one possible implementation of a capacitor as the input impedance of a common gate MOSFET, the resistance is given by the formula R = l/gm. The noise power spectral density of such a resistor is 4KT γ/gm or 4KT γ R, where K is the boltzmann constant, T is the kelvin temperature, and γ is a thermal noise parameter and is a function of the process. On the other hand, the passive resistor has a fixed noise power spectral density given by 4 KTR. For the most recent deep sub-micron technology, the value of γ is less than 1, so that the resistor using the common gate MOSFET generates less noise for the same resistor.

Fig. 24 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 1010 and an SOC module 1012. The front end module 1010 includes a duplexer 816 and a balancing network 1030. The system-on-chip module 812 includes a detector module 820 and a processing module 822. The balancing network 1013 includes an impedance up-converter 1032 and a baseband impedance circuit 1034.

In an embodiment of operation, the baseband impedance circuit generates an impedance based on the tuning signal 823. At a desired frequency (e.g. f)_LOOr f_RF) The clocked impedance up-converter 1032 up-converts the baseband impedance to a radio frequency impedance. When tuned, the radio frequency impedance of the balancing network 1013 substantially matches the impedance of the antenna 826 within a given frequency band of operation.

Fig. 25 is a schematic block diagram of an embodiment of a balancing network 1030, the balancing network 1030 comprising a plurality of transistors (e.g., a multi-phase transistor switching network as an up-conversion module) and a plurality of baseband impedances (Z)_BB(s)) 396-402. Each baseband impedance may include a plurality of capacitive elements, a plurality of resistive elements, and a plurality of switching elements. For each baseband impedance, one or more capacitive elements and/or one or more resistances are connected together based on the tuning signal to produce the baseband impedance. Note that the resistive elements may be resistors, transistor-inductor based active resistors, and/or switched capacitors, and the capacitive elements may be capacitors and/or varactors.

In an embodiment of operation, the balancing network receives the tuning signal 832 and adjusts the baseband impedance accordingly. The transistors are switched using the four-phase clock generated by the clock generator 404 of fig. 26. As shown in fig. 26, the clock generator 404 generates four clock signals each having a duty cycle of 25% and sequentially offset by 90 °. The clock signal has a frequency related to the carrier frequency of the inbound and/or outbound RF signals and can be adjusted to better track the carrier frequency.

Fig. 27 illustrates frequency conversion of baseband impedance to RF impedance. As shown, the baseband impedance is tuned to have a desired impedance at DC (e.g., 50 ohms). The up-conversion module modulates the baseband impedance to +/-RF frequency.

Fig. 28 is a schematic block diagram of another embodiment of a balancing network comprising two impedance up-converters 1042, 1044 and two corresponding baseband impedances (Zbb 1046, 1048). Each impedanceThe up-converter being operated at a desired frequency (e.g. f)_{RF_TX}And f_{RF_TX}) And (6) timing. For example, the upconverter 1042 may be clocked at a frequency within a first frequency band and the upconverter 1044 may be clocked at a frequency within a second frequency band.

As another embodiment, the first frequency band of operation is associated with a transmit frequency band of a wireless communication protocol and the second frequency band of operation is associated with a receive frequency band of the wireless communication protocol. As another embodiment, the first frequency band of operation is associated with a frequency band of a first wireless communication protocol and the second frequency band of operation is associated with a frequency band of a second wireless communication protocol. Note that each combination of impedance up-converters 1042, 1044 and their corresponding baseband impedance may be implemented in a similar manner as previously discussed with reference to fig. 27.

Figure 29 is a schematic block diagram of a front end module including a duplexer 816 and a balancing network 818. The duplexer 816 includes a first winding 871, a second winding 873, a third winding 875, and a compensation module 877. The windings are connected to have five nodes: a first node for connecting the antenna to the first winding; a second node for receiving the outbound wireless signal and for connecting the first winding to the second winding; a third node for connecting the second winding to the balancing network; a fourth node operatively connected to output a first signal component corresponding to the inbound wireless signal from the third winding; and a fifth node for connection to output a second signal component corresponding to the inbound wireless signal from the third winding.

In an embodiment of operation, the duplexer 816 is between the first and second windings 871&873 receives the outbound wireless signal 835. The current of the outbound wireless signal 835 is split between the first and second windings, which is denoted as I_TX-ANTAnd I_TX-BN. If the impedance of the balancing network 818 matches the impedance of the antenna 826, the transmit antenna current and the balancing network current will be substantially equal. Since these currents are substantially equal, they effectively cancel each other with respect to the third winding, such that the third winding has a negligible TX leakage component. However, if the network is balanced818, and the impedance of the antenna 826 are unbalanced, there will be non-negligible transmission leakage current across the third winding.

The series combination of the first winding 871 and the second winding 873 receives an inbound wireless signal from the antenna 826, the inbound wireless signal having a current component I_RX. Due to the high output impedance of the PA, the series connected first and second windings are magnetically connected and receive current to the third winding 875 to generate the inbound wireless signal 837, there will be a transmit leakage current on the third winding if there is an imbalance between the impedance of the antenna 826 and the balancing network 818.

Even if the impedances of the balancing network 818 and the antenna 826 are substantially equal, there may be an imbalance within the duplexer that causes transmit leakage current to appear on the third winding. The imbalance may be caused by an imbalance between the parasitic capacitances of the windings. In this example, the compensation module 877 is used to compensate for electrical isolation between the first and second signals and the outbound wireless signal due to imbalance within the duplexer 816.

FIG. 30 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 930 and an SOC 932. Portions of FEM 930 include a power amplifier module (PA) 936, a duplexer 816, and a balancing network 818. The duplexer 816 includes a transformer having three windings 871, 873 & 875, and a parasitic capacitance Cp 1& Cp 2. The compensation module 877 includes compensation capacitors Ccl & Cc 2. Portions of SOC 932 include a peak detector, a processing module (which includes the functionality of a tuning engine), and a low noise amplifier module (LNA) 940. Only LNA 940 is shown.

In this embodiment, the compensation capacitor Ccl & Cc2 compensates for the mismatch of parasitic capacitances (e.g., Cp1 and Cp 2) that may cause a mismatch between the main windings (e.g., L1 and L2). As such, the compensation capacitors (Ccl and Cc 2) are selected such that Cpl + Ccl = Cp2 + Cc 2. By adding the compensation capacitor, the isolation bandwidth of the duplexer 932 is larger than it would be without the compensation capacitor, and further reduces transmit leakage.

FIG. 31 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 930 and an SOC 932. Portions of FEM 930 include a power amplifier module (PA) 936, a duplexer 816, and a balancing network 818. The duplexer 816 includes a transformer having three windings 871, 873 & 875, and a parasitic capacitance Cp 1& Cp 2. The compensation module 877 includes compensation capacitors Ccl & Cc2, a detection module 891, and a processing module 893. Portions of SOC 932 include a peak detector, a processing module (which includes the functionality of a tuning engine), and a low noise amplifier module (LNA) 940. Note that the detection module 891 and/or the processing module 893 may be in the SOC 932.

In this embodiment, the compensation capacitors Ccl & Cc2 may be adjusted to compensate for the mismatch in parasitic capacitances (e.g., Cp1 and Cp 2). As such, the compensation capacitors (Ccl and Cc 2) are adjusted such that Cpl + Ccl = Cp2 + Cc 2. To determine the set point of the compensation capacitor, the detection module detects an imbalance between the first and second parasitic capacitances. This operation may be accomplished by: detecting a transmission leakage on the third winding; determining a transmission leakage fraction for an imbalance between the impedances of the balanced network and the antenna; and estimating (or calculating) a portion of the transmission leakage due to the parasitic capacitance imbalance.

The processing module determines capacitances of the first and second compensation capacitors based on an imbalance between the first and second parasitic capacitances. The processing module then generates a first capacitance setting value based on the determined capacitance of the first compensation capacitor and a second capacitance setting value based on the determined capacitance of the second compensation capacitor.

Fig. 32 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 950 and an LNA 952. Portions of FEM 950 include a power amplifier module (PA) 954, a duplexer 956, and a balancing network 958. The duplexer 956 includes a transformer having three windings and parasitic capacitances (Cp 3 and Cp 4). LNA 952 includes an input transistor having a parasitic capacitance (Cp), a bias transistor, a common mode isolation circuit, and a load impedance (Z). The common mode isolation circuit includes an inductor (L3) as a common mode damping inductor and first and second capacitors. In an embodiment, the first and second capacitors may be parasitic capacitors Cp3 & Cp4 of the LNA. In another embodiment, the first and second capacitors may be connected in parallel with the parasitic capacitor.

Transmission leakage is further reduced due to the inclusion of common mode isolation compensation circuitry in LNA 952. As such, the common mode isolation circuit of LNA 952 further reduces the adverse effects of transmit leakage even though the balancing network 15 and compensation module are unable to fully compensate for the imbalance.

FIG. 33 is a schematic block diagram of an embodiment of an equivalent circuit 20 of a portion of each of the Front End Module (FEM) and the LNA of FIG. 32. The figure shows how common mode isolation is improved. The unbalanced current, which is connected to the secondary winding (L) through the parasitic capacitances (Cp 3 and Cp 4) of the transformer, is connected to separate the tank circuit formed by the inductor (L3) and the parasitic capacitance of the input transistor. The tank circuit provides a high differential impedance in addition to a low common mode impedance, thereby suppressing imbalance.

Fig. 34 is a schematic block diagram of an embodiment of a transformer 980 of a duplexer. The transformer comprises a primary winding (L1 & L2) and a secondary winding (L3). Each main winding has the same number of turns. The number of turns of the secondary winding may be the same or different from the primary winding. The direction of the windings is as shown.

Fig. 35 is a diagram of an embodiment of a transformer implementing an integrated circuit of 4 thick metal layers on an IC package substrate and/or a printed circuit board. The primary winding is on the top two layers and the secondary winding is on the two lower layers. The secondary windings on the third and fourth layers may be connected in series or in parallel.

Fig. 36 is a diagram of another embodiment of a transformer implementing a 3 thick metal layer IC on an IC package substrate and/or printed circuit board. The primary winding is on the top layer, interconnected using the next layer, and can be rotated 90 ° with respect to the direction of the secondary winding. The secondary winding is on the second and/or third lower layer.

Fig. 37 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 990 and an LNA 992. The front end module 990 includes a power amplifier 994, a duplexer 996, a balancing network 1000, and a tone injection module 998. The system-on-chip module 992 includes the processing module 1004 and may also include other components as described previously.

In the event that the transmit noise and/or receive band noise in the receive path is below the noise floor of the low noise amplifier, further compensation of the transmit noise and/or receive band noise may be detected and subsequently compensated for by the included tone injection module 998. For example, the tone injection module 998 (which may be an oscillator, phase locked loop, direct digital frequency synthesizer, etc.) generates a tone 995 having a carrier frequency substantially similar to the carrier frequency of the inbound wireless signal in the first mode. A tone 995 is injected into the outbound wireless signal received by duplexer 996, which may be accomplished by adding the tone to the output of the PA or to the input of the PA.

A duplexer 996 operatively connected to the antenna provides electrical isolation between the outbound wireless signals and the combined signals of the audio and inbound wireless signals in the first mode. In the second mode, the duplexer 996 provides electrical isolation (e.g., no tones are present) between the outbound wireless signals and the inbound wireless signals. The balancing network 1000 establishes an impedance that substantially matches the impedance of the antenna based on the tuning signal 997.

The processing module 1004 determines the magnitude of the tonal components of the combined signal. This can be done at baseband, intermediate frequency or at RF. The processing module 1004 then corrects the amplitude of the tone component to an inbound band-isolated signal (e.g., a measure of receive band noise and/or transmit noise on the receive path). The processing module 1004 then adjusts the baseband processing of the down-converted representation of the combined signal based on the inbound band isolation. For example, since the inbound band isolated signal is a measure of receive band noise and/or transmit noise on the receive path, these noise components may be digitally filtered during the baseband conversion process.

The processing module 1004 may be further to validate the first mode when the noise of the inbound wireless signal is favorably compared to a noise threshold (e.g., below a noise floor of the LNA). Alternatively, the processing module enables the second mode when the noise of the inbound wireless signal is disadvantageously compared to a noise threshold, wherein the tone injection module is disabled in the second mode.

The processing module 1004 may still further be used to generate the tuning signal 997 based on the electrical performance characteristics of the duplexer 996 as previously discussed. The processing module then sends the tuning signal 997 to the balancing network 1000, and the balancing network 1000 adjusts the impedance based on the tuning signal 997. The processing module then adjusts the tuning signal based on the inbound band isolation to further compensate for noise on the receive path.

FIG. 38 is a schematic block diagram of another embodiment of portions of each of a Front End Module (FEM) 990 and an SOC 992. Portions of the FEM 990 include a power amplifier module (PA) 994, a duplexer 996, a balancing network 1000, a tone injection module 998, and sensing circuitry (e.g., R1& R2). The duplexer 996 includes a transformer (or other structure, such as a frequency selective duplexer and/or an electrically balanced duplexer) and the balancing network 1000 includes at least one variable resistor and at least one variable capacitor. The SOC 992 portion includes a detector 1002, a processing module 1004 (which performs the functions of a tuning engine), a baseband processing unit 1008, and a low noise amplifier module (LNA) 1006. Alternatively, the peak detector 1002 and/or the tuning engine may be within the FEM 990.

In an embodiment of operation, the sensing circuit, tuning engine, detector 1002, and balancing network 1000 are used to balance the impedance of the balancing network and antenna as previously discussed. In many cases, this will reduce the Transmitter (TX) and/or Receiver (RX) noise in the receiver band below the noise reference of the LNA 1006 or equivalent to the noise reference of the LNA 1006. Since TX and/or RX noise is at or below the noise reference, it is difficult to track, which is detrimental to tracking the impedance of the antenna.

To improve the skyTracking of line impedance, tone injection 998 module injects tones into the receiver band (e.g., a cos (ω)_{RX_RF}(t))). Duplexer 996 attenuates RX tones differently than TX signals because RX tones are in the RX band and duplexer 996 and balancing network 1000 are tuned for the TX band. As such, a leakage signal that can be easily detected is generated on the RX side of the duplexer 996 (e.g., on the secondary winding of the transformer).

The RX tone-based leakage signal is propagated through the receiver section until it is converted to a baseband signal. At baseband, the tone amplitude is a measure of the RX band isolation. From the measurement of the RX strip isolation, the impedance of the antenna can be determined. As the antenna impedance changes, the antenna tuning unit and/or the balancing network 1000 may be adjusted to track the impedance of the antenna. Note that tones can be easily removed at baseband.

In an embodiment of operation, the power amplifier amplifies the upconverted signal to generate an outbound wireless signal. The tone injection module generates tones having a carrier frequency substantially similar to a carrier frequency of the inbound wireless signal, wherein the tone signal is combined with the outbound wireless signal. The duplexer 996 provides electrical isolation between the outbound wireless signals and the combined signals of the tones and inbound wireless signals. The balancing network establishes an impedance that substantially matches the impedance of the antenna based on the tuning signal.

The duplexer 996 provides an inbound wireless signal to the low noise amplifier 1006, where the inbound wireless signal includes an inbound RF signal component and an acoustic component. The LNA amplifies the combined signal to produce an amplified combined signal, which is converted to a baseband or near baseband signal by the down-conversion module 1007.

The processing module generates the tuning signal based on the electrical performance characteristics of the duplexer as previously described. The processing module then converts the baseband or near baseband signal to a baseband tone signal and a baseband inbound signal. The processing module then determines inbound band isolation based on the baseband signal (which is a measure of RX band isolation) and adjusts the tuning signal based on the inbound band isolation. The processing module may also adjust the baseband inbound signal based on the inbound frequency band isolation to compensate for transmit noise in the inbound frequency band.

In the foregoing drawings, some elements have common or similar designations and have the same or different reference numerals. For these elements (e.g., FEM, SOC, duplexer, balanced network, etc.), the elements may include any combination of features and/or characteristics of elements having various names and/or different reference numerals.

As may be used herein, the term "substantially" or "about" provides an industry-accepted tolerance to the corresponding term. Such an industry-accepted tolerance ranges from less than 1% to 50% and corresponds to, but is not limited to, component values, integrated circuit process fluctuations, temperature fluctuations, rise and fall times, and/or thermal noise. Such inter-component relativity ranges from a few percent difference to a large number of differences. As may be used herein, the terms "operatively connected," "coupled," and/or "connected," include direct connection between the two and/or indirect connection through an intermediary (e.g., including, but not limited to, a component, element, circuit, or module), where the intermediary does not alter the information in the signal for indirect connection but may adjust its current level, voltage level, and/or power level. As further used herein, inferred coupling (i.e., where one element is coupled to another element by inference) includes direct and indirect coupling between two elements in the same manner as "operably coupled". As further used herein, the term "operatively" or "operatively connected" means that a component includes one or more power connections, inputs, outputs, etc. for performing one or more associated functions when activated and may further include inferring connections to other components. As further used herein, the term "associated with … …" includes direct or indirect connection to discrete components and/or embedding of one component within another component. As used herein, the term "compares favorably", indicates that a comparison between two or more elements, signals, etc., provides a desired relationship. For example, when the desired relationship is that signal 1 has a greater amplitude than signal 2, favorable comparison results may be obtained when the amplitude of signal 1 is greater than the amplitude of signal 2 or the amplitude of signal 2 is less than the amplitude of signal 1.

Although the transistors in the figure(s) described above are shown as Field Effect Transistors (FETs), as one of ordinary skill in the art will appreciate, the transistors may be implemented using any type of transistor structure, including, but not limited to, bipolar, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), N-well transistors, P-well transistors, enhancement mode, depletion mode, and zero Voltage Threshold (VT) transistors.

The invention also describes the performance of particular functions and relationships by means of method steps. The boundaries and sequence of these functional blocks and method steps have been specifically defined for convenience of description. Their boundaries and sequence may be redefined as appropriate to perform the specified functions and relationships. These redefinitions of boundaries and order are intended to fall within the scope and spirit of the present invention.

The present invention has been described, at least in part, with respect to one or more embodiments. Embodiments of the invention are used herein to illustrate the invention, an aspect thereof, a feature thereof, a concept thereof, and/or an embodiment thereof. The physical bodies, articles of manufacture, machines and/or processes of an appliance embodied by the invention can include one or more aspects, features, concepts, embodiments, etc. described with reference to one or more embodiments discussed herein.

The invention has also been described above with the aid of functional blocks illustrating some important functions. For convenience of description, the boundaries of these functional building blocks have been defined specifically herein. When these important functions are implemented properly, varying their boundaries is permissible. Similarly, flow diagram blocks may be specifically defined herein to illustrate certain important functions, and the boundaries and sequence of the flow diagram blocks may be otherwise defined for general application so long as the important functions are still achieved. Variations in the boundaries and sequence of the above described functional blocks, flowchart functional blocks, and steps may be considered within the scope of the following claims. Those skilled in the art will also appreciate that the functional blocks described herein, and other illustrative blocks, modules, and components, may be implemented as discrete components, special purpose integrated circuits, processors with appropriate software, and the like.

Claims (10)

1. A front-end module, comprising:

a duplexer, the duplexer comprising:

a first winding;

a second winding;

a third winding;

first to fifth nodes, wherein:

the first node is for operatively connecting an antenna to the first winding;

the second node is operable to receive an outbound wireless signal and operatively connect the first winding to the second winding;

the third node operatively connects the second winding to a balancing network;

a fourth node is operably connected to output a first signal component corresponding to an inbound wireless signal from the third winding; and

a fifth node is operably connected to output a second signal component corresponding to an inbound wireless signal from the third winding,

wherein the first and second signal components are electrically isolated from the outbound wireless signal; and

a compensation module operatively connected to at least one of the first, second and third windings and operable to compensate for electrical isolation between the first and second signals and the outbound wireless signal; and

a balancing network operable to establish an impedance that substantially matches the antenna impedance.

2. The front-end module of claim 1, wherein the compensation module comprises:

a first compensation capacitor connected in parallel with a first parasitic capacitance formed between the first and third windings; and

a second compensation capacitor connected in parallel with a second parasitic capacitance formed between the second and third windings, wherein a sum of capacitances of the first compensation capacitor and the first parasitic capacitance is substantially equal to a sum of capacitances of the second compensation capacitor and the second parasitic capacitance.

3. The front-end module of claim 1 or 2, further comprising:

a detection module operatively connected for detecting an imbalance between the first and second parasitic capacitances;

a processing module operatively connected to:

determining the capacitance of the first and second compensation capacitors based on an imbalance between the first and second parasitic capacitances;

generating a first capacitance setting value based on the determined capacitance of the first compensation capacitor; and

generating a second capacitance setting value based on the determined capacitance of the second compensation capacitor;

a first compensation capacitor comprising a first capacitor network set based on the first capacitance setpoint; and

a second compensation capacitor comprising a second capacitor network set based on the second capacitance setpoint.

4. The front-end module of claim 1, further comprising:

a low noise amplifier operably connected to amplify the inbound wireless signal, wherein the low noise amplifier includes a common mode isolation compensation circuit.

5. The front-end module of claim 4, wherein the common-mode isolation compensation circuit comprises:

a first capacitor connected to the first input transistor;

a second capacitor connected to the second input transistor; and

a common mode degeneration inductor connected to a common node of the loop and the first and second capacitors.

6. The front-end module of claim 1, wherein the diplexer comprises:

the first and second windings formed on a first double-thick metal layer of a substrate; and

the third winding is formed on the second double-thick metal layer of the substrate.

7. The front-end module of claim 1, wherein the diplexer comprises:

the first and second windings formed on a first thick metal layer of a substrate; and

the third winding formed on at least a second thick metal layer of the substrate, wherein the first and second windings have a rotation of substantially ninety degrees with respect to the third winding.

8. A radio frequency front end, comprising:

a power amplifier operably connected to amplify the upconverted signal to generate an outbound wireless signal;

a duplexer operatively connected to an antenna, wherein the duplexer operatively provides electrical isolation between the outbound wireless signals and the inbound wireless signals;

a balancing network operatively connected to the duplexer and operative to establish an impedance substantially matching the antenna impedance;

a low noise amplifier operably connected to amplify the inbound wireless signal, wherein the low noise amplifier includes a common mode isolation compensation circuit that compensates for attenuation of common mode isolation by parasitic capacitances of the duplexer.

9. The front-end module of claim 8, wherein the common-mode isolation compensation circuit comprises:

a first capacitor connected to the first input transistor;

a second capacitor connected to the second input transistor; and

a common mode degeneration inductor connected to a common node of the loop and the first and second capacitors.

10. A radio frequency front end, comprising:

a power amplifier operably connected to amplify the upconverted signal to generate an outbound wireless signal;

a duplexer operatively connected to an antenna, wherein the duplexer operatively provides electrical isolation between the outbound wireless signals and inbound wireless signals;

a balancing network operatively connected to the duplexer and operative to establish an impedance substantially matching the antenna impedance; and

a compensation module operable to compensate for attenuation of electrical isolation between the first and second signals and the outbound wireless signal caused by parasitic capacitance of the duplexer.